JP2000032475A - Dynamic image reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display images of another channel at a part of the screen of a main channel as a sub screen, with an economical configuration. SOLUTION: This device is provided with a demultiplex circuit 103 for fetching the encoded image data of the main channel from the encoded image data of the plural channels, a decoder 107 for decoding the fetched encoded image data, the demultiplex circuit 113 for taking out the encoded image data of a sub channel, a pre-decoder 117 for fetching only the data part of an I picture in the taken-out encoded image data, a buffer 119 for storing the output data of the pre-decoder, a variable length decoder 120, an inverse DCT transformer 121, a thinning circuit 122 for thinning decoded data, a memory 123 for temporarily storing down-sampled image data and an image output circuit 114 for combining the decoded data of a main screen and the data of the sub screen.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a moving picture reproducing apparatus,
More specifically, the present invention relates to a moving image reproducing apparatus that reproduces information-compressed moving image signals of a plurality of channels and displays a plurality of images on a screen of a display device by dividing display areas.

[0002]

2. Description of the Related Art In recent years, in order to provide a high-quality moving image signal to a limited transmission path capacity and a storage medium, compression coding of the moving image signal has been used. Have been. For example, in the compression of moving images and audio signals, MPEG (Moving Pictures Expert Groove) is used.
up ISO The above IEC 11172 and 13818) methods have been standardized. Further, image reproducing apparatuses compatible with these compression methods have been developed.

A typical moving picture signal reproducing apparatus selectively reproduces and displays a moving picture signal of an arbitrary channel. However, when a moving image signal of a certain channel is reproduced and displayed, a moving image signal of another channel is superimposed on a part of the display screen, that is, the display area is divided and reproduced and displayed. Have to be displayed on the same display screen. FIG. 2 shows an example of a screen configuration for displaying a plurality of channels. In this example, a moving image of channel 1 is displayed on the main part of the screen, and the display area is reduced to 1/8 of the upper right part of the screen.
2 is displayed. As described above, in order to simultaneously display two types of moving images on the same screen, it is necessary to decode coded moving image data of two channels in parallel, and the decoding device includes two similar devices. It must be configured to be juxtaposed.

Further, in order to simultaneously reproduce and display moving image signals of a plurality of channels, a conventional reproducing apparatus is required to have the structure shown in FIG.
As shown in (1), a synchronizing circuit including a playback device corresponding to the number of channels to be displayed and an image memory for synchronizing a display image of each channel is required.

FIG. 3 shows a configuration example of a conventional moving picture signal reproducing apparatus for displaying moving pictures of a plurality of channels. In this example, 2
13 shows an example of a moving image reproducing apparatus in which moving images of channels are simultaneously displayed on the same screen. The signal received by tuner 301 is demodulated by demodulator 302. afterwards,
The demultiplexing circuit 303 selects a moving image signal of a main channel. The demultiplexing circuit 303 is, for example, a PID (Prog
ram ID) filter 304, depacketizer 305, descrambler 306, and the like. Demultiplexing circuit 3
03 is input to the MPEG image data decoder. Also, based on the reference obtained by the program clock reference filter 314, P
The clock 1 is generated by the LL circuit 315, and the clock 1 becomes a clock signal for operating the MPEG decoder 307. The MPEG decoder internal 307 includes a video bit stream verifier buffer 308 and a variable length decoder 30.
9, an inverse DCT converter 310, a motion compensation circuit 312, an image storage frame memory 311, and an image signal output circuit 313.

On the other hand, the encoded moving image data of the sub-screen is
Similarly, a channel is selected by the demultiplexing circuit 316,
The encoded moving image data is input to the MPEG decoder 317. The decoder 317 performs decoding based on the clock signal generated by the program / clock reference filter 314 and the PLL 319 and outputs image data.

Since the output image data from the second decoder 317 is the full size of the screen, downsampling for forming the sub-screen is performed by the thinning circuit 320 to obtain the size of the sub-screen. After that, the moving image data of the sub-screen is synchronized with the moving image playback time of the main screen, so that it is stored in the synchronization memory 321 and then read out together with the playback of the main screen, and is partially stored on the display screen. Is displayed.

With the above arrangement, a plurality of MPEG image data decoders are provided, and the decoded image data of the sub-screen is read out at the same time as the main image output timing. It is possible to display an image of a different channel as a sub screen on a part thereof.

[0009]

In the above-described moving picture reproducing apparatus, a reproducing apparatus capable of displaying moving pictures of two channels on the same screen has been shown. However, the moving picture data of each channel is decoded. The same circuit configuration as the decoder for the main channel is also required for the image data decoder for the channel serving as the sub-screen, and the circuit scale becomes large. In addition, a memory for temporarily storing image data is required in the MPEG decoder, and having a plurality of decoders also requires a plurality of image storage memories, which is not economical.

A main object of the present invention is to provide a moving picture reproducing apparatus which displays an image of another channel as a sub-screen on a part of a screen of a main channel with a simple configuration. In particular, it is an object of the present invention to provide a moving image reproducing apparatus in which the number of necessary frame memories is reduced.

[0011]

In order to achieve the above object, a moving picture reproducing apparatus according to the present invention includes a moving picture which has been subjected to intra-frame coding and motion-compensated inter-frame coding such as MPEG coding. A moving image reproducing apparatus that receives encoded image data strings of a plurality of channels composed of image data and reproduces an image, wherein the demultiplexing unit separates the encoded image data strings of the plurality of channels, A moving image reproducing apparatus comprising: a plurality of decoding units for decoding each of the encoded image data strings; and an image combining circuit for compressing at least one decoded signal of the plurality of decoding units on a screen and combining the compressed image with an output of another decoding unit. In the apparatus, a decoding unit that performs the screen compression includes a pre-decoder that extracts only intra-frame encoded data in the received encoded image data, and a frame that is extracted from the pre-decoder. A buffer memory for temporarily storing inner encoded data, a decoding unit for decoding intra-frame encoded data in the buffer memory, a thinning unit for thinning out the decoded data, that is, a downsampling unit for downsampling, And a memory for temporarily storing the obtained image data.

In a preferred embodiment of the present invention, the coded image data sequence is an coded image data sequence of the MPEG system, and the intra-frame coded data is data relating to an I picture of the coded image data of the MPEG system.

In the following description of the embodiment, an example will be described in which each functional unit is configured by a dedicated circuit. However, each functional unit can be realized by a program process using a CPU.

[0014]

<First Embodiment> FIG. 1 is a block diagram showing the configuration of a first embodiment of a moving picture reproducing apparatus according to the present invention. The present embodiment constitutes a moving image reproducing apparatus for displaying moving images of two channels simultaneously on the same screen. The received encoded image data sequence is encoded image data of the MPEG system. The signal received by tuner 101 is demodulated by demodulator 102. From the demodulated multiplexed data, a demultiplexing circuit 103 selects a moving image signal of a main channel of a desired screen. The demultiplexing circuit 103 includes, for example, the program ID filter 104, the depacketizer 10
5, a descrambler 106 and the like. The encoded image data obtained by the demultiplexing circuit 103 is input to an image data decoder 107. Further, the clock 1 is generated by the PLL circuit 116 based on the reference obtained by the filter 115. Clock 1 is a clock signal for operating the decoder.

The decoder 107 includes a video buffering verifier buffer 108, a variable length decoder 109,
It comprises an inverse DCT converter 110, a motion compensation circuit 112, an image storage frame memory 111, and an image signal output circuit 113. The above-mentioned components are the conventionally known MPEG
It is substantially the same as the reproducing apparatus of the coded image data of the system.

On the other hand, the encoded moving image data of the sub-screen is
The demultiplexing circuit 113 selects a moving image signal of a channel that becomes a desired sub-screen, and applies the selected moving image signal to the decoder 117. The configuration operation of the demultiplexing circuit 113 is the same as that of the demultiplexing circuit 103. The coded image signal of the selected sub-screen is sent to pre-decoder 118. The pre-decoder 118 extracts only the information relating to the I picture in the coded image signal of the sub-screen and stores it in the buffer 119. The I picture is M
In PEG coding, a screen in which all of the screens are intra-coded in a screen structure in which an intra-frame coded screen based on information closed only within the screen is periodically inserted. The variable-length decoder 120 performs variable-length decoding on the encoded data read from the buffer 119, and the inverse DCT transform circuit 121 performs an inverse DCT transform to decode an I-picture image. The decoded image is down-sampled by the thinning-out circuit 122 to become the size of the sub-screen, and is stored in the image storage memory 1.
23. The memory 123 stores the image of the sub screen as 2
It has a capacity to store images (two frames), and always secures image data for one completed sub-screen. When the image data of the decoder 107 is displayed on the main screen, the image synthesizer 114 switches to an I-picture image completed from the memory 123 when in the sub-screen area to form an image. With the above-described configuration, the image of the different channel is displayed as a sub-screen on a part of the image of the main channel on the same screen at the same time.

FIG. 4 shows an outline of the processing timing of the main part in the first embodiment. The output of the demultiplexing circuit 103 is that the encoded image data of the main channel is an I1 picture,
The pictures are transmitted to the decoder 107 in the order of a P picture, a B picture, a B picture, and an I2 picture (hereinafter, picture words are omitted for simplicity). At this time, the operations of the variable length decoder 109 and the IDCT 110 are based on the input I1, P, B, B,
The images of I2 are sequentially decoded.

On the other hand, the coded image data of the channels constituting the sub-screen are inputted in the order of I'1, P ', B', B ', I'2. 2 information, and the variable length decoder 120
The data is transmitted to the CT circuit 121. Variable length decoder 12
The 0 and inverse DCT section 121 decodes information of only the extracted I 'picture and restores an image. The decoded image information is temporarily stored in the buffer memory 123 after being decimated by the decimating circuit 122. The operations of the variable length decoder 120 and the inverse DCT circuit 121 are performed at the time of decoding P ′ and B ′ by I ′
Only takes a long time to decode and write to memory. After completely storing the information of the I′1 picture written in the memory, the image synthesizing circuit 114 displays the I′1 picture as a sub-screen.

Comparing this embodiment with the moving picture reproducing apparatus shown in FIG. 3, it can be seen that the number of circuits for decoding the image of the sub-screen is greatly reduced. That is, in the example shown in FIG. 3, a complete decoder is required for decoding the image data of the sub-screen, and the components such as the VBV buffer, the motion compensation circuit 312, and the frame memory 311 are required. In the moving picture reproducing apparatus, the decoder 117
Compensation circuit 312, frame memory 31
No 1 is needed. The moving picture reproducing apparatus of the present embodiment displays only an I-picture image on a sub-screen, and cannot display P-picture and B-picture image data that should be displayed. Therefore, although the moving image on the sub-screen has a frame-like operation, it can function sufficiently to confirm the program contents.

In the above embodiment, when the main picture starts displaying a P picture after displaying the decoded I'0 picture on the sub picture, the display of the I1 picture of the sub picture is started. As can be understood from the outline of the processing timing described above, the variable-length decoder 120 and the inverse DCT circuit 121 for decoding the image data constituting the sub-screen have a processing time that does not perform the decoding processing of the P picture or the B picture as compared with the normal processing. Can be applied. This makes it possible to reduce the scale of the variable length decoder 120 and the inverse DCT circuit 121. Further, the variable length decoder 120 and the inverse DCT circuit 121 used for decoding the image data of the sub-screen are used.
Can be performed between the decoding processes of the main screen, and the variable length decoder and the inverse DCT circuit can be shared.

<Embodiment 2> FIG. 5 is a block diagram showing the configuration of a second embodiment of the moving picture reproducing apparatus according to the present invention. This embodiment also shows a case where moving images of two channels are simultaneously displayed on the same screen.

The signal received by tuner 501 is applied to demodulator 5
02 is demodulated. After that, the moving image signal of the main channel of the desired screen is selected by the demultiplexing circuit 503.
The demultiplexing circuit 503 includes, for example, a program ID filter 504, a depacketizer 505, and a descrambler 50.
6 and the like. The encoded image data obtained by the demultiplexing circuit 503 is input to an image data decoder 507.
Further, based on the reference obtained by the program clock reference filter 514, the PLL circuit 515
Generates a clock 1, and this clock is supplied to the decoder 507.
Becomes a clock signal for operating. On the other hand, with respect to the coded moving image data of the sub-screen, the demultiplexing circuit 512 selects a moving image signal of a channel which becomes a desired sub-screen.

The encoded moving image data of the sub-screen from the demultiplexing circuit 512 is input to the decoder 517 of the image data decoder 507. The predecoder 517 extracts only information related to the I picture from the encoded moving image data of the sub-screen and stores the extracted information in the buffer 516. At this time, buffer 5
16 can be stored in the same memory as the main image data VBV buffer. The image data decoder 507 is 50
9 The variable length decoder circuit and the inverse DCT circuit 510 perform the variable length decoding and the inverse DCT operation. Perform DCT operation. That is, decoding of two channels is realized by one variable length decoder circuit and inverse DCT circuit. Image data of main screen after inverse DCT processing. Motion compensation is performed by the frame memory 5 by the motion compensation circuit 511.
22 and the image is restored.

On the other hand, the image data of the sub-screen is down-sampled by the thinning circuit 518 after the inverse DCT processing, and stored in the frame memory 519. Thereafter, the image synthesizing circuit 523 displays the completed I-picture of the sub-screen together with the image data display of the main screen, so that an image of a main channel on the same screen and a part of a different channel as a sub-screen are displayed at the same time. Can be displayed without specially having a variable length decoder circuit for decoding the sub-screen and an inverse DCT circuit.

FIG. 6 is a diagram showing a processing flow of a main part in the decoder according to the second embodiment. The variable length decoding circuit 509 and the inverse DCT circuit 510 of the decoder 507 perform the variable length decoding process and the inverse DCT process of the sub image during the period in which the main image is not processed, so that the same variable length decoding circuit 509 and the inverse DCT process are performed. The inverse DCT circuit 510 can decode both the main screen and the sub-screen image data. This makes it possible to reduce the circuit size as compared with the circuit configuration of the decoder for two channels shown in FIG. 3, and to configure a low-cost moving image reproducing apparatus.

<Third Embodiment> FIG. 8 is a diagram showing a configuration of a sub-picture decoder in a third embodiment of the moving picture reproducing apparatus according to the present invention. The configuration other than the decoder is substantially the same as that shown in FIG. 1 and will not be described. In the present embodiment, the downsampling is performed by the inverse DCT operation with respect to the compression of the image area of the image data of the sub-screen.

As shown in FIG. 7, the DCT transform data is
When the horizontal axis indicates the horizontal spatial frequency and the vertical axis indicates the vertical horizontal spatial frequency, D is the numerical order indicated by the number divided by the dotted line in the drawing.
CT coefficients are arranged, and the smaller the number, the lower the spatial frequency. In the present embodiment, 2 × 2 pixel data is calculated by performing an operation using only the 2 × 2 matrix component of the low frequency component of the DCT coefficient, and the number of pixels is normally set to 8 × 2.
8 is down-sampled from 64 pixels to 16 pixels.

In the decoder 401 shown in FIG. 8, only information relating to the I picture is extracted from the image data input by the predecoder 402, and is subjected to variable length decoding by the variable length decoder 404 via the buffer 403. As shown in FIG.
Down-sampling is performed so that only the four low-frequency components of the DCT coefficient are transmitted to the inverse DCT circuit 406. Inverse DC
The T circuit 406 performs an inverse DCT operation of 2 × 2 to restore the image of the sub-screen and stores it in the memory 407. Thus, the inverse D
By down-sampling with the CT circuit 406,
The size of the inverse DCT circuit used for decoding the sub-screen is reduced.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments.
For example, although one sub-screen has been described, a plurality of sub-screens may be provided. Also, the case where the coded image data is based on the MPEG system has been described.
Non-systems, for example, if intraframe coding is DCT
No conversion may be performed.

In the above-described embodiment, the decoding unit has been described with the circuit configuration having the function described above. However, it is obvious that the CPU, the memory, and the bus can be realized by a combination program processing. , Hardware configuration and program processing configuration.

[0031]

The moving picture reproducing apparatus according to the present invention provides a moving picture reproducing apparatus capable of displaying an image of another channel as a sub-screen on a part of the main channel screen. Is limited to I-pictures and restored, it is possible to provide an economical, that is, a low-cost, moving image reproducing apparatus without the need for a complete decoder for two channels.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a moving image reproducing apparatus according to the present invention.

FIG. 2 is an example of a display screen as an object of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional moving picture signal reproducing apparatus for displaying moving pictures of a plurality of channels.

FIG. 4 is a diagram showing processing timing of a main part in the embodiment of FIG. 1;

FIG. 5 is a block diagram showing a configuration of a second embodiment of the moving image reproducing apparatus according to the present invention.

FIG. 6 is a diagram showing processing timing of a main part in the embodiment of FIG. 5;

FIG. 7 is a diagram showing DCT transform data for explaining the operation principle of the third embodiment of the moving picture reproducing apparatus according to the present invention.

FIG. 8 is a block diagram showing a configuration of a decoder according to a third embodiment of the moving picture reproducing apparatus according to the present invention.

[Explanation of symbols]

101, 301, 501 ... tuner, 102, 302, 502 ... demodulator, 103, 113, 303, 316, 503, 512 ... demultiplexing circuit, 104, 304, 504, 513 ... PID filter, 105, 305, 505 514: depacketizer, 106, 306, 506, 515: descrambler, 107, 117, 307, 317, 507: MPEG decoder, 108, 308, 508, 404: VBV buffer, 109, 309, 509: variable length decoder 110, 310, 510, 406: inverse DCT converter, 111, 311, 522: frame memory, 112, 312, 511: motion assurance circuit, 113, 313, 523: image output circuit, 114, 322: image synthesis circuit 115,314,318,520 ... PCR filter, 16, 315, 319, 521 PLL circuit, 118, 517, 402 ... predecoder, 119, 516, 403 ... buffer, 120 ... variable length decoder, 121 ... inverse DCT converter, 122, 320, 518, 405 ... 123, 519, 407 memory, 321 synchronization memory, 401 sub-image decoder.

Claims (7)

[Claims] 1. A moving image reproducing apparatus for receiving an encoded image data sequence of a plurality of channels composed of intra-frame encoded and motion compensated inter-frame encoded image data and reproducing an image, comprising: A demultiplexing unit that separates the encoded image data sequence, a plurality of decoding units that decode each of the separated encoded image data sequences, and a sub-screen that compresses at least one decoded signal of the plurality of decoding units. In a moving picture reproducing apparatus having an image synthesizing unit for synthesizing with information of a main screen output from another decoding unit as information, the decoding unit for performing the screen compression includes an intra-frame encoding in the received encoded image data. A pre-decoder for extracting only data, a buffer memory for temporarily storing intra-frame encoded data extracted from the pre-decoder, and a buffer in the buffer memory. A moving image reproducing apparatus characterized by comprising a decoding unit for decoding intra-frame encoded data and a thinning unit for thinning out the decoded data. 2. The moving picture reproducing apparatus according to claim 1, wherein
A moving image reproducing apparatus, wherein the encoded image data is encoded data of the MPEG encoding system, and the intra-frame encoded data is encoded data of an I picture. 3. The moving picture reproducing apparatus according to claim 2, wherein
A variable length decoding unit for decoding a variable length code of the encoded data of the I picture and an inverse DCT transform unit for performing an inverse DCT transform of an output of the variable length decoding unit are provided between the buffer memory and the thinning unit. A moving image reproducing apparatus. 4. The moving picture reproducing apparatus according to claim 3, wherein
A moving picture reproducing apparatus, wherein the inverse DCT transform unit is configured to perform an inverse DCT transform only on the low frequency component coefficients decoded by the variable length decoding unit. 5. The moving picture reproducing apparatus according to claim 2, wherein
A moving image storing means for storing the decoded sub-screen image data in a memory and displaying, as a part of the main screen image data, the sub-screen image after one image data is completely decoded; Image reproduction device. 6. The moving picture reproducing apparatus according to claim 3, wherein a variable length decoding unit used for decoding image data of the sub-screen is provided in a variable length decoding unit in the image data decoder of the main screen. Moving image reproducing apparatus. 7. The moving picture reproducing apparatus according to claim 3, wherein
A moving picture reproducing apparatus characterized in that an inverse DCT transform section used for decoding image data of a sub-screen is performed by an inverse DCT transform section in an image data decoding section of a main screen.