JPH1187552A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is hardly affected by α-rays emitted from a solder by a method wherein an electrical connection part where a wiring pattern is exposed from the backside of a board is formed through a through-hole on a board at a position outside a region where a semiconductor chip is mounted. SOLUTION: A semiconductor device mounted with a semiconductor chip 3 and a mother board 10 are connected together by connecting a copper foil 6 exposed through a via V to a semiconductor device connecting pad 11, which is installed to the surface of the board 10, with a cream solder 20. The cream solder 20 is previously applied to the semiconductor device connecting pad 11, and a soldering operation is carried out through a method where the semiconductor device is mounted on the board 10 aligning the semiconductor device connecting pad 11 with the via V, and a prescribed reflow process is carried out. As mentioned above, a soldering operation is carried out outside a region where the semiconductor chip 3 is mounted, so that semiconductor chip 3 is less affected by α-rays emitted from a solder.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for suppressing the influence of alpha rays emitted from solder by providing an electrical connection site for soldering outside a semiconductor chip mounting area. The present invention relates to a semiconductor device that can be used.

[0002]

2. Description of the Related Art Higher integration and higher density of semiconductor devices are strongly demanded along with higher performance of electric and electronic parts. Has been changed from a structure having bonding pads on two sides to a structure having bonding pads on all four sides.

Further, as a countermeasure against the increase in the number of pins, for example, in US Pat. BG with multiple solder balls arranged in a grid on the surface of a conductive film
A semiconductor device called A (ball grid array) has been proposed.

In the above-mentioned BGA type semiconductor device, since a semiconductor chip occupies a large portion in the semiconductor device, it is called a chip size package, and the size and weight of the package can be reduced.

[0005]

However, when a memory device is configured with the BGA as described above, the α-rays emitted from the solder balls arranged in a grid form affect the semiconductor chip, and the memory contents are lost. There is.

In particular, since it is susceptible to the influence of the solder balls disposed below the semiconductor chip, it has been conventionally desired to minimize the amount of solder in that portion.

[0007] Accordingly, the present invention provides a method for producing α
It is an object of the present invention to provide a semiconductor device of a chip size package that is hardly affected by lines.

[0008]

According to one aspect of the present invention, there is provided a substrate having a wiring pattern formed thereon, and a semiconductor chip mounted on a surface of the substrate and connected to the wiring pattern. And an electrical connection portion where the wiring pattern is exposed from the back surface of the substrate via a through hole formed outside a region of the substrate on which the semiconductor chip is mounted.

According to a second aspect of the present invention, in the first aspect of the present invention, the semiconductor device further comprises a second electrical connection portion in which the wiring pattern is exposed from a side surface of the substrate.

According to a third aspect of the present invention, in the first or second aspect, the substrate is not provided with a solder ball.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings.

First, an outline of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view showing the structure of the semiconductor device according to the present invention and a state where it is soldered to a motherboard.

According to the present invention, as shown in FIG. 1, a via V is formed outside a region where the semiconductor chip 3 is mounted so that the copper foil 6 connected to the semiconductor chip 3 by the wire 2 is exposed. By connecting the exposed copper foil 6 and the semiconductor device connection pads 11 provided on the motherboard 10 with cream solder 20, the influence of α rays emitted from the solder is reduced.

Hereinafter, the structure of the semiconductor device according to the present invention will be described in more detail.

FIG. 1 is a top view showing the structure of a semiconductor device according to the present invention. As shown in FIG. 1, a semiconductor device according to the present invention includes a semiconductor chip 3 serving as a functional unit of the device.
A window W for exposing the copper foil 6 from the solder resist 5, a wire 2 connecting the semiconductor chip 3 and the copper foil 6 exposed from the window W, and a mold resin for sealing the semiconductor chip 3, the window W and the wire 2 1
And a solder resist 5 covering the copper foil 6, and are arranged as follows.

The semiconductor chip 3 is mounted at the center of the device, and the number of windows W corresponding to the number of output terminals of the semiconductor chip is formed around the semiconductor chip 3. Each window W
Form a predetermined wiring pattern, and the tip of the wiring pattern is formed as a soldering terminal 50 outside the mold resin 1.

As shown in FIG. 1, the soldering terminals 50 are arranged in a staggered manner so that the pitch between the terminals is small, and form a large number of output terminals. The pitch between the terminals arranged in a zigzag pattern is preferably 0.5 mm in consideration of the printing limit of cream solder of 0.4 mm.

Each soldering terminal 50 must be exposed on the upper surface so as to increase the contact surface with the solder at the time of soldering, and must be exposed to the outside such as the soldering terminal 50 and the window W. The copper foil 6 other than the portion is covered with the solder resist 5.

FIG. 2 is a sectional view of the semiconductor device shown in FIG.
It is sectional drawing which shows the structure of a cross section. As shown in FIG. 1, in the semiconductor device shown in FIG.
Are formed in a predetermined pattern, the upper surface thereof is covered with a solder resist 5, and the semiconductor chip 3 is mounted by applying an Ag paste 4 on the surface of the solder resist.

In the insulating film 7, a via V for exposing the copper foil 6 to the bottom surface side is formed.

FIG. 3 shows a semiconductor device having the above structure mounted on a motherboard. As described above, the connection between the semiconductor device according to the present invention and the motherboard 10 is performed by using the copper foil 6 exposed from the via V and the motherboard 1.
This is performed by connecting the semiconductor device connection pads 11 provided on the surface of the “0” with the cream solder 20.

The cream solder 20 is applied to the semiconductor device connection pads 11 in advance, and the soldering is performed by placing the semiconductor device on the motherboard by matching the positions of the semiconductor device connection pads and the positions of the vias V. Then, it is performed through a predetermined reflow process.

As described above, according to the present invention, since the soldering is performed outside the region where the semiconductor chip is mounted, the influence of α rays emitted from the solder can be reduced.

Further, since solder balls are not used unlike the BGA type semiconductor device, the cost for forming the solder balls can be reduced, and the mounting height of the package can be reduced.

Next, a method for manufacturing the semiconductor device according to the present invention as described above will be described.

First, FIG. 4 is a sectional view showing a step of forming a copper foil of a semiconductor device according to the present invention. As shown in the figure,
A copper foil 6 is attached to the surface of an insulating film 7 made of a polyimide tape.

Then, a photoresist is applied to the surface and patterned by photolithography.
A resist pattern R as shown in FIG. FIG.
FIG. 5 is a cross-sectional view showing a state where a resist pattern is formed on the copper foil part shown in FIG. 4.

Then, the copper foil 6 exposed from the resist pattern R is etched to form a predetermined wiring pattern. FIG. 6 is a sectional view showing a state in which a wiring pattern is formed on the copper foil shown in FIG.

Thereafter, a photoresist is applied to the back surface of the insulating film 7 and photolithography is performed to form a resist pattern. Using the resist pattern as a mask, the insulating film 7 is etched and soldered as shown in FIG. A via V is formed in a region where the etching is performed. FIG. 7 is a cross-sectional view showing a state where vias are formed in the insulating film shown in FIG.

Then, as shown in FIG. 8, the entire surface of the copper foil 6 is covered with the solder resist 5. FIG. 8 is a cross-sectional view showing a state where the surface of the copper foil shown in FIG. 7 is covered with a solder resist.

Then, a photoresist is applied to the surface of the solder resist 5 and photolithography is performed to form a resist pattern R. FIG. 9 is a sectional view showing a state where a resist pattern is formed on the surface of the solder resist shown in FIG.

Thereafter, using the resist pattern R as a mask, the solder resist 5 is etched to form a window W in a region where a wire is connected as shown in FIG. Expose 6. FIG. 10 is a cross-sectional view showing a state in which a window and a copper foil exposed portion are formed in the solder resist shown in FIG.

Then, after Ni / Au plating is applied to the copper foil exposed from the solder resist, as shown in FIG. 11, an Ag paste 4 is applied on the upper surface of the solder resist, and the semiconductor chip 3 is mounted. And window W
Are connected by a wire. FIG.
FIG. 11 is a cross-sectional view illustrating a state where a semiconductor chip is mounted on the solder resist illustrated in FIG. 10.

Thereafter, the semiconductor chip 3, the wires 2 and the window W are sealed with a resin to obtain the semiconductor device shown in FIG.

Next, a second embodiment of the semiconductor device according to the present invention will be described.

FIG. 12 shows a second example of the semiconductor device according to the present invention.
FIG. 3 is a top view showing the embodiment. In the semiconductor device shown in the figure, half through holes are formed in terminals outside the staggered soldering terminals. The terminal having such a half through hole can be soldered from the side.

The half through hole as described above is formed by cutting an insulating film and a copper foil by punching.

In each of the above embodiments, as shown in FIG. 2, a case where the semiconductor device according to the present invention has a structure in which a copper foil 6 is formed on an insulating film 7 will be described as an example. However, the present invention is not limited to the above-described structure, and can be applied to, for example, a device in which an adhesive layer is provided between the copper foil 6 and the insulating film 7.

Further, the semiconductor chip 3 may be mounted on the insulating film 7 shown in FIG. 2, and the solder resist 5 may be mounted on the motherboard. In this case, a window W for bonding is formed on the insulating film 7, and the copper foil 6 exposed from the window and the semiconductor chip 3 are connected by wires. In a portion to be soldered to the motherboard, a via V is formed in the insulating film 7, the solder resist 5 is peeled off, and the copper foil 6 is exposed.

[0040]

As described above, according to the present invention,
Since the configuration is such that soldering is performed outside the region where the semiconductor chip is mounted, the influence of α-rays emitted from the solder can be reduced.

Further, since solder balls are not used unlike the BGA type semiconductor device, the cost for forming the solder balls can be reduced, and the mounting height of the package can be reduced.

[Brief description of the drawings]

FIG. 1 is a top view illustrating a structure of a semiconductor device according to the present invention.

FIG. 2 is a sectional view showing the structure of the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view showing a structure of the semiconductor device according to the present invention and a state of being soldered to a motherboard.

FIG. 4 is a sectional view showing a copper foil forming step of the semiconductor device according to the present invention.

FIG. 5 is a sectional view showing a state where a resist pattern is formed on the copper foil part shown in FIG. 4;

FIG. 6 is a sectional view showing a state where a wiring pattern is formed on the copper foil shown in FIG. 5;

FIG. 7 is a sectional view showing a state in which a via is formed in the insulating film shown in FIG. 6;

FIG. 8 is a sectional view showing a state where the surface of the copper foil shown in FIG. 7 is covered with a solder resist.

FIG. 9 is a sectional view showing a state where a resist pattern is formed on the surface of the solder resist shown in FIG. 8;

FIG. 10 is a sectional view showing a state in which a window and a copper foil exposed portion are formed in the solder resist shown in FIG. 9;

FIG. 11 is a sectional view showing a state where a semiconductor chip is mounted on the solder resist shown in FIG. 10;

FIG. 12 is a top view showing a second embodiment of the semiconductor device according to the present invention.

[Explanation of symbols]

1 ... mold resin, 2 ... wire, 3 ... semiconductor chip,
4 ... Ag paste, 5 ... Solder resist, 6 ... Copper foil,
7: Insulating film, 10: Mother board, 11: Pad for connecting semiconductor device, 20: Cream solder, 50: Terminal for soldering, R: Resist pattern, V: Via, W ...
window.

Claims (3)

[Claims] A substrate on which a wiring pattern is formed; a semiconductor chip mounted on a surface of the substrate and connected to the wiring pattern; and a semiconductor chip formed outside a region of the substrate on which the semiconductor chip is mounted. A semiconductor device comprising: an electrical connection portion where the wiring pattern is exposed from a back surface of the substrate via a through hole. 2. The semiconductor device according to claim 1, further comprising a second electrical connection portion where said wiring pattern is exposed from a side surface of said substrate. 3. The semiconductor device according to claim 1, wherein the substrate does not include a solder ball.