JPH1187513A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit where a multilayer wiring technique is used and which is improved in circuit operation and reliability by a method wherein the uppermost wiring layer is made to serve as a signal wiring layer which restrains a signal delay. SOLUTION: Multilayer wirings 1AL, 2AL, and 3AL on a semiconductor integrated circuit are metal wiring layers which are isolated from each other by an insulator. When the metal wirings 1AL, 2AL, and 3AL or semiconductor substrates are made to confront each other being isolated from each other with an insulating film, a parasitic electric capacitance is generated between them. A capacitance generated between them is directly proportional to the opposed areas but inversely proportional to the thickness of the insulating film. A parasitic capacitance is generated between all the wirings, a wiring as the uppermost wiring layer 3AL is smaller in parasitic capacitance than other wirings as the wiring layers 1AL and 2AL. By this setup, the semiconductor integrated circuit can be improved in circuit performance by suppressing signal delays.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit using a multilayer wiring technique.

[0002]

2. Description of the Related Art At present, a semiconductor integrated circuit has a complicated structure in which transistors formed on a silicon substrate are interconnected by using wirings formed in a plurality of metal wiring layers separated by an insulator. It constitutes a circuit (system). Which wiring layer wiring to use for connecting the elements is determined by
A group of wirings extending in the same general direction is composed of one wiring layer, and a group of wirings in a direction perpendicular to the wiring layer is composed of wirings of another wiring layer, and the wiring in a direction perpendicular to the adjacent wiring layer is allocated to each layer. . Such a wiring method is suitable for handling by an automatic placement and routing tool which is indispensable for the design of a semiconductor integrated circuit, and contributes to shortening the design period of the semiconductor integrated circuit by using the automatic placement and routing tool. .

On the other hand, in the semiconductor integrated circuit, the wiring connecting each element and each circuit does not all have the same weight. In other words, the characteristics required for each wiring are different. Further, the wiring has an electrical resistance and an additional capacitance of the metal wiring body, thereby causing a propagation delay of a signal transmitted through the wiring. The additional capacitance of the wiring is an electric capacitance determined by the distance between the wiring and the substrate, the area facing the substrate, or the distance between the adjacent wiring and the facing area. Therefore, some types of wiring require placement and wiring to minimize propagation delay. In some wirings, the high level and the low level of a signal transmitted through the wiring change at high speed, so that there is a possibility that a signal transmitted through an adjacent wiring may generate noise due to the effect. Therefore, in the uniform placement and routing using the automatic placement and routing tool, there is little consideration for the arrangement of the signal lines as described above, and the reliability of the operation of the semiconductor integrated circuit may be impaired.

[0004]

As described above,
In the conventional semiconductor device having a multilayer wiring structure, a placement and routing method that is easy to handle with an automatic placement and routing tool such as CAD has been adopted. We did not make the best choice. For this reason, the operation speed is delayed and the reliability of the circuit operation is reduced.

The present invention has been made in view of the above, and an object of the present invention is to select an optimum wiring layer in accordance with the characteristics of wiring and a signal propagated through the wiring to improve the circuit operation. Another object is to provide a semiconductor integrated circuit with improved reliability.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit using a multi-layer wiring technique, wherein a signal wiring for suppressing a signal delay is provided in an uppermost wiring layer. It is characterized by having.

According to a second aspect of the present invention, in a semiconductor integrated circuit using a multi-layer wiring technique, a signal wiring which needs to be connected to the outside at the time of failure analysis is a top wiring layer. .

According to a third aspect of the present invention, in a semiconductor integrated circuit using a multilayer wiring technique, the first power supply wiring and the first signal wiring group are the uppermost wiring layer, and the second power supply wiring is the next layer. The wiring layer is characterized in that:

According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the first or third aspect, the signal wiring for suppressing the signal delay or the first signal wiring group is a clock signal wiring or an address signal wiring. Alternatively, it is a data signal wiring.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, the first signal wiring group is a signal wiring that needs to be connected to the outside during failure analysis. And

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, the first signal line group is a signal line for suppressing noise from a region lower than the first signal line group. It is characterized by being.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the sixth aspect, the signal wiring for suppressing noise from a region below the first signal wiring group is an analog signal wiring. It is characterized by.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit using the multi-layer wiring technique, all of the uppermost wiring layers are first power supply wirings, and all of the next wiring layers are second power supply wirings. It is characterized by having.

According to a ninth aspect of the present invention, in a semiconductor integrated circuit using a multi-layer wiring technique, the same kind of signal wiring arranged in parallel over a long distance is divided into a plurality of wiring layers and arranged.
In addition, the same kind of signal wiring of each wiring layer is wired at a wiring interval wider than the minimum wiring interval.

According to a tenth aspect of the present invention, in the semiconductor integrated circuit of the ninth aspect, the same kind of signal wiring is an address bus or a data bus.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

Before describing the embodiment shown in FIG. 1, the structure of the multilayer wiring and the additional capacitance of each wiring layer will be described with reference to FIGS.

FIG. 2 shows the state of, for example, three-layer wiring on a semiconductor integrated circuit.
3AL schematically shows metal wiring layers separated by an insulator (not shown in the figure) such as an oxide film. For convenience, reference numerals corresponding to numbers from the lower layer are given. ing. The lines shown on each of the wiring layers 1AL, 2AL, and 3AL schematically show actual metal wirings interconnecting transistor elements, circuits, and the like. Although FIG. 2 shows a three-layer wiring structure, the present embodiment and the embodiments described below are not limited to three layers, and it is needless to say that the present invention can be applied to a multilayer wiring structure having more layers. .

FIG. 3 schematically shows the parasitic capacitance between the metal wirings of each layer and between the metal wiring and the semiconductor substrate 1 in the three-layered multilayer wiring structure. In FIG. 3, when the metal wirings 1AL, 2AL, 3AL or the semiconductor substrate 1 is opposed by being separated by the insulating film 2, a parasitic capacitance occurs between them. This capacitance value is proportional to the facing area and inversely proportional to the insulating film thickness. For this reason, the capacitance value between the wirings located far from each other or between the semiconductor substrates 1 becomes small. Therefore, it is only necessary to pay attention to the capacitance value between the adjacent wiring layers approximately.

In all the wirings, a parasitic capacitance is generated between other wirings surrounding the wirings. The wiring using the uppermost wiring layer 3AL is compared with the wirings formed in the other layers 1AL and 2AL. As a result, the parasitic capacitance value decreases, and the relationship between the capacitances of the wiring layers 1AL, 2AL, and 3AL is as follows: the capacitance value of the wiring layer 1AL> the capacitance value of the wiring layer 2AL> the wiring layer 3A.
L is the capacitance value. This is because there is no “wiring layer above” the wiring layer 3AL adjacent to the uppermost wiring layer 3AL, and accordingly the capacitance generated in the wiring of the uppermost wiring layer 3AL becomes smaller. The capacitance value on a wiring greatly affects the delay of a signal propagated on the wiring.

Therefore, in this embodiment, as shown in FIG. 1, a signal wiring to be simultaneously transmitted to the entire chip, such as a signal wiring 3 of a system clock for controlling the operation of the whole semiconductor integrated circuit, is formed in the uppermost wiring layer. It is characterized in that it is arranged and wired using 3AL. In addition to the system clock, it is effective to place and route important signals whose propagation delay is to be minimized using the uppermost wiring layer 3AL.

FIG. 4 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

A feature of the embodiment shown in FIG. 4 is that the signal transmitted through the signal wiring 4 is observed for analysis of a circuit failure or the like on the semiconductor integrated circuit, or the signal wiring 4 is forcibly externally applied to the signal wiring 4. When a signal is applied to analyze a defective portion or the like, the signal line is previously placed in the uppermost wiring layer 3A.
L is used.

FIG. 5 is a diagram showing an embodiment of a system including the signal lines used for failure analysis.

In FIG. 5, a system 5 composed of a semiconductor integrated circuit has a POR composed on the same chip.
(Power ON Reset) circuit 6 may be used together. Generally, a data holding circuit such as a register and a latch in the system 5 which is configured by a semiconductor integrated circuit may hold unexpected data when the system 5 is powered on. When the operation of the system 5 is started in such a state, a malfunction of the entire system 5 may be caused. In order to avoid this, immediately after the system 5 is powered on using the POR circuit 6, the register,
It is necessary to completely clear latches and the like.

Therefore, as a specification required for the POR circuit 6, a reset signal is inputted to the system 5 upon detecting that the power is supplied to the system 5, and as shown in FIG. It is necessary to detect that the voltage has become equal to or higher than the minimum voltage at which the system operates (VccMIN in the figure) and release the reset signal. In FIG. 6, it is assumed that the register, the latch, and the like are cleared when the reset signal is at the low level. However, since the POR circuit 6 is an analog circuit, it is difficult to design the POR circuit 6 as compared with a digital circuit, and a malfunction often occurs in an early stage of system development. For example, as shown in FIG. 6B, the reset signal is released when the power supply voltage is equal to or lower than the minimum voltage at which the system 5 operates,
Registers and latches in the system 5 cannot be completely cleared, causing a malfunction of the entire system 5.

In such a POR circuit 6, POR
The signal line from the circuit 6 to the system 5 is connected to the uppermost wiring layer 3
If the AL is used, the ion beam processing is performed when a failure occurs in the POR circuit 6 and these signal wirings are externally observed or signals are forcibly applied to these signal wirings from the outside. By using an apparatus or the like, the insulating film is removed to expose the uppermost wiring, so that processing for controlling signals on the signal lines from the outside can be easily performed. As a result, it is possible to easily verify the operation of the POR circuit 6 immediately after the power is turned on or to confirm the operation of the other system, and it is possible to sufficiently and easily perform the failure analysis.

FIG. 7 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

The feature of the embodiment shown in FIG. 7 is that the uppermost wiring layer 5AL in the five-layer multilayer wiring structure is used.
And a power supply wiring 7 such as a high-level power supply wiring (VDD) and a signal wiring group 8, and another power supply wiring 9 such as a low-level power supply wiring (VSS) is disposed and wired below the next layer 4AL. In FIG. 7, five wiring layers 1AL, 2AL, 3A
Although an example using L, 4AL, and 5AL is shown, the number of layers is not limited to five, and another number of layers may be used.

In a system composed of semiconductor integrated circuits, a signal line such as a system clock whose signal constantly changes at high speed emits noise to the surroundings. On the other hand, on the other hand, there are signal lines that minimize the influence of external noise. In a system or the like in which analog signals and digital signals are mixed, it is desirable to minimize noise of digital signals on analog signal lines.
The source of such a noise or, on the contrary, a signal line to avoid the influence of the noise is constituted by the uppermost wiring layer 5AL, and the power wiring is uniformly spread over the next layer 4AL thereunder to thereby provide the power wiring. However, since it has a shielding effect against noise, the influence of noise can be suppressed. Note that the signal wiring wired in the uppermost layer of the embodiment shown in FIG. 7 may be an address signal wiring, a data signal wiring, or a signal wiring that needs to be connected to the outside during failure analysis.

FIG. 8 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

The feature of the embodiment shown in FIG. 8 is that five layers (1AL, 2AL, 3AL, 4AL, 5AL) are provided.
In the multi-layer wiring structure of (1), all of the uppermost wiring layer 5AL is a first power supply wiring 10 such as a high power supply wiring (VDD), and all of the next wiring layer 4AL is a second power supply wiring 11 such as a low power supply wiring ( VSS). In such an embodiment, a large opposing area can be secured by the power supply wiring of the uppermost layer 5AL and the lower layer 4AL, so that a large parasitic capacitance value can be secured. As a result, the effect of noise on the power supply of the system can be reduced. Such an effect can also be obtained in the embodiment shown in FIG.

FIG. 9 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

A feature of the embodiment shown in FIG. 9 is that the same kind of signal wiring arranged in parallel for a long distance is divided into a plurality of wiring layers and arranged, and the same kind of signal wiring of each wiring layer is arranged. That is, the signal wiring is arranged and wired at a wiring interval wider than the minimum wiring interval.

In a system constituted by a semiconductor integrated circuit, a bus line group 12 of an address bus or a data bus having a bit width of 8 to 64 lines and processed by a CPU is frequently used. These wirings are often arranged in parallel over a long distance. In this case, adjacent wirings are connected by a parasitic capacitance, and a phenomenon called crosstalk occurs in which a change in a signal transmitted on one signal line affects adjacent wirings as noise. In order to avoid this effect, it is preferable that wiring is performed at intervals wider than the minimum possible wiring interval in the manufacturing process of the semiconductor integrated circuit. However,
If the wiring interval is widened in this way, the entire wiring area increases. For this reason, the bus wiring group 12 is divided into a plurality of wiring layers,
For example, as shown in FIG. 9, by dividing and arranging the wiring into the second wiring layer 2AL and the fourth wiring layer 4AL and making the wiring interval wider than the minimum wiring interval, the bus wiring 1 is formed.
In addition to suppressing crosstalk between the two, it is possible to suppress an increase in the wiring area.

[0037]

As described above, according to the first aspect of the present invention, since the signal wiring for suppressing the signal delay is the uppermost wiring layer having the least wiring capacitance, the signal delay is suppressed and the circuit is suppressed. Performance can be improved.

According to the second aspect of the present invention, since the signal wiring which needs to be connected to the outside at the time of failure analysis is the uppermost wiring layer, the operation of connecting the signal wiring to the outside becomes easy. In addition, failure analysis can be easily performed.

According to the third to seventh aspects of the present invention, the first power supply wiring and the first signal wiring group are the uppermost wiring layer, and the second power supply wiring is the next wiring layer. The first signal wiring group is shielded by the power supply wiring, so that noise emitted from the first signal wiring group or given to the first power supply wiring group can be suppressed.

According to the eighth aspect of the present invention, all of the uppermost wiring layer is used as the first power supply wiring, and all of the next wiring layer is used as the second power supply wiring. Can be reduced.

According to the ninth aspect of the present invention, the signal wirings arranged in parallel for a long distance are divided into a plurality of wiring layers and arranged, and the signal wirings of each wiring layer are wider than the minimum wiring interval. Since wiring is performed at the wiring interval, crosstalk between the divided wirings can be suppressed, and an increase in the wiring area can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a state of three-layer wiring on a semiconductor integrated circuit;

FIG. 3 is a diagram schematically showing the capacitance of each layer in a three-layer multilayer wiring structure.

FIG. 4 is a diagram showing a configuration of a semiconductor device according to one embodiment of the invention described in claim 2;

FIG. 5 is a diagram illustrating an embodiment of a system including a signal line used for failure analysis.

FIG. 6 is a diagram illustrating a change over time of a power supply voltage of a POR circuit.

FIG. 7 is a diagram showing a configuration of a semiconductor device according to an embodiment of the invention as set forth in claim 3, 4, 5, 6, or 7;

FIG. 8 is a diagram showing a configuration of a semiconductor device according to one embodiment of the invention described in claim 8;

FIG. 9 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulator 3,4 Signal wiring 5 System 6 POR circuit 7,10 High power supply wiring 8 Signal wiring group 9,11 Low power supply wiring 12 Bus wiring group 1AL, 2AL, 3AL, 4AL, 5AL Wiring layer

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hirofumi Yashiro 580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside Toshiba Semiconductor System Technology Center Co., Ltd.

Claims (10)

[Claims] 1. A semiconductor integrated circuit using a multi-layer wiring technique, wherein a signal wiring for suppressing signal delay is an uppermost wiring layer. 2. A semiconductor integrated circuit using a multilayer wiring technique, wherein a signal wiring which needs to be connected to the outside at the time of failure analysis is a top wiring layer. 3. A semiconductor integrated circuit using a multi-layer wiring technique, wherein the first power supply wiring and the first signal wiring group are the uppermost wiring layer, and the second power supply wiring is the next wiring layer. A semiconductor integrated circuit characterized by the above-mentioned. 4. The signal line according to claim 1, wherein the signal line for suppressing the signal delay or the first signal line group is a clock signal line, an address signal line, or a data signal line. Semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 3, wherein the first signal wiring group is a signal wiring that needs to be connected to the outside during failure analysis. 6. The semiconductor integrated circuit according to claim 3, wherein the first signal line group is a signal line for suppressing noise from a region below the first signal line group. 7. The semiconductor integrated circuit according to claim 6, wherein the signal wiring for suppressing noise from a region lower than the first signal wiring group is an analog signal wiring. 8. A semiconductor integrated circuit using a multilayer wiring technique, wherein all of the uppermost wiring layers are used as first power supply wirings, and all of the next wiring layers are used as second power supply wirings. Semiconductor integrated circuit. 9. A semiconductor integrated circuit using a multi-layer wiring technique, wherein the same kind of signal wiring arranged in parallel over long distances is divided into a plurality of wiring layers, and the same kind of signal wiring of each wiring layer is arranged. A semiconductor integrated circuit, wherein signal wirings are arranged at wiring intervals wider than the minimum wiring interval. 10. The semiconductor integrated circuit according to claim 9, wherein said same kind of signal wiring is an address bus or a data bus.