JPH1187418A - Semiconductor chip with bump - Google Patents
Semiconductor chip with bumpInfo
- Publication number
- JPH1187418A JPH1187418A JP9239666A JP23966697A JPH1187418A JP H1187418 A JPH1187418 A JP H1187418A JP 9239666 A JP9239666 A JP 9239666A JP 23966697 A JP23966697 A JP 23966697A JP H1187418 A JPH1187418 A JP H1187418A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- bump
- electrodes
- chip
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は回路基板上にフリ
ップチップ方式で実装されるバンプ付半導体チップに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip with bumps mounted on a circuit board by a flip chip method.
【０００２】[0002]
【従来の技術】従来のこの種のバンプ付半導体チップの
外観構造の一例を図７に示す。このバンプ付半導体チッ
プ（以下、チップと言う。）１１は端子が周辺配置構造
とされたもので、チップ本体１２の方形をなす一面の各
辺に沿って電極１３が配列形成され、それら電極１３上
にバンプ１４がそれぞれ形成されている。2. Description of the Related Art FIG. 7 shows an example of an appearance structure of a conventional semiconductor chip with bumps of this kind. The semiconductor chip with bumps (hereinafter, referred to as chip) 11 has terminals arranged in a peripheral structure, and electrodes 13 are arranged and formed along each side of a square surface of the chip body 12. The bumps 14 are formed on each of them.
【０００３】バンプ１４の形成は図８に示したように、
超音波ホーン１５に取付けられたキャピラリ１６を用い
て行われ、即ちキャピラリ１６より供給されるワイヤ１
７がスパーク電極（図示せず）により溶融されてワイヤ
１７の先端にボール１８が形成され、ワイヤ１７の冗長
部分をキャピラリ１６内に収容した後、キャピラリ１６
によりボール１８を電極１３に押し付け、超音波を加え
てボール１８を電極１３に接合させることにより、バン
プ１４が形成される。この際、チップ本体１２は所要の
温度に加熱されている。ワイヤ１７の材料としては、Ａ
ｕ，Ｃｕ，あるいはこれらを主成分とする合金、半田等
が用いられる。[0003] As shown in FIG.
This is performed using a capillary 16 attached to the ultrasonic horn 15, that is, the wire 1 supplied from the capillary 16
7 is melted by a spark electrode (not shown) to form a ball 18 at the tip of the wire 17, and a redundant portion of the wire 17 is accommodated in the capillary 16.
The bumps 14 are formed by pressing the ball 18 against the electrode 13 and applying ultrasonic waves to join the ball 18 to the electrode 13. At this time, the chip body 12 is heated to a required temperature. The material of the wire 17 is A
u, Cu, an alloy containing these as a main component, solder, or the like is used.
【０００４】ボール１８が電極１３に接する時のボール
１８への荷重は、超音波を加えている時の荷重の例えば
1.５倍程度に設定され、これによりボール１８が電極１
３に接した時の荷重でバンプ１４の径が決定され、超音
波を加えている時の荷重はバンプ形状に影響せず、ボー
ル１８と電極１３との接合に供せられる。図９はこのよ
うにして形状されたバンプ１４の形状を拡大して示した
ものであり、ボール１８が電極１３に接した時の荷重は
ボール１８を上方より均等に押しつぶすように作用する
ため、形成されたバンプ１４の電極１３との接合面の形
状はほぼ円形となっている。なお、この円形をなす接合
部１４ａ上に続く先細部分は、ワイヤ１７の破断により
生じる破断部１４ｂである。The load on the ball 18 when the ball 18 contacts the electrode 13 is, for example, the load when applying ultrasonic waves.
It is set to about 1.5 times, so that the ball 18
The diameter of the bump 14 is determined by the load when it comes into contact with 3, and the load when ultrasonic waves are applied does not affect the bump shape, and is used for bonding the ball 18 and the electrode 13. FIG. 9 is an enlarged view of the shape of the bump 14 thus formed. Since the load when the ball 18 comes into contact with the electrode 13 acts to crush the ball 18 evenly from above, The shape of the bonding surface of the formed bump 14 with the electrode 13 is substantially circular. The tapered portion following the circular joining portion 14a is a broken portion 14b caused by the breaking of the wire 17.
【０００５】上記のようなバンプ１４を有するチップ１
１は、図１０ＡあるいはＢに示すようにして基板２１に
実装される。図１０Ａは各バンプ１４が対応する基板電
極２２上に位置するように、チップ１１を基板２１に搭
載し、チップ本体１２を押圧して各バンプ１４を基板電
極２２に圧接させた状態で、チップ本体１２の周辺より
例えばエポキシ樹脂等の樹脂２３を毛細管現象によりチ
ップ本体１２の下に流し込むことにより、樹脂封止して
実装する方法を示したものである。[0005] Chip 1 having bumps 14 as described above
1 is mounted on the substrate 21 as shown in FIG. 10A or 10B. FIG. 10A shows a state in which the chip 11 is mounted on the substrate 21 so that each bump 14 is located on the corresponding substrate electrode 22, and the chip body 12 is pressed to press each bump 14 against the substrate electrode 22. This shows a method in which a resin 23 such as an epoxy resin is poured under the chip main body 12 from the periphery of the main body 12 by a capillary phenomenon, and is sealed with a resin and mounted.
【０００６】一方、図１０Ｂは基板２１のチップ搭載位
置中央付近に予め所定量の樹脂２３を供給しておき、チ
ップ１１の搭載によりチップ本体１２の下に樹脂２３を
押し広げて実装する方法を示したものであり、チップ１
１はこれらの方法により樹脂封止されて基板２１にフリ
ップチップ実装される。On the other hand, FIG. 10B shows a method in which a predetermined amount of resin 23 is supplied in advance in the vicinity of the center of the chip mounting position of the substrate 21, and the resin 23 is spread under the chip main body 12 by mounting the chip 11 for mounting. Shown, chip 1
1 is flip-chip mounted on the substrate 21 by resin sealing by these methods.
【０００７】[0007]
【発明が解決しようとする課題】ところで、半導体素子
の集積度の向上及び入出力端子数の増加が進む中、この
種のチップ１１においても、その電極１３の配列ピッチ
の狭ピッチ化が進んでおり、この場合以下に示すような
問題が発生する。即ち、隣接バンプ間の間隔が狭くなる
ため、図１０Ａ及びＢに示したいずれの実装方法におい
ても共通する問題として、樹脂封止工程において樹脂２
３が周辺からチップ本体１２の下へ、あるいはチップ本
体１２の下から周辺へ移動する際に、バンプ間を通過し
難くなり、つまり樹脂２３の流れが非常に悪くなるとい
う問題が発生する。そして、この場合、バンプ１４の位
置精度のばらつきにより、バンプ間の間隔がばらつく
と、樹脂２３の通過速度に差が生じてエアーを巻き込む
ような状況が発生し、樹脂２３が硬化した後にボイドと
して残ってしまうという状況が発生する。図１１は図１
０Ｂの実装方法を例に、この様子を示したものであり、
図中、２４は発生したボイドを示す。By the way, as the degree of integration of semiconductor devices and the number of input / output terminals increase, the pitch of the electrodes 13 of this type of chip 11 also decreases. In this case, the following problem occurs. That is, since the distance between adjacent bumps becomes narrow, a common problem in any of the mounting methods shown in FIGS.
When 3 moves from the periphery to below the chip body 12 or from below the chip body 12 to the periphery, it becomes difficult to pass between the bumps, that is, the flow of the resin 23 becomes extremely poor. In this case, if the distance between the bumps varies due to the variation in the positional accuracy of the bumps 14, a difference occurs in the passing speed of the resin 23, causing a situation in which air is entrapped. A situation occurs in which it remains. FIG. 11 shows FIG.
This is shown by taking the mounting method of 0B as an example.
In the drawing, reference numeral 24 denotes a generated void.
【０００８】封止樹脂２３′内にボイド２４が発生する
と、その内包された気体が温度変化により膨張・収縮す
ることによって樹脂２３′に応力が作用し、例えばバン
プ１４と基板電極２２との圧接状態がその影響を受けて
接触抵抗値が増大するといった不具合が発生する恐れが
あり、また最悪、バンプ１４が基板電極２２から離れる
といった障害が発生し、信頼性上、大きな問題となる。When a void 24 is generated in the sealing resin 23 ', the gas contained therein expands and contracts due to a change in temperature, so that a stress acts on the resin 23', for example, the pressure contact between the bump 14 and the substrate electrode 22. There is a possibility that a problem such as an increase in the contact resistance value occurs due to the influence of the state, and a trouble such as the bump 14 separating from the substrate electrode 22 occurs at worst, which is a serious problem in reliability.
【０００９】この発明の目的は上述した問題点に鑑み、
ボイドの発生を抑制することができ、信頼性に優れた実
装状態を実現できるようにしたバンプ付半導体チップを
提供することにある。In view of the above problems, an object of the present invention is to provide
An object of the present invention is to provide a bumped semiconductor chip capable of suppressing the generation of voids and realizing a highly reliable mounting state.
【００１０】[0010]
【課題を解決するための手段】請求項１の発明によれ
ば、チップ本体の一面の各辺に沿って電極が配列形成さ
れ、それら電極上にバンプがそれぞれ形成されてなるバ
ンプ付半導体チップにおいて、バンプの、電極との接合
面の形状が楕円形とされる。請求項２の発明では、請求
項１の発明において、上記楕円の長軸方向がそのバンプ
が沿う辺と直交する方向とされる。According to the first aspect of the present invention, there is provided a semiconductor chip with bumps in which electrodes are formed along each side of one surface of a chip body and bumps are formed on the electrodes. The shape of the bonding surface of the bump and the electrode is elliptical. According to a second aspect of the present invention, in the first aspect, a major axis direction of the ellipse is a direction orthogonal to a side along which the bump is located.
【００１１】請求項３の発明では、請求項２の発明にお
いて、上記楕円の長軸方向及び短軸方向における電極の
長さをそれぞれａ及びｂとした時、楕円の長軸長さＬ1
及び短軸長さＬ2 が、 Ｌ2 ≦0.８Ｌ1 ａ／２≦Ｌ1 ≦ａ ｂ／３≦Ｌ2 を満足するように選定される。According to a third aspect of the present invention, when the lengths of the electrodes in the major axis direction and the minor axis direction of the ellipse are a and b, respectively, in the invention of the second aspect, the major axis length L 1 of the ellipse is set.
And the short axis length L 2 is selected so as to satisfy L 2 ≦ 0.8 L 1 a / 2 ≦ L 1 ≦ ab / 3 ≦ L 2 .
【００１２】[0012]
【発明の実施の形態】この発明の実施の形態を図面を参
照して実施例により説明する。なお、図７〜１１と対応
する部分には同一符号を付し、その説明を省略する。図
１はこの発明の一実施例を示したものである。この例で
は電極１３上に形成されるバンプ３１の、電極１３との
接合面の形状は楕円形とされる。電極１３は図１では省
略して示しているが、チップ本体１２の方形をなす一面
の各辺に沿って例えば８０個ずつ、計３２０個配列形成
されている。各電極１３上の楕円形をなすバンプ３１
は、その楕円の長軸方向が、そのバンプ３１が沿う辺と
それぞれ直交する方向とされている。Embodiments of the present invention will be described with reference to the accompanying drawings. Parts corresponding to those in FIGS. 7 to 11 are denoted by the same reference numerals, and description thereof is omitted. FIG. 1 shows an embodiment of the present invention. In this example, the shape of the bonding surface of the bump 31 formed on the electrode 13 with the electrode 13 is elliptical. Although not shown in FIG. 1, a total of 320 electrodes 13 are formed along each side of one surface of the chip body 12, for example, 80 electrodes 13. Elliptical bumps 31 on each electrode 13
Is such that the major axis direction of the ellipse is orthogonal to the sides along which the bumps 31 extend.
【００１３】図２はバンプ３１の形状を拡大して示した
ものであり、バンプ３１は楕円形をなす接合部３１ａ
と、それに続くワイヤ破断部３１ｂとを有している。上
記のような形状を有するバンプ３１の形成は図３に示し
たように、従来と同様、超音波ホーン１５に取付けられ
たキャピラリ１６を用いて行われる。この際、従来の荷
重の設定とは異なり、ワイヤ１７の先端に形成されたボ
ール１８が電極１３に接する時の荷重に対し、超音波を
加えている時の荷重が例えば１〜1.５倍になるように設
定する。これにより、超音波を加えている時の荷重がバ
ンプ形状に影響し、つまりキャピラリ１６は超音波ホー
ン１５の振動方向に振動しながらボール１８を変形させ
ていくため、楕円形のバンプ３１を形成することができ
る。FIG. 2 is an enlarged view of the shape of the bump 31. The bump 31 has an elliptical joint 31a.
And a subsequent wire break 31b. As shown in FIG. 3, the formation of the bump 31 having the above-described shape is performed by using the capillary 16 attached to the ultrasonic horn 15, as in the related art. At this time, unlike the conventional setting of the load, the load when applying the ultrasonic wave is, for example, 1 to 1.5 times the load when the ball 18 formed at the tip of the wire 17 contacts the electrode 13. Set to be. As a result, the load when the ultrasonic wave is applied affects the bump shape, that is, the capillary 16 deforms the ball 18 while vibrating in the vibration direction of the ultrasonic horn 15, so that the elliptical bump 31 is formed. can do.
【００１４】図４は各辺の電極１３へのバンプ３１の形
成方法の一例を示したものであり、チップ本体１２の一
辺に沿って超音波ホーン１５を移動させて順次バンプ３
１を形成し、その一辺のバンプ形成が終了したら、チッ
プ本体１２を９０°回転させて次の辺のバンプ３１を形
成し、これを繰り返して４辺の電極１３全てにバンプ形
成を行うようにしたものである。FIG. 4 shows an example of a method of forming the bumps 31 on the electrodes 13 on each side. The ultrasonic horn 15 is moved along one side of the chip body 12 to sequentially form the bumps 3.
1 is formed, and when the formation of the bumps on one side is completed, the chip body 12 is rotated by 90 ° to form the bumps 31 on the next side, and this is repeated so that the bumps are formed on all the electrodes 13 on the four sides. It was done.
【００１５】上記のようなバンプ３１を有するバンプ付
半導体チップ（以下、チップと言う。）３２において
は、隣接バンプ間の間隔が図９に示した従来の円形の接
合面を有するバンプ１４よりも広くなり、つまり同一接
合面面積としても楕円形ゆえ、隣接バンプ間の間隔を広
くすることができるため、その分樹脂封止工程における
バンプ間を通過する樹脂の流れを良くすることができ
る。In the bumped semiconductor chip (hereinafter, referred to as a chip) 32 having the bumps 31 as described above, the distance between adjacent bumps is larger than that of the conventional bump 14 having a circular bonding surface shown in FIG. Since the area becomes wider, that is, even if the area of the same joint surface is elliptical, the interval between adjacent bumps can be made wider, so that the flow of the resin passing between the bumps in the resin sealing step can be improved.
【００１６】なお、楕円形の大きさは図２に示したよう
に、楕円の長軸方向及び短軸方向における電極１３の長
さをそれぞれａ及びｂとし、楕円の長軸長さをＬ1 ，短
軸長さＬ2 とした時、これらａ，ｂ，Ｌ1 及びＬ2 が下
式を満足するように選定するのが好ましい。 Ｌ2 ≦0.８Ｌ1 ａ／２≦Ｌ1 ≦ａ ｂ／３≦Ｌ2 図５はチップ３２を樹脂封止して基板２１に実装する様
子を示したものであり、図５Ａは樹脂２３を周辺からチ
ップ本体１２の下へ流し込む場合を示し、図５Ｂは樹脂
２３をチップ本体１２の下から周辺に押し広げる場合を
示している。いずれの場合にもバンプ間の間隔が従来に
比し、広いため、樹脂２３は良好に流れ、よってエアー
の巻き込みは生じにくくなり、封止樹脂２３′内にボイ
ドが発生しにくいものとなる。As shown in FIG. 2, the elliptical shape is such that the lengths of the electrodes 13 in the major axis direction and the minor axis direction of the ellipse are a and b, respectively, and the major axis length of the ellipse is L 1. , when the short axis length L 2, these a, b, preferably L 1 and L 2 is selected to satisfy the following equation. L 2 ≦ 0.8 L 1 a / 2 ≦ L 1 ≦ ab / 3 ≦ L 2 FIG. 5 shows a state in which the chip 32 is sealed with a resin and mounted on the substrate 21, and FIG. FIG. 5B shows a case in which the resin 23 is spread from below the chip body 12 to the periphery. In any case, since the interval between the bumps is wider than in the conventional case, the resin 23 flows well, so that the entrainment of air is less likely to occur, and voids are less likely to occur in the sealing resin 23 '.
【００１７】図６は上述のようにしてチップ３２が基板
２１に実装された状態を示したものである。なお、上述
した例では楕円形をなすバンプ３１は、その楕円の長軸
方向が、そのバンプ３１が沿うチップ本体１２の辺と直
交する方向とされているが、例えばチップ本体１２の中
央部から放射状に樹脂２３が流れる場合には、その流れ
に対応して楕円の長軸方向をチップ本体１２の中心から
の放射方向に向けることも考えられる。つまり、楕円の
長軸方向は樹脂２３の流れる方向に対応して選定されう
る。FIG. 6 shows a state in which the chip 32 is mounted on the substrate 21 as described above. In the above-described example, the elliptical bump 31 has a major axis direction perpendicular to a side of the chip body 12 along which the bump 31 extends. When the resin 23 flows radially, the major axis of the ellipse may be directed in the radial direction from the center of the chip body 12 corresponding to the flow. That is, the major axis direction of the ellipse can be selected according to the direction in which the resin 23 flows.
【００１８】[0018]
【発明の効果】以上説明したように、この発明によれば
隣接バンプ間の間隔が従来に比し、広いチップ３２を得
ることができるため、基板２１への実装時に封止用の樹
脂２３がバンプ間を通過しやすくなり、即ち樹脂２３が
良好かつ一様に流れ、エアーの巻き込みが生じにくくな
るため、封止樹脂２３′内のボイドの発生を抑制するこ
とができ、従って信頼性に優れたフリップチップ実装を
実現することができる。As described above, according to the present invention, it is possible to obtain a chip 32 in which the distance between adjacent bumps is wider than in the conventional case. Since the resin 23 easily flows between the bumps, that is, the resin 23 flows favorably and uniformly, and the air is hardly caught, the generation of voids in the sealing resin 23 'can be suppressed, and therefore, the reliability is excellent. Flip chip mounting can be realized.
【図１】この発明の一実施例を示す底面図。FIG. 1 is a bottom view showing one embodiment of the present invention.
【図２】Ａは図１におけるバンプの拡大図、Ｂはその側
面図。2A is an enlarged view of a bump in FIG. 1, and FIG. 2B is a side view thereof.
【図３】バンプの形成方法を説明するための図。FIG. 3 is a diagram illustrating a method of forming a bump.
【図４】チップの各電極へのバンプの形成方法を説明す
るための図。FIG. 4 is a diagram for explaining a method of forming bumps on each electrode of a chip.
【図５】チップの基板への実装方法及び封止樹脂の流れ
を説明するための図。FIG. 5 is a diagram for explaining a method of mounting a chip on a substrate and a flow of a sealing resin.
【図６】Ａはチップの基板への実装状態を示す部分拡大
図、ＢはそのＥＥ断面図、ＣはそのＦＦ断面図。6A is a partially enlarged view showing a mounted state of a chip on a substrate, FIG. 6B is an EE sectional view thereof, and C is an FF sectional view thereof.
【図７】従来のチップを示す底面図。FIG. 7 is a bottom view showing a conventional chip.
【図８】従来のバンプの形成方法を説明するための図。FIG. 8 is a view for explaining a conventional bump forming method.
【図９】Ａは図７におけるバンプの拡大図、Ｂはその側
面図。9A is an enlarged view of a bump in FIG. 7, and FIG. 9B is a side view thereof.
【図１０】チップの基板への実装方法を説明するための
図。FIG. 10 is a diagram for explaining a method of mounting a chip on a substrate.
【図１１】封止樹脂内にボイドが発生する様子を示す
図。FIG. 11 is a diagram illustrating a state in which voids are generated in a sealing resin.
Claims (3)
配列形成され、それら電極上にバンプがそれぞれ形成さ
れてなるバンプ付半導体チップにおいて、 上記バンプの、上記電極との接合面の形状が楕円形とさ
れていることを特徴とするバンプ付半導体チップ。1. A bumped semiconductor chip in which electrodes are arranged and formed along each side of one surface of a chip body, and bumps are respectively formed on the electrodes, wherein a shape of a bonding surface of the bumps with the electrodes is provided. Wherein the semiconductor chip has an elliptical shape.
おいて、 上記楕円の長軸方向がそのバンプが沿う辺と直交する方
向とされていることを特徴とするバンプ付半導体チッ
プ。2. The semiconductor chip with bump according to claim 1, wherein the major axis direction of the ellipse is a direction orthogonal to a side along which the bump extends.
おいて、 上記楕円の長軸方向及び短軸方向における上記電極の長
さをそれぞれａ及びｂとした時、上記楕円の長軸長さＬ
1 及び短軸長さＬ2 が、 Ｌ2 ≦0.８Ｌ1 ａ／２≦Ｌ1 ≦ａ ｂ／３≦Ｌ2 を満足するように選定されていることを特徴とするバン
プ付半導体チップ。3. The semiconductor chip with bumps according to claim 2, wherein the lengths of the electrodes in the major axis direction and the minor axis direction of the ellipse are a and b, respectively.
A semiconductor chip with bumps, wherein 1 and the minor axis length L 2 are selected so as to satisfy L 2 ≦ 0.8 L 1 a / 2 ≦ L 1 ≦ ab / 3 ≦ L 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9239666A JPH1187418A (en) | 1997-09-04 | 1997-09-04 | Semiconductor chip with bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9239666A JPH1187418A (en) | 1997-09-04 | 1997-09-04 | Semiconductor chip with bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1187418A true JPH1187418A (en) | 1999-03-30 |
Family
ID=17048108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9239666A Pending JPH1187418A (en) | 1997-09-04 | 1997-09-04 | Semiconductor chip with bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1187418A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002334901A (en) * | 2001-05-08 | 2002-11-22 | Nec Corp | Semiconductor device |
| JP2011171720A (en) * | 2010-01-20 | 2011-09-01 | Connectec Japan Corp | Mounting substrate, production method thereof, electronic component, and production method thereof |
-
1997
- 1997-09-04 JP JP9239666A patent/JPH1187418A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002334901A (en) * | 2001-05-08 | 2002-11-22 | Nec Corp | Semiconductor device |
| JP2011171720A (en) * | 2010-01-20 | 2011-09-01 | Connectec Japan Corp | Mounting substrate, production method thereof, electronic component, and production method thereof |
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