JPH1184428A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to completely suppress the generation of flicker even with a liquid crystal display device of a large display screen by constituting the capacitance between the gate electrodes and source electrodes of thin-film transistors(TFTs) to be small on the input terminal side of gate signal lines and large on the terminal sides thereof. SOLUTION: The gate signal lines GL which extend in an x-direction and are arranged in juxtaposition in a y-direction are formed on the liquid crystal side surface of a transparent substrate. Pixel electrodes ITO 1 consisting of transparent conductive films are formed in the greater part of the pixel regions enclosed by the gate signal lines GL and drain signal lines DL. The drain signal lines DL are previously formed on the gate insulating films GI, insulating film GI and semiconductor layer AS of the thin-film transistors TFTS in its forming region and are formed of the successive laminate of, for example, chromium and aluminum. The thin-film transistors TFTs consist of MIS type and the capacitors between the gate electrodes and source electrodes thereof are constituted small on the input terminal side of the gate signal lines GL and large on the terminal side thereof.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device, and more particularly to an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art A liquid crystal display device of this type is arranged in the x direction on a liquid crystal side surface of one of a pair of transparent substrates disposed opposite to each other with a liquid crystal interposed therebetween and arranged in the y direction. And a drain signal line extending in the y direction and juxtaposed in the x direction, and each region surrounded by each of the signal lines is a pixel region.

In each of the pixel regions, a thin film transistor turned on by a scanning signal from the gate signal line, and a pixel electrode to which a video signal from the drain signal line is applied via the turned on thin film transistor. Is provided.

[0004] Such a liquid crystal display device can form a good contrast and is an indispensable technique especially for a color liquid crystal display device.

[0005] In order to prevent the TFT driving ability near the end from being deteriorated due to the waveform distortion of the gate bus line, the size of the TFT is increased toward the end of the gate bus line in the prior art. 258261. However, in the above prior art, there was no idea to make the amount of voltage (ΔV) entering the pixel electrode constant via the gate-source capacitance (Cgs) without changing the size of the TFT.

Therefore, in the above-mentioned prior art, since the size of the TFT is different for each location in the display area, the driving conditions of the TFT are different for each location, and it is difficult to find the optimal driving conditions for the liquid crystal display device. There is a problem that the design of the liquid crystal display device is also complicated.

[0007]

However, in such a liquid crystal display device, the flickering of the screen, which is called a flicker, has become a problem that cannot be ignored with the recent trend toward larger size and higher definition. Was. Especially the diagonal length of the display area is 34cm (13 type)
The above liquid crystal display device has become a problem that cannot be ignored.

The inventors of the present invention have investigated the causes of flicker and have found the following.

First, since the gate signal line must be formed long, the scanning signal line inputted to the signal line will be distorted toward the terminal side due to the influence of the resistance and capacitance of the signal line.

This waveform distortion delays the gate-off timing of the thin film transistor, and
This reduces the source electrode potential drop component due to the voltage jumped through the gate-source capacitance when the gate is turned off. This means that the source electrode potential on the terminal side becomes higher than the input terminal side of the gate signal line.

For this reason, since an electrode (common electrode) opposed to the pixel electrode via the liquid crystal is uniformly applied with a constant potential in the display surface, the voltage applied to the liquid crystal is applied to the gate signal line. Will be different between the input terminal side and the terminal side.

Since the AC drive is performed to invert the potential applied to the liquid crystal in order to avoid the polarization of the liquid crystal, the magnitude of the voltage applied to the liquid crystal between the input terminal side and the terminal side of the gate signal line is changed. Is inverted every half cycle of the AC driving, and the screen flickers due to a change in luminance.

In particular, a 13-inch liquid crystal display device is 20 cm long,
It has a display area of 27 cm wide and the gate signal line length is 2
7 cm or more, and the difference between the voltage jumped in via the gate-source capacitance between the input terminal side and the terminal side of the gate signal line becomes so large that it cannot be ignored.

Therefore, in a liquid crystal display device having a gate signal line length of 27 cm or more (13 type or more), it has become difficult to completely eliminate flicker simply by adjusting the potential of the common electrode.

When each signal line and thin film transistor are formed by selective etching using photolithography technology, the pattern of the thin film transistor in each pixel region is completely changed due to distortion of the optical system of the exposure apparatus or bending of the transparent substrate. It is difficult to make them uniform.

In this case, if the capacitance between the gate and the source of the thin film transistor becomes non-uniform due to the variation in the pattern, the amount of decrease in the source potential due to the capacitance between the gate and the source when the gate is turned off is not constant in the screen.

Therefore, also in this case, for the same reason as described above, the screen flickers due to the change in luminance.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a liquid crystal display device that can completely suppress flicker even in a liquid crystal display device having a large display screen.

[0019]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

Means 1. A gate signal line provided over an insulating substrate, a driving circuit electrically connected to the gate signal line and outputting a gate driving voltage, first and second thin film transistors each having a source electrode, a gate electrode, and a drain electrode; A first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; a second pixel electrode electrically connected to one of a source electrode and a drain electrode of the second thin film transistor; First
A first video signal line electrically connected to the other of the source electrode and the drain electrode of the thin film transistor; and a second video signal line electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor. The gate electrode of the first thin film transistor is connected to the first of the gate signal lines.
And the gate electrode of the second thin film transistor is electrically connected to a second portion of the gate signal line farther from the drive circuit than the first portion of the gate signal line, and the first and second gates are connected to the second portion. A source electrode of the thin-film transistor is provided on the gate electrode with a channel length apart from the drain electrode and opposed by a channel width, and a channel length and a channel width of the second thin-film transistor are the first and the second.
The capacitance between the second pixel electrode and the gate signal line is substantially equal to the channel length and the channel width of the thin film transistor, and is larger than the capacitance between the first pixel electrode and the gate signal line. It is characterized by having done.

In the liquid crystal display device configured as described above, the positive shift of the potential of the pixel electrode due to the waveform distortion of the scanning signal to the gate signal line is reduced by the capacitance Cgs of the jump voltage.
The voltage applied to each pixel electrode of the gate signal line on the input terminal side near the drive circuit, on the input terminal side, far from the drive circuit, and on the terminal side by offsetting by the negative shift of the potential of the pixel electrode depending on Are equal.

For this reason, it is possible to suppress the flicker of the screen due to the change in luminance.

Means 2. A gate signal line provided over an insulating substrate, a driving circuit electrically connected to the gate signal line and outputting a gate driving voltage, first and second thin film transistors each having a source electrode, a gate electrode, and a drain electrode; A first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; a second pixel electrode electrically connected to one of a source electrode and a drain electrode of the second thin film transistor; First
A first video signal line electrically connected to the other of the source electrode and the drain electrode of the thin film transistor; and a second video signal line electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor. The gate electrode of the first thin film transistor is connected to the first of the gate signal lines.
And the gate electrode of the second thin film transistor is electrically connected to a second portion of the gate signal line farther from the drive circuit than the first portion of the gate signal line. The capacitance between the gate signal lines is
The capacitance between the first pixel electrode and the gate signal line is larger than the capacitance between the first pixel electrode and the gate signal line, and the source electrodes of the first and second thin film transistors are separated from the drain electrode by a channel length on the gate electrode. Between the portion where one of the source and drain electrodes of the first and second thin film transistors is connected to the pixel electrode and no longer overlaps with the gate electrode. Is formed to be smaller than the channel width of the first and second thin film transistors.

In the liquid crystal display device configured as described above, even if the shift occurs during the formation of the source electrode of the thin film transistor, the change in the area of the overlapping portion of the source electrode with the gate electrode can be extremely reduced.

Therefore, the change in the capacitance Cgs between the gate electrode and the source electrode can be made extremely small, and the flicker of the screen due to the change in luminance can be suppressed.

Means 3. A first gate signal line provided on the insulating substrate; a capacitor line provided on the insulating substrate adjacent to the first gate signal line; and a driving voltage electrically connected to the gate signal line. And first and second thin film transistors having a source electrode, a gate electrode, and a drain electrode; a first pixel electrode electrically connected to one of the source electrode and the drain electrode of the first thin film transistor; A second pixel electrode electrically connected to one of a source electrode and a drain electrode of the thin film transistor;
A first video signal line electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor, and a second video signal line electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor A gate electrode of the first thin film transistor is electrically connected to a first portion of the first gate signal line, and a gate electrode of the second thin film transistor is connected to a first portion of the first gate signal line. A source portion of the first and second thin film transistors is separated from the drain electrode by a channel length on the gate electrode, and is opposed to the drain portion by a channel width. And the channel length and the channel width of the second thin film transistor are substantially equal to the channel length and the channel width of the first thin film transistor. In addition, the first and second pixel electrodes partially overlap with the capacitance line via an insulating film, and the area where the second pixel electrode and the capacitance line overlap is changed to the area where the first pixel electrode and the capacitance line overlap. It is characterized in that it has been made smaller.

According to the liquid crystal display device having the above-described configuration, the potential reduction component of the pixel electrode voltage due to the leakage of the scanning signal fluctuates between the input terminal side and the terminal side of the gate signal line due to the waveform distortion of the scanning signal. It can be suppressed by adjusting the storage capacity. For this reason, flickering of the screen due to a change in luminance can be suppressed.

Means 4. A first gate signal line provided on an insulating substrate; a second gate signal line provided on the insulating substrate adjacent to the first gate signal line; and a gate electrically connected to the first gate signal line. A driving circuit for outputting a driving voltage; first and second thin film transistors having a source electrode, a gate electrode, and a drain electrode; and a first pixel electrode electrically connected to one of the source electrode and the drain electrode of the first thin film transistor A second pixel electrode electrically connected to one of a source electrode and a drain electrode of the second thin film transistor; and a first video signal electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor And a second video signal line electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor. A gate electrode of the first transistor is electrically connected to a first portion of the first gate signal line, and a gate electrode of the second thin film transistor is farther from the driving circuit than the first portion of the first gate signal line. 2 and electrically connected to the first and second portions.
A source electrode of the thin film transistor is provided on the gate electrode at a channel length apart from the drain electrode and opposed by a channel width, and a channel length and a channel width of the second thin film transistor are equal to a channel length and a channel length of the first thin film transistor. The first and second pixel electrodes are substantially equal to a channel width, and the first and second pixel electrodes partially overlap with the second gate signal line via an insulating film, and the area where the second pixel electrode and the second gate signal line overlap with each other is: The first pixel electrode and the second pixel electrode
It is characterized in that the area is smaller than the overlapping area of the gate signal lines.

In the liquid crystal display device having the above-described configuration, the potential reduction component of the pixel electrode voltage due to the leakage of the scanning signal fluctuates between the input terminal side and the terminal side of the gate signal line due to the waveform distortion of the scanning signal. It can be suppressed by adjusting the storage capacity. For this reason, flickering of the screen due to a change in luminance can be suppressed.

Further, since the electrode of the storage capacitor is also used as the gate signal line of the adjacent line, the aperture ratio of the pixel is improved.

Means 5 A gate signal line provided over an insulating substrate, a driving circuit electrically connected to the gate signal line and outputting a gate driving voltage, first and second thin film transistors each having a source electrode, a gate electrode, and a drain electrode; A first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; a second pixel electrode electrically connected to one of a source electrode and a drain electrode of the second thin film transistor; First
A first video signal line electrically connected to the other of the source electrode and the drain electrode of the thin film transistor; and a second video signal line electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor. The gate electrode of the first thin film transistor is connected to the first of the gate signal lines.
And the gate electrode of the second thin film transistor is electrically connected to a second portion of the gate signal line farther from the drive circuit than the first portion of the gate signal line. The capacitance between the second video signal lines is larger than the capacitance between the first pixel electrodes and the first video signal lines.

In the liquid crystal display device having the above-described structure, the potential drop component of the pixel electrode voltage due to the leakage of the scanning signal fluctuates between the input terminal side and the terminal side of the gate signal line due to the waveform distortion of the scanning signal. It can be suppressed by adjusting the capacitance (or the capacitance between the source and the drain) between the pixel electrode and the video signal line. For this reason, flickering of the screen due to a change in luminance can be suppressed.

Means 6. First and second thin film transistors having a gate signal line provided on a first insulating substrate, a terminal electrically connected to the gate signal line for inputting a gate drive voltage, and a source electrode, a gate electrode, and a drain electrode A first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor;
A second pixel electrode electrically connected to one of a source electrode and a drain electrode of the second thin film transistor; and a first video signal line electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor. A second video signal line electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor, a transparent second insulating substrate provided to overlap the first insulating substrate,
A transparent common electrode provided on the insulating substrate at a position facing the first and second pixel electrodes;
A liquid crystal provided between the first and second pixel electrodes; and a light-shielding film provided on the second insulating substrate and surrounding the first and second pixel electrodes. The first thin film transistor is electrically connected to a first portion of the gate signal line, and the gate electrode of the second thin film transistor is electrically connected to a second portion farther from the terminal than the first portion of the gate signal line; The area of the portion of the second pixel electrode covered by the light-shielding film is smaller than the area of the portion of the first pixel electrode covered by the light-shielding film.

In the liquid crystal display device having the above-described configuration, the potential reduction component of the pixel electrode voltage due to the leakage of the scanning signal fluctuates between the input terminal side and the terminal side of the gate signal line due to the waveform distortion of the scanning signal. It can be suppressed by adjusting the pixel capacitance (liquid crystal capacitance). For this reason, flickering of the screen due to a change in luminance can be suppressed.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the liquid crystal display device according to the present invention will be described below with reference to the drawings.

Embodiment 1 << Equivalent Circuit of Liquid Crystal Display Panel >> FIG. 2 is a circuit diagram showing an equivalent circuit on one transparent substrate (TFT substrate) side of the transparent substrates constituting the liquid crystal display panel. Although the figure is a circuit diagram, it is drawn corresponding to an actual geometric arrangement.

On the liquid crystal side surface of the TFT substrate TFT-LCD in FIG. 2, gate signal lines (also referred to as scanning signal lines) GL extending in the x direction and juxtaposed in the y direction are provided. A drain signal line (also referred to as a video signal line) D which is insulated by the line GL and extends in the y direction and is arranged in parallel in the x direction.
L are formed.

A rectangular region surrounded by the gate signal line GL and the drain signal line DL constitutes a pixel region, and each pixel region has one gate signal line G.
The thin film transistor TFT turned on by the supply of the scanning signal (voltage) from L and the pixel electrode ITO1 to which the video signal (voltage) supplied from one drain signal line is applied via the turned on thin film transistor TFT. Provided.

The pixel electrode ITO1 is made of, for example, Indium
It is composed of a transparent conductive layer made of -Tin-Oxide.

An additional capacitance element Cadd is provided between the pixel electrode ITO1 and the other gate signal line GL.
The video signal applied to TO1 is configured to be accumulated for a long time.

It should be noted that R,
Although any of the symbols G and B is attached, they indicate the three primary colors of red, green, and blue, and each pixel area is assigned a corresponding color. More specifically, a filter substrate (second transparent substrate SUB2) arranged to face the TFT substrate (first transparent substrate SUB1)
A filter of a color corresponding to the side is formed.

The display panel is connected to a scanning signal line driving circuit 104 and a video signal line driving circuit 103 as external circuits.

A scanning signal is sequentially input to each gate signal line from the scanning signal line driving circuit 104, and a video signal is input to each drain signal line from the video signal line driving circuit section 103 in accordance with the timing. ing.

Further, a power supply section 102 and a controller section 101 are connected to the scanning signal line drive circuit section 104 and the video signal line drive circuit section 103, whereby power is supplied to each circuit section and signals are transmitted. It is supposed to.

Note that the TFT substrate T thus configured
A black matrix layer is formed on the surface of the other transparent substrate (filter substrate) facing the FT with the liquid crystal therebetween on the liquid crystal side so as to border the frame of the pixel region so as to cover the pixel region. A color filter is formed such that the periphery thereof overlaps the black matrix layer BM.

A common electrode made of a transparent conductive layer is formed via a protective film formed so as to cover the black matrix layer and the color filters.

Further, an alignment film for regulating the alignment of the liquid crystal is formed on the upper surface of the common electrode.

<< Configuration of Pixel Region >> FIG. 3 is a plan view showing a specific configuration of the pixel region corresponding to the dotted frame A in FIG.

FIG. 4 is a sectional view taken along the line IV-IV of FIG. 3, FIG. 5 is a sectional view taken along the line VV, and FIG. 6 is a sectional view taken along the line VI-VI.

First, on the liquid crystal side surface of the transparent substrate SUB1,
A gate signal line G extending in the x direction and juxtaposed in the y direction
L is formed.

The gate signal line GL is formed on the surface of a conductive layer gl made of, for example, aluminum by an aluminum oxide film AOF.
(Formed by anodization).

A pixel electrode ITO1 made of a transparent conductive film (for example, Indium-Tin-Oxide) is formed in most of the pixel region surrounded by the gate signal line GL and a drain signal line DL described later. .

The gate signal line GL at the lower left of the drawing in the pixel area
The upper part is a region where a thin film transistor TFT is formed. In this region, a gate insulating film GI made of, for example, SiN, a semiconductor layer AS made of i-type amorphous Si, a drain electrode SD2 and a source electrode SD1 are sequentially formed. It is formed by being laminated.

It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that it is understood that the source and the drain are switched during the operation. However, in this specification, the electrode directly connected to the pixel electrode ITO1 is expressed as a fixed source electrode.

The drain electrode SD2 and the source electrode SD1 are formed simultaneously with the drain signal line DL.

That is, the drain signal line DL is formed in the region where the drain signal line DL is formed at the same time when the gate insulating film GI of the thin film transistor TFT and the semiconductor layer AS are formed in advance.
I, formed on the semiconductor layer AS and formed, for example, by a sequentially laminated body of chromium and aluminum (see FIG. 5). The reason why the insulating film GI and the semiconductor layer AS are formed in the region where the drain signal line DL is formed is, for example, to reduce the possibility that the drain signal line DL crosses over a step.

The drain electrode S of the thin film transistor TFT
D2 is formed integrally with the drain signal line DL, and the source electrode SD1 is formed so as to be separated from the drain electrode SD2 by a predetermined channel length, and extends over a part of the pixel electrode ITO1 to be directly superimposed. It is formed.

As shown in FIG. 6, the additional capacitance element Cadd has a gate signal line (another gate signal line adjacent to the gate signal line for driving the thin film transistor TFT) GL.
Is a conductive layer d1 formed simultaneously with the drain signal line DL and a conductive layer ITO2 formed simultaneously with the pixel electrode ITO1 and overlapped with the conductive layer d1 as the other electrode, and is an insulating film interposed therebetween. An aluminum oxide film AOF (or a silicon nitride film GI) may be used as a dielectric film.

The insulating film GI and the semiconductor layer AS are formed simultaneously with their formation in the thin film transistor TFT, and the conductive layer d1 as the other electrode is formed.
Is formed so as to extend over a part of the pixel electrode ITO1 and directly overlap with the pixel electrode ITO1.

Then, a protective film PSV1 made of SiN is formed on the surface of the pixel region configured as described above, so as to avoid deterioration of characteristics due to direct contact of the liquid crystal with the thin film transistor TFT.

An alignment film (not shown) for regulating the alignment of the liquid crystal is formed on the entire surface of the protective film PSV1.

<< Operation of TFT >> FIG. 15 is a diagram showing an equivalent circuit of a unit pixel of a TFT active matrix liquid crystal display device.

The thin film transistor TFT is turned on (the resistance value between the source and the drain is reduced) by biasing the gate electrode with a positive voltage with respect to the source electrode, and the bias supplied to the gate electrode is close to zero. As a result, the transistor has an off state, that is, a transfer characteristic that the resistance value between the source and the drain increases.

FIG. 16 is a waveform chart for explaining an example of the operation of the liquid crystal display device shown in FIG.

Each signal V shown in FIG.
The G, VD and the voltage PXV of the pixel PIX are depicted in a time-shifted manner in the order of the signals VG, VD and PXV in order to prevent the distinction of each waveform from being obscured due to their overlapping.

Writing of the video signal (drain signal) VD supplied from the video signal line DL to the pixel PIX coupled to the gate signal line Gi (GL) selected according to the high level of the scanning signal (gate signal) VG. Is performed. At this time, as shown by a dotted line in FIG. 16, the voltage PXV of the pixel PIX is changed according to the fact that the TFT turned on has a resistance component and the pixel PIX is a capacitive element Cpix. Stand up according to a constant. FIG. 16 initially shows a positive-level video signal VD that brings a pixel (or a liquid crystal cell) into a high gradation state. In response to the selection of the next gate signal line Gi + 1 (GL), the scanning signal VG shown in FIG. 16 is changed from the high-level selection level to the low-level non-selection level. This gives TF
Since T is turned off, the written video signal V
D is held in the pixel PIX acting as the capacitive element Cpix. In response to the switching of the scanning signal VG from the high level to the low level, the pixel voltage PXV changes to the pixel PIX.
A potential reduction component ΔV is generated by a parasitic capacitance Cgs between the gate electrode of the TFT (or an electrode connected to the pixel electrode in a source electrode or a drain electrode of the TFT; hereinafter, it is treated as a source electrode for convenience of description). Note that by switching the scanning signal VG from a low level to a high level,
Pixel PI by coupling Cgs between gate and source
The voltage jumping into X can be canceled by writing the video signal VD from the drain line Xi (DL). However, the voltage jumping into the pixel PIX when the scanning signal VG switches from the high level to the low level is changed by writing the video signal VD. I can't counter it.

FIG. 16 shows that the video signal VD of a low gradation level is supplied for one frame thereafter.

Generally, since the liquid crystal display device is driven by an alternating current, the polarity of the video signal VD is switched between positive and negative for each period of the scanning signal VG and supplied.

That is, as shown in FIG.
When G is again set to the high selection level, the video signal VD is set to a desired negative gray scale level. Note that FIG. 16 shows an example in which the negative gradation level is set to a high level.
Also in this case, the TFT to be turned on has a resistance component, and the pixel PIX has the capacitive element Cpi.
Since it is x, the voltage PXV of the pixel falls according to the time constant corresponding thereto. Next gate signal line Gi + 1
In response to the selection (not shown), the scanning signal VG shown in FIG. 16 is changed from the high-level selection level to the low-level non-selection level. As a result, the TFT is turned off, so that the video signal VD is applied to the capacitive element Cpix.
Is held in the pixel PIX acting as

In response to the switching of the scanning signal VG from the high level to the low level, the voltage PXV of the pixel has a potential reduction component ΔV due to the parasitic capacitance Cgs between the gate electrode and the source electrode of the TFT as described above. Similarly to the case of the positive polarity, the voltage jumping into the pixel PIX due to the coupling Cgs between the gate and the source by switching the scanning signal VG from the low level to the high level is canceled by writing the video signal VD from the drain signal line Xi. However, the voltage that jumps into the pixel PIX when the scanning signal VG switches from the high level to the low level cannot be canceled by writing the video signal VD. Therefore, when the polarity is negative, the coupling C between the gate and the source is the same as in the case of the positive polarity.
gs, the voltage jumping into the pixel PIX is the pixel voltage P
XV is reduced in the negative direction.

FIG. 16 shows that the video signal VD of a low gray level is supplied for one frame thereafter.

As described above, when the scanning signal VG changes from the high level to the low level in both the positive polarity and the negative polarity of the liquid crystal AC driving, the parasitic capacitance Cgs between the gate electrode and the source electrode of the TFT causes the pixel voltage PXV to change. Causes a potential drop component ΔV with respect to the level of the video signal VD at the time of writing, as shown by a dotted line in FIG.

Accordingly, the bias voltage Vcom applied to the common electrode COM of the liquid crystal display panel is substantially intermediate between the positive polarity and the negative polarity of the pixel voltage PXV, as shown by the two-dot chain line in FIG. (Optimum common electrode voltage). That is, by applying an optimum common electrode voltage to the common electrode COM in consideration of the potential drop ΔV of the pixel voltage PXV, it is possible to perform a substantially AC drive of the liquid crystal.

If the bias voltage Vcom applied to the common electrode COM deviates from the above-mentioned optimum common electrode voltage, a difference occurs in the voltage Vlc applied to the liquid crystal during the period of the positive polarity and the negative polarity of the liquid crystal AC drive. , A periodic luminance change called flicker occurs, and the display quality is significantly reduced.

<< Operation of Storage Capacitor >> In FIG.
Cgs is a parasitic capacitance formed between the gate electrode and the source electrode of the thin film transistor TFT described above. The dielectric of the parasitic capacitance Cgs is an interlayer insulating film between the gate electrode and the source electrode. Cpix is a liquid crystal capacitance formed between the transparent pixel electrode PIX and the common transparent pixel electrode COM. The dielectric film of the liquid crystal capacitor Cpix is a liquid crystal and an alignment film. Vlc is a voltage applied to the liquid crystal.

When the thin-film transistor TFT switches, the storage capacitor Cadd has a pixel electrode potential PXV.
In order to reduce the influence of the potential change ΔVG of the scanning signal. This situation is expressed by Expression 1.

ΔV = {Cgs / (Cgs + Cds1 + Cds2 + Cadd + Cpix)} × ΔVG Equation 1 Here, ΔV is the potential change ΔV of the scanning signal described above.
G represents a potential drop component of the pixel voltage PXV. Although this potential drop component ΔV causes a DC component applied to the liquid crystal, the larger the storage capacitor Cadd, the smaller the potential drop component ΔV of the pixel voltage PXV can be made. In addition, the storage capacitance element Cadd also has a function of prolonging the discharge time, and stores video information after the thin film transistor TFT is turned off for a long time. The reduction of the DC component applied to the liquid crystal can improve the life of the liquid crystal and reduce so-called image sticking in which the previous image remains when the liquid crystal display screen is switched.

In FIG. 15 and Equation 1, Cds1 is a parasitic capacitance between the source electrode SD1 and the drain electrode SD2 of the thin film transistor, and is also a capacitance between the pixel electrode PIX and the drain signal line Di.

Cds2 indicates a parasitic capacitance between the pixel electrode PIX and the adjacent drain signal line Di + 1.
Cgd indicates a parasitic capacitance between the gate electrode and the drain electrode.

As shown in FIG. 3, since the gate electrode GL is made large so as to cover the i-type semiconductor layer AS, the area of overlap with the source electrode SD1 and the drain electrode SD2 increases, so that the parasitic capacitance Cgs increases. Therefore, the pixel electrode potential PXV has an adverse effect of being easily affected by the scanning signal VG. However, the provision of the storage capacitor Cadd has an effect that the pixel electrode potential PXV is less likely to be affected by the parasitic capacitance Cgs.

In this embodiment, the capacity of the pixel is about 150
Since the capacitance is fF, the capacitance of the storage capacitor Cadd is set to about 100 fF in consideration of the writing characteristics. Since the parasitic capacitance Cgs is approximately 15 fF, the storage capacitance element Cadd
Is six times or more the parasitic capacitance Cgs.

In FIG. 2, FIG. 3, and FIG. 6, the storage capacitor Cadd is formed by overlapping a part of the gate signal line GL of the adjacent pixel with the pixel electrode ITO1 via an insulating film. Of the storage capacitor C
Add is not limited to this, and as shown in FIGS. 12, 13 and 14, the capacitance line C is provided separately from the gate signal line GL.
A storage capacitor method may be used in which a storage capacitor Cadd is formed by providing L and overlapping the capacitor line CL with the pixel electrode ITO1 via an insulating film. In this embodiment, the additional capacity method is as follows.
It has the advantage that the aperture ratio can be increased, and the disadvantage that the distribution capacitance of the gate signal line GL increases. Further, in the present embodiment, the storage capacitor method has an advantage that the distributed capacitance of the gate signal line GL can be reduced, a point that the aperture ratio is reduced by the provision of the capacitor line CL, and an increase in the number of manufacturing steps.

<< Measures to Prevent Variation of Parasitic Capacitance Cgs >> Conventionally, the display area of a liquid crystal display device is a 10-inch display area (diagonal 25.4c).
m), the production variation of the parasitic capacitance Cgs between the gate electrode and the source electrode is small, and the optimum common electrode voltage Vcom applied to the common electrode COM is uniquely determined.

However, when the display area of the liquid crystal display device is larger than the 13-inch (diagonal 34 cm), the parasitic capacitance Cgs
In this case, there is a problem that the optimum common electrode voltage Vcom applied to the common electrode COM is greatly different in each part of the display region and cannot be uniquely determined.

In order to solve the above problem, in this embodiment, in particular, the source electrode S of the thin film transistor TFT is used.
In D1, as shown in the enlarged view of FIG. 1, at a portion connected to the pixel electrode ITO1 and a portion not overlapping with the gate electrode, the width thereof is larger than the channel width w of the thin film transistor. It is formed small.

That is, in FIG.
D2 is formed so as to extend from the drain signal line DL on the gate signal line GL in the running direction and then bend toward the pixel electrode ITO1.

In this case, what substantially functions as the drain electrode SD2 is a bent portion directed to the pixel electrode ITO1, and the length thereof determines the channel width w of the thin film transistor TFT.

The source electrode SD1 is opposed to the bent portion of the drain electrode SD2 and is separated from the bent portion of the drain electrode SD2 by an amount corresponding to the channel length l.
It extends to the side to establish connection with the pixel electrode ITO1.

Therefore, the drain electrode S of the source electrode SD1
The length of the side facing D2 is the channel width.

Here, the length of the width w0 orthogonal to the extending direction of the source electrode SD1 is formed smaller than the channel width w.

The source electrode SD1 thus configured
Is formed so as to be displaced in the y direction in the drawing when forming it, the area of the overlapping portion of the source electrode SD1 with respect to the gate signal line GL does not largely change. Width w0 orthogonal to the extending direction of source electrode SD1
Is formed relatively small.

When a displacement occurs in the x direction in the figure, there is no change in the area of the overlapping portion of the source electrode SD1 with the gate signal line GL.

Therefore, even if the position shift occurs in the rotational direction θ, the gate signal line G of the source electrode SD1 is not affected.
The area of the overlapped portion with respect to L does not change significantly.

Therefore, the thin film transistor TFT in each pixel region has a capacitance Cg between its gate electrode and source electrode.
s can be formed almost uniformly, and the occurrence of flicker can be suppressed.

Such an effect is not obtained only by the pattern of the drain electrode SD2 and the source electrode SD1 shown in FIG.
Needless to say, the same can be obtained by forming each pattern as shown in FIGS.

In this case, in the above-described embodiment, the source electrode SD1 is configured to have a symmetrical relationship with the drain electrode SD2 except for an extending portion for connecting to the pixel electrode ITO1.

However, as shown in FIG.
Needless to say, D1 may be formed so as to extend in the direction opposite to the pixel electrode ITO1 to be connected thereto and to extend beyond the gate signal line GL.

In this case, in order to prevent the source electrode SD1 from being connected to the pixel electrode ITO1 in the adjacent pixel region, the gate signal line GL is partially notched GLC.
To extend over the gate signal line GL.

In other words, the source electrode SD1 formed integrally with another portion which does not substantially function as an electrode is formed so as to cross the gate signal line GL.

The thus configured source electrode SD1
Is formed not only in the x direction in the drawing but also in the y direction, for example, even when it is formed, the area of the overlapping portion of the source electrode SD1 with respect to the gate signal line GL changes completely. Never.

From this, even if the position shift occurs in the rotation direction θ, the gate signal line G of the source electrode SD1 is formed.
The area of the superimposed portion with respect to L does not change at all.

Therefore, the thin film transistor TFT in each pixel region has a capacitance Cg between its gate electrode and source electrode.
s can be formed uniformly, and the occurrence of flicker can be greatly suppressed.

Further, in this embodiment, in particular, in each thin film transistor TFT arranged along the gate signal line GL, its gate electrode (gate signal line G)
The capacitance Cgs between L) and the source electrode SD1 is configured to be small on the input terminal side of the gate signal line and large on the terminal side.

That is, FIG. 9A shows the gate signal line GL.
9B shows a thin film transistor on the terminal side of the gate signal line GL.

As is clear from FIGS. 9A and 9B, the semiconductor layer AS on the side of the source electrode SD1 of the thin film transistor TFT shown in FIG. 9B is smaller than that shown in FIG. 9A. Due to the large size of the thin film transistor (the excess is indicated by the symbol I), the thin film transistor TF on the terminal side is formed.
The capacitance Cgs between the gate signal line GL of T and the source electrode SD1 increases.

That is, the area where the semiconductor layer AS near the source electrode of the thin film transistor on the terminal side overlaps with the gate signal line GL is smaller than the area where the semiconductor layer AS near the source electrode of the thin film transistor on the input terminal overlaps the gate signal line GL. It is getting bigger.

In this case, the capacitance Cgs of each thin film transistor TFT from the input terminal side of the gate signal line GL to the terminal side may be configured to increase sequentially, or
A plurality of thin film transistors adjacent to each other may be sequentially grouped, and each group may be sequentially increased in size.

With this configuration, the pixel electrode IT due to the waveform distortion of the scanning signal applied to the gate signal line GL
The shift of the potential of O1 in the positive direction is offset by the shift of the potential of the pixel electrode ITO1 in the negative direction depending on the jump voltage due to the capacitance Cgs, so that each of the input terminal side and the terminal side of the gate signal line GL is controlled. The voltage applied to the liquid crystal is made equal. For this reason, it is possible to suppress flickering of the screen due to a change in luminance.

Generally, the writing time of one line in the liquid crystal panel is completed within the time determined by the width of the TFT ON signal output from the scanning signal line driving circuit 104.

However, the TFT ON signal is a rectangular pulse whose width is uniquely determined by the horizontal scanning frequency. Generally, the rectangular pulse has a large current change (di / dt) at the rise and fall. For,
It is susceptible to the time constant in the signal path, and the actual rising and falling waveforms are curvilinear along the time constant curve (hereinafter, this curvilinear waveform is called "waveform distortion" and has a large curvature. Since the waveform becomes "large waveform distortion"), and the waveform distortion increases as approaching the end of the signal path, the above-described potential drop component ΔV of the pixel voltage PXV is at the end of the scanning signal line. As a result, the pixel voltage (source electrode potential) on the terminal side becomes higher than that on the input terminal side of the scanning signal line.

Such a problem is particularly remarkable when the number of pixels is increased or when the screen size (particularly, the size in the scanning line direction) is increased.

The distribution capacitances (Cgs, Cadd, C
gd) increases in proportion to the number of pixels and the screen size.

The above problem will be specifically described below. FIG.
Reference numeral 7 denotes an equivalent circuit for one line of the liquid crystal display panel. In this figure, GTM is an input terminal of the TFT ON signal (that is, a terminal connected to the output of the scanning signal line driving circuit 104 in FIG. 2), and this terminal GTM is connected between the scanning signal line driving circuit 104 and the liquid crystal display panel. Through the wiring 11 between
It is connected to the gate signal line GL of the liquid crystal display panel.
R11 and C11 represent a resistance component and a capacitance component of the wiring 11, respectively. The gate signal line GL is equivalent for each pixel, and R12 and C12 of each pixel are resistance and capacitance (also referred to as distributed capacitance, Cgs + Cadd + C) of each pixel.
gd).

Attention is now focused on two points a and c of the gate signal line GL, and the waveform distortion of the TFT ON signal at each point will be considered. a is a point closest to the terminal GTM. The TFT ON signal at this point a is set to VGa for convenience. c is the point farthest from the terminal GTM (in other words, the end of the scanning signal line). The TFT-on signal at this point c is referred to as V for convenience.
Gc.

FIG. 18A shows a driving waveform of the TFT on the terminal side, FIG. 18B shows a driving waveform of the TFT on the center, and FIG. 18C shows a driving waveform of the TFT on the terminal side. Each of the signals VGa and VGc is a rectangular pulse that changes from rising to falling in a predetermined writing period Tx allocated within one horizontal scanning period. Although the waveform distortion of the signal VGa is minute due to the time constant of R11 and C11, the waveform distortion of the signal VGc is based on the time constants of R11 and C11 and the number of pixels R12 and C12 of one line. This is a large one caused by the included time constant. For this reason, the fall tfr of the signal VGc is considerably slower than the fall tfl of the signal VGa. The degree of the delay increases as the number of pixels increases.
Also, it becomes more noticeable as the screen size increases. This is because the above-described distribution capacity (that is, C12) increases.

That is, the relationship tfr> tfl is established, and
The difference mainly depends on the size of the distribution capacitance described above.

Accordingly, from the relationship of the above-described equation 1, the drop component ΔVl of the pixel voltage on the terminal side becomes larger than the drop component ΔVr of the pixel voltage on the terminal side.

Conventionally, the parasitic capacitance (Cgs, Cd
It has been common sense to design s1, Cds2) and the storage capacitor (Cadd) to be constant at any location in the display area in order to equalize the driving conditions of the pixel electrodes. Therefore, in the conventional technique, the above-described optimum voltage Vc of the common electrode is obtained.
om actually differs between the terminal side and the terminal side of the gate signal line GL.

However, conventionally, the size of the display screen is smaller than 10 inches (length 15 cm, width 21 cm) and the gate signal line GL is not long (21 cm or less). Since the difference between the potential lowering components ΔV of the pixel electrodes is so small as to be negligible and the drive margin of the liquid crystal display device (especially, the margin of the optimal common electrode voltage Vcom) has room, the problem to be solved by the present invention is recognized. I couldn't do it.

Therefore, in the conventional technique, when the number of pixels in one line is large, or when the length of the display region in the gate signal line direction is long (at least in a liquid crystal display device having a gate signal line length of 27 cm or more), It is no longer possible to optimize the voltage applied to the common electrode for all pixels in the display area.

In order to solve the above problem, in the above-described embodiment, the source electrode SD1 of the thin film transistor TFT is used.
The capacitance Cgs is varied by varying the size of the semiconductor layer AS on the side.

In the above-described embodiment, since the size of the semiconductor layer AS is made different in a portion other than the channel forming region (the region between the source electrode SD1 and the drain electrode SD2) of the thin film transistor TFT, the gate-source capacitance is reduced. C
gs on the input terminal side and the terminal side,
(Specifically, channel length l and channel width w)
Does not change, and the design of the liquid crystal display device is easy.

As is apparent from Equation 1, the method of adjusting the potential lowering component ΔV of the pixel electrode so that the difference between the pixels is reduced, as in the above-described embodiment, is to reduce the gate-source capacitance Cgs. Not only in the method of adjusting, but also in the holding capacitor C
a method of adjusting the add, a method of adjusting the liquid crystal capacitance Cpix (specifically, an area of the pixel electrode ITO1 or a distance between the pixel electrode ITO1 and the common electrode COM (not shown)),
A method of adjusting the source-drain capacitance Cds1 or the pixel electrode ITO1 and the drain signal line D adjacent thereto.
A method of adjusting the parasitic capacitance Cds2 between L may be used.

However, in the above-described embodiment in which the gate-source capacitance Cgs is adjusted, as is clear from the fact that the numerator of the formula 1 is composed of only the gate-source capacitance Cgs, a smaller gate-source capacitance is obtained. The change amount of the capacitance Cgs,
The potential drop component ΔV of the pixel electrode can be adjusted in a wide dynamic range. Therefore, in the above embodiment, the space for changing the gate-source capacitance Cgs is small, and the aperture ratio of the pixel can be increased.

The gate-source capacitance Cgs, the storage capacitance element Cadd, the liquid crystal capacitance Cpix, the source-drain capacitance Cds1, and the pixel electrode drain signal line capacitance Cd
By adjusting s2 in combination, it is possible to adjust the potential decrease component ΔV of the pixel electrode in a wider dynamic range.

The storage capacitor Cadd and the liquid crystal capacitor C
pix, the source-drain capacitance Cds1 or the pixel electrode drain signal line capacitance Cds2, when adjusting the potential drop component ΔV of the pixel electrode, the capacitance is expressed by the following equation (1).
It is clear from the above that the capacitance of the terminal pixel (c) on the terminal side where the distortion of the scanning signal driving waveform is large is reduced, and the distortion of the scanning signal driving waveform is small on the input terminal side. What is necessary is just to increase those capacitances in the pixel (a).

The method of adjusting the gate-source capacitance Cgs is not limited to the method of adjusting the overlapping area of the semiconductor layer AS with the gate signal line GL. As shown in FIG. A projection GLP as shown in the drawing is formed to extend on the gate signal line GL in the overlap region of the electrode SD1.
The same effect can be obtained even if the area of P is formed smaller on the input terminal side of the gate signal line GL and larger on the terminal side.

Further, as shown in FIG. 11, the overlap region of the source electrode SD1 with respect to the gate signal line GL may be made different by changing the length of the gate signal line GL in the width direction. Nor.

That is, each pixel region arranged along the gate signal line GL is grouped into a plurality of pixel regions adjacent to each other, and the gate signal line GL of each grouped pixel region is connected to its input terminal side. From the end to the terminal side (the width of the source electrode SD1 on the side connected to the pixel electrode ITO1 is increased).

Also, as shown in FIGS. 12, 13 and 14,
In the case of a liquid crystal display device that employs a storage capacitor method for the storage capacitor Cadd, the width of the overlapping area of the pixel electrode ITO1 and the capacitor line CL may be sequentially increased from the input terminal side to the terminal side. Pixel electrode potential drop component Δ
V can be adjusted. In the embodiment shown in FIGS. 13 and 14, by adjusting the width W3 of the capacitance line CL,
The potential drop component ΔV is adjusted.

The storage capacitance type liquid crystal display device has a feature that the influence of waveform distortion of the scanning signal VG can be reduced because the distribution capacitance of the gate signal line GL is small. However, even in the storage capacitance type liquid crystal display device, the difference between the potential drop component ΔV between the input terminal side and the terminal side is reduced by adjusting the gate-source capacitance Cgs and the storage capacitance Cadd as in the above-described embodiment. Since the influence of the waveform distortion of the scanning signal VG can be completely eliminated, a liquid crystal display device having the largest display screen can be realized.

The distortion of the signal waveform input to the gate signal line GL monotonically increases from the input end to the end.

FIG. 17B shows a central portion of the gate signal line (scanning signal line) GL, and FIG. 18B shows a TFT drive waveform of that portion. FIG. 18A shows a TFT drive waveform on the input terminal side shown in FIG. 17A, and FIG. 18C shows a TFT drive waveform on the terminal side shown in FIG. 17C. FIG.
18A, 18B and 18C, the falling time tf of the scanning signal VGb at the center is the falling time tfl on the input terminal side and the falling time tfl on the terminal side. between tfr. That is, tfl <tf <tf
r. Therefore, in the conventional liquid crystal display device designed so that the parasitic capacitance is equal in all the pixels, the potential drop component ΔV of the pixel electrode at the center is the potential drop component ΔVl on the input terminal side and the potential drop component ΔV1 on the output terminal side. It is between the decreasing components ΔVr. That is, there is a relationship of ΔVl>ΔV> ΔVr.

Therefore, the amount of shift in the positive direction of the voltage of the pixel electrode ITO corresponding to the central portion of the gate signal line GL depends on the pixel electrode IT corresponding to the input end of the gate signal line GL.
O and less than the pixel electrode ITO corresponding to the end of the gate signal line GL.

Therefore, the capacitance Cgs between the gate electrode and the source electrode SD1 of the thin film transistor TFT connected to the central portion of the gate signal line GL is changed to the capacitance Cgs of the thin film transistor TFT connected to the input terminal of the gate signal line GL.
By making it larger and smaller than the capacitance Cgs of the thin film transistor TFT connected to the terminal of the gate signal line GL, the leakage component of the gate signal jumping into the pixel electrode ITO at the input terminal and the terminal and the pixel electrode ITO at the center is made uniform. The optimum common electrode voltage does not differ between the input terminal and the terminal pixel and the central pixel, and flicker does not occur at the central portion of the display area.

Here, the input terminal and the terminal pixel electrode ITO1 of the gate signal line are connected to the pixel electrode IT contributing to display.
The pixel electrode IT, which is discussed in O1, is shielded by the light-shielding film.
It goes without saying that it is appropriate to exclude pixel electrodes ITO1 that do not contribute to display, such as O1 and pixel electrodes of unfinished pixels, because they are irrelevant to flicker.

However, the pixel electrode ITO1 which is shielded from light by the pixel electrode ITO1 at the input end and the terminal end of the gate signal line.
The pixel corresponding to 1 also has a thin film transistor T on the input end side.
The thin film transistor TF on the terminal side with respect to the capacitance Cgs of the FT
By employing a configuration in which the capacitance Cgs of T is increased, a DC component is not added to the liquid crystal, and an effect of improving the life of the liquid crystal can be obtained.

In this embodiment, the liquid crystal is provided with measures against flicker due to waveform distortion of the scanning signal input to the gate signal line GL and measures against flicker due to displacement of the source electrode SD1 due to distortion of the optical system of the exposure apparatus. Although the display device has been described, it goes without saying that the display device may be configured to take one of these preventive measures.

However, in the liquid crystal display device in which flicker prevention due to the displacement of the source electrode SD1 has been performed, the flicker prevention due to the waveform distortion of the scanning signal input to the gate signal line GL is performed, thereby reducing the potential of the pixel electrode. The component ΔV can be adjusted with high accuracy, and even when the display area is enlarged to the maximum, a drive margin of the liquid crystal display panel (particularly, a margin of the common electrode voltage Vcom) can be sufficiently secured.

<< Method of Manufacturing Transparent Substrate SUB1 >>
A method for manufacturing the first transparent insulating substrate (thin film transistor substrate) SUB1 side of the liquid crystal display device shown in FIG.
This will be described with reference to FIGS. In the figure,
The characters in the center are the abbreviations of the process names, the thin film transistor TFT (IV-IV cutting line) on the left, and the storage capacitor Cadd (VI
-VI cutting line) shows the flow of processing viewed from the cross-sectional shape. Except for the steps B and D, the steps A to G are photographs (photos)
Each of the sectional views in each step shows the stage after the processing after the photo-processing is completed and the photoresist is removed. In the present description, the photo (photo) processing refers to a series of operations from application of a photoresist, through selective exposure using a mask, to development thereof, and a repeated description thereof will be omitted. A description will be given below according to the divided steps.

Step A, FIG. 19 After a silicon oxide film SIO is provided on both surfaces of a first transparent insulating substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. Note that this SIO film is formed to alleviate the surface irregularities of the transparent insulating film SUB1, but can be omitted if the irregularities are small. Al-Ta having a thickness of 2800 °,
First conductive film g made of Al-Ti-Ta, Al-Pd or the like
1 is provided by sputtering. After the photo-treatment, the first conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step B, FIG. 19 After the resist is directly drawn (after the above-described anodic oxidation pattern is formed),
3% tartaric acid with ammonia PH 6.25 ± 0.05
The substrate SUB1 is immersed in an anodizing solution composed of a solution obtained by diluting the solution adjusted to 1: 9 with an ethylene glycol solution,
The formation current density is adjusted to 0.5 mA / cm ² (constant current formation). Next, anodic oxidation (anodization) is performed until the formation voltage 125 V necessary for obtaining a predetermined Al2O3 film thickness is reached. Thereafter, it is desirable to maintain this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al2O3 film. As a result, the conductive film g1 is anodized, and the film thickness is 1800 on the scanning signal lines (gate lines) GL and on the side surfaces in a self-aligned manner.
The anodic oxide film AOF of Å is formed and the thin film transistor T
It becomes a part of the gate insulating film of the FT.

Step C, FIG. 19 A conductive film ITO made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photoprocessing, the conductive film ITO is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming one electrode of the storage capacitor Cadd and the transparent pixel electrode ITO1.

Step D, FIG. 20 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a 2000-nm thick Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form a film. After providing a 2000 ° i-type amorphous Si film, hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus to form a 300 ° -thick N + type amorphous Si film d0. This film formation is performed continuously by changing the reaction chamber in the same CVD apparatus.

Step E, FIG. 20 After photo processing, SF6, BC
1 using N + type amorphous Si film d0, i type amorphous Si
The film AS is etched. Subsequently, the Si nitride film GI is etched using SF6. Of course, the N + type amorphous Si film d0, the i type amorphous Si film AS, and the Si nitride film GI may be successively etched with SF6 gas.

By thus continuously etching the three-layer CVD film with a gas containing SF6 as a main component, i.
Side walls of the type amorphous Si film AS and the Si nitride film GI can be processed into a tapered shape. Due to the tapered shape, the probability of disconnection is significantly reduced even when the source electrode SD1 is formed on the upper portion. N + type amorphous Si film d0
Is close to 90 degrees, but since the thickness is as thin as 300 °, the probability of disconnection at this step is very small. Therefore, the N + type amorphous Si film d0 and the i type amorphous Si film A
The plane pattern of the S and Si nitride films GI is not strictly the same pattern, and the cross section has a forward tapered shape. Therefore, the N + type amorphous Si film d0, the i type amorphous Si film AS, and the The pattern becomes larger in order.

Step F, FIG. 21 A first conductive film d1 made of Cr and having a thickness of 600 ° is provided by sputtering. After the photo-treatment, the first conductive film d1 is etched with a ceric ammonium nitrate solution to form a drain signal line DL, a source electrode SD1, and a drain electrode S.
Form D2.

Here, in this embodiment, as shown in step E, the N + type amorphous Si film d0, the i type amorphous Si film AS,
Since the Si nitride film GI has a forward taper, even if the source electrode SD1 is formed only of the first conductive film d1, the source electrode SD1 does not break.

Next, SF6,
By introducing the BC1, the N + type amorphous Si film d0 is etched to selectively remove the N + type semiconductor film d0 between the source and the drain.

Step G, FIG. 21 Ammonia gas, silane gas and nitrogen gas are introduced into the plasma CVD apparatus to form a 0.6 μm-thick Si nitride film. After photo processing, SF6 is used as a dry etching gas.
The protective film PSV1 is etched by using
To form As the protective film, not only a SiN film formed by CVD but also a film using an organic material can be used.

<< Design of Photomask >> First substrate SUB1
Are formed by photolithography. FIG. 22A shows an example of a pattern forming method.

MSK1 is a pattern P for transferring to a substrate.
It is a photomask on which an AT is formed. The number of the MSK1 is one, and the entire pattern of the liquid crystal display panel is formed.

SUB1 is a substrate having a main surface coated with a photoresist. In the example of FIG. 22A, one substrate SU
B1 shows an example in which a pattern of one liquid crystal display panel is formed. However, a pattern of a plurality of liquid crystal display panels may be formed on one mother glass substrate.

The alignment mark ALM is provided on the photomask.
Is provided, and the alignment mark ALM 'provided on the substrate is provided.
The alignment between the layers of the first substrate SUB1 is performed by aligning the alignment mark ALM with the photomask.

Light such as ultraviolet rays generated by a light source LIT such as a mercury lamp is processed into a uniform surface light source by a lens optical system LEN and sent to a reflecting mirror MIR.

The light sent to the reflecting mirror MIR is transmitted through the slit S
The light reflected toward the LT and passing through the slit SLT becomes linear light and illuminates the photomask MSK1.

The linear light transmitted through the photomask MSK1 impinges on the substrate SUB1 to expose the photoresist.

At this time, the pattern PAT of the photomask MSK1 is transferred onto the substrate SUB1 only in the portion e where light is irradiated.

In the direction shown by the arrow in FIG. 22 (a), the slit SLT and the reflecting mirror MIR are formed with respect to the substrate and the photomask.
Are relatively moved to form the photomask MSK1.
Is transferred as the pattern PAT ′ of the substrate SUB1.

FIG. 22B is used in the method shown in FIG. 9 shows an example of a pattern PAT of a photomask MSK1.

Referring to the embodiment shown in FIG. 9, FIG.
The photomask MSK1 shown in FIG. 2B has a pattern of the semiconductor layer AS formed thereon.

Assuming that the direction in which the gate signal line GL extends is x, a in FIG. 22B indicates a pattern of the semiconductor layer AS on the input terminal side, and b indicates a pattern of the semiconductor layer AS on the terminal side. The portion I of FIG. 22B is the gate / gate described above.
This is a pattern for adjusting the inter-source capacitance Cgs.

The entire pattern of one layer of the liquid crystal display panel is formed on one photomask MSK1 shown in FIGS. 22A and 22B, and a desired layer (eg, semiconductor layer AS) of the substrate SUB1 is patterned. According to the forming method, the pattern on the input terminal side and the pattern on the terminal side can be formed under the same exposure condition, so that the pattern I for adjusting the potential drop component ΔV of the pixel electrode can be formed with high accuracy. Can be done.

Therefore, since the potential drop component ΔV can be controlled with high precision, the margin for driving the liquid crystal display panel (particularly, the margin of the common electrode voltage Vcom) is improved.

Note that, as shown in FIG.
The formation of the pattern PAT 'on the UB1 is performed by using a reflecting mirror MIR.
And the slit SLT are moved to perform exposure, so that the pattern PAT ′ on the substrate may be distorted due to the accuracy of the mechanical part.

However, the length of the width W0 orthogonal to the extending direction of the source electrode SD1 shown in FIGS. 1, 7A to 7D and 8 is formed smaller than the channel width W. With this configuration, the capacitance Cgs between the gate and the source due to misalignment between the source electrode SD1 and the gate signal line GL.
, The influence of distortion in the exposure process can be reduced.

FIG. 23A shows another example of a method for forming a pattern on the first substrate SUB1.

The difference from FIG. 22A is that the substrate SUB1
The above pattern PAT 'is replaced with a plurality of block patterns PAT.
i, PATii, PATiii, PATiv, and one photomask MSKi, MSKii, MSKii for each block.
i and MSKiv.

FIG. 23B shows a plurality of photomasks MSKi, MSKii, MSKi used in the method shown in FIG.
ii, shows an example of a pattern of MSKiv.

Referring to the embodiment shown in FIG. 9, FIG.
FIG. 3B shows an example of a photomask of the semiconductor layer AS. Assuming that the direction in which the gate signal line GL extends is x, the photomasks MSKi and MSKiv indicate the input terminal side, and the photomasks MSKii and MSKiii indicate the end-side photomasks. 23A shows a pattern of the semiconductor layer AS on the input terminal side, and b shows a pattern of the semiconductor layer AS on the terminal side. The portion I in FIG. 23B is a pattern for adjusting the gate-source capacitance Cgs described above.

Other points that are not particularly described are the same as those of the embodiment shown in FIGS. 22A and 22B described above.

According to the embodiment shown in FIG. 23A, the pattern PAT 'of one layer of one liquid crystal display device is formed by a plurality of photomasks MSKi, MSKii, MSKiii, MSKiv.
Thus, a liquid crystal display device having a large display screen can be manufactured.

However, in the embodiment shown in FIG. 23 (a), it is necessary to form the pattern I for adjusting the potential drop component ΔV on the input terminal side and the termination side using different photomasks. It is difficult to adjust ΔV.

In the embodiment shown in FIG. 23A, each block pattern PATi ′, PATi of the substrate SUB1 is used.
In the boundary region between i ′, PATiii ′, and PATiv ′,
Since the pattern is exposed a plurality of times, the pattern becomes thinner than other portions.

Therefore, it is necessary to provide a pattern I for adjusting the potential drop component ΔV in a portion other than a portion exposed a plurality of times.

On the other hand, in the embodiment shown in FIG. 22A, since all the patterns PAT 'of one layer of the liquid crystal display device are formed by one photomask MSK1, there is no boundary region and the potential drop component ΔV is reduced. There are few restrictions for providing the pattern I to be adjusted.

However, in the case of manufacturing a liquid crystal display device having the largest display area, the embodiment shown in FIG. 23A is better unless the accuracy of the pattern I for adjusting the potential drop component ΔV is considered. Are suitable.

The method of forming the patterns shown in FIGS. 22A and 22B or FIGS. 23A and 23B is a method of adjusting the potential drop component ΔV in the semiconductor layer AS. Although the example in which I is provided is shown, a pattern I for adjusting the potential lowering component ΔV may be provided in other layers.

For example, in the embodiment shown in FIGS. 10 and 11, the photomask in the step (first photo) for forming the gate signal line GL is provided with the photomask shown in FIG. 22 (a), FIG. 22 (b) or FIG. ) And the pattern forming method shown in FIG. In addition, a photomask used in the step of forming the source electrode SD1 (fourth photo) is shown in FIG.
(A), FIG. 22 (b) or FIG. 23 (a), FIG.
The pattern forming method shown in FIG.

<< Case of Driving Gate Signal Line GL at Both Ends >> FIG. 24 shows scanning signal line driving circuit sections 104 at the left and right ends of the gate signal line GL in order to reduce the waveform distortion of the scanning signal line driving waveform VG. 7 is an equivalent circuit of a liquid crystal display device in an example provided. In the liquid crystal display device having the configuration shown in FIG. 24, the terminal of the gate signal line GL does not exist.

However, even in the liquid crystal display device having the configuration shown in FIG. 24, the waveform distortion of the scanning signal VG of the pixel B at the central portion far from the two scanning signal line driving circuit units 104 causes the two scanning signal line driving circuit units 104 to have the same waveform distortion. Scan signal V of pixels A and C on the near side
It is larger than the waveform distortion of G.

Therefore, also in the liquid crystal display device driven on both sides shown in FIG. 24, the capacitance Cgs between the gate and the source of the pixel B farther from the input terminal is changed to the capacitance Cgs between the gate and the source of the pixels A and C closer to the input terminal. By increasing the value, the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal VG can be reduced.

The specific method of adjusting the gate-source capacitance Cgs is as in the embodiment shown in FIGS. 9, 10 and 11.

In the liquid crystal display device driven on both sides shown in FIG. 24, the method of reducing the difference in the potential reduction component ΔV of the pixel electrode is not limited to the method of adjusting the gate-source capacitance Cgs, but also the method of controlling the storage capacitor Cadd, The liquid crystal capacitance Cpix, the capacitance Cds1 between the source and the drain, or the capacitance Cds2 between the pixel electrode and the drain signal line may be adjusted.

In this embodiment, a reversely staggered thin film transistor T is formed in the order of gate electrode formation, gate insulating film formation, semiconductor layer formation, and source / drain electrode formation.
FT was indicated.

However, the present invention is not limited to a liquid crystal display device using an inverted staggered thin film transistor TFT, but uses a forward staggered thin film transistor TFT having a gate electrode formed on a semiconductor layer via a gate insulating film. The present invention may be applied to a liquid crystal display device.

Embodiment 2 The present invention describes a so-called vertical electric field type liquid crystal display device as an example. However, in the case of the in-plane switching method (In Plain Switching method), a pair of electrodes facing each other is provided on the liquid crystal side of one transparent substrate, and an electric field is generated between these electrodes in parallel with the transparent substrate. Since the situation is exactly the same, the present invention can be applied to this in-plane switching mode liquid crystal display device.

FIG. 25 is a plan view showing one pixel of an active matrix type color liquid crystal display device of a horizontal electric field type to which the present invention is applied and the periphery thereof.

FIG. 26 is a view showing a section taken along section line 3-3 in FIG. As shown in FIGS. 25 and 26, a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode COM2 are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC, and on the upper transparent glass substrate SUB2 side. Is formed with a color filter FIL and a light-shielding black matrix pattern BM.

Further, the transparent glass substrates SUB1, SUB2
Are provided with alignment films ORI1 and ORI2 for controlling the initial alignment of the liquid crystal on the inner surface of each (liquid crystal LC side), and the polarizing axes are provided on the outer surfaces of the transparent glass substrates SUB1 and SUB2. A polarizing plate arranged orthogonally (crossed Nicols arrangement) is provided.

As shown in FIG. 25, each pixel has a gate signal line (scanning signal line or horizontal signal line) GL, a counter voltage signal line (common electrode line) COM1, and two adjacent drain signal lines (video The signal line or the vertical signal line) is arranged in an intersecting region with the DL (in a region surrounded by four signal lines). Each pixel is a thin film transistor TFT, a storage capacitor C
stg, the pixel electrode PX, and the counter electrode COM2.
The gate signal line GL and the counter voltage signal line COM1 extend in the left-right direction in FIG. The drain signal lines DL extend in the up-down direction, and a plurality of drain signal lines DL are arranged in the left-right direction. The pixel electrode PX is a thin film transistor T
FT, and the common electrode COM2 is connected to the common voltage signal line C.
It is integrated with OM1.

The two pixels vertically adjacent to each other along the drain signal line DL have such a configuration that when they are bent along the line A in FIG. 25, their plane configurations overlap. This is because the common voltage signal line COM1 is shared by two vertically adjacent pixels along the drain signal line DL, and the electrode width of the common voltage signal line COM1 is increased, thereby reducing the resistance of the common voltage signal line COM1. That's why. This makes it easy to sufficiently supply a counter voltage from the external circuit to the counter electrode COM2 of each pixel in the left-right direction.

The pixel electrode PX and the counter electrode COM2 are opposed to each other, and the electric state between each pixel electrode PX and the counter electrode COM2 controls the optical state of the liquid crystal LC to control the display. The pixel electrode PX and the counter electrode COM2 are formed in a comb shape, and each is an electrode that is elongated in the vertical direction in the figure.

The electrode width of the gate signal line GL is set so as to satisfy a resistance value enough to apply a scanning voltage to the gate electrode GT of the pixel on the terminal side. The electrode width of the common voltage signal line COM1 is also set so as to satisfy a resistance value enough to apply a common voltage to the common electrode COM2 of the terminal pixel.

In FIG. 25, the portion indicated by the symbol I is a portion for adjusting the potential drop component ΔV of the pixel electrode. The portion indicated by the symbol I is formed integrally with the pixel electrode Px,
A gate-source capacitance Cgs is formed by overlapping the gate signal line GL via the insulating film GI.

Therefore, in the embodiment shown in FIG.
The area of the overlapping portion between the inter-source capacitance adjustment pattern I and the gate signal line GL is reduced in the pixel closer to the input terminal,
The difference between the pixels of the potential drop component ΔV of the pixel electrode is reduced by increasing the value of the pixel farther from the input terminal.

The horizontal electric field type liquid crystal display device is characterized by a wide viewing angle characteristic. Therefore, by adopting the horizontal electric field method in a liquid crystal display device having a large display area, the conventional problem that a part of the screen becomes invisible due to narrow viewing angle characteristics can be solved.

Therefore, by applying the present invention to a horizontal electric field type liquid crystal display device, the influence of the drive waveform distortion due to the longer gate signal line GL can be reduced.
A liquid crystal display device having the largest display area can be realized.

In the liquid crystal display device of the in-plane switching mode, the method of adjusting the potential drop component ΔV of the pixel electrode is not limited to the method of adjusting the gate-source capacitance Cgs, but the method of adjusting the storage capacitor Cgs.
add, liquid crystal capacitance Cpix, source-drain capacitance C
ds1 or pixel electrode drain signal line capacitance Cds2
May be adjusted.

Embodiment 3 Next, another embodiment for adjusting the gate-source capacitance Cgs is shown in FIGS. 27 (a) and 27 (b).

FIGS. 27A and 27B are views showing a portion near the thin film transistor TFT in the plan view of the pixel shown in FIG. The configuration of the parts not described in FIGS. 27A and 27B is the same as the configuration of the pixel shown in FIG.

FIG. 27A shows the structure of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 27B shows the structure of the thin film transistor TFT on the far side from the input terminal.

In this embodiment, the direction of the channel length 1 of the thin film transistor TFT is arranged perpendicular to the direction in which the gate signal line GL extends.

In this embodiment, the gate-source capacitance Cgs is adjusted by two portions, the adjustment pattern I1 provided on the semiconductor layer AS and the adjustment pattern I2 provided on the source electrode SD1, and the potential drop component of the pixel electrode is adjusted. The difference ΔV between pixels is reduced. Therefore, in this embodiment, the adjustment pattern I1 and the adjustment pattern I2 can be provided in a narrow area, so that the aperture ratio of the pixel can be improved.

As shown in FIGS. 27A and 27B, in this embodiment, the adjustment pattern I2 provided on the source electrode SD1 is changed by adjusting the channel length l of the thin film transistor TFT.
Further, since it is provided apart from the portion that defines the channel width W, the driving capability of the thin film transistor TFT does not change by providing the adjustment pattern I2 on the source electrode SD1.

Embodiment 4 FIGS. 28A and 28B show another embodiment for adjusting the gate-source capacitance Cgs.

FIGS. 28A and 28B are also diagrams showing a portion near the thin film transistor TFT in the plan view of the pixel shown in FIG. The configuration of the portion not described in FIGS. 28A and 28B is the same as the configuration of the pixel illustrated in FIG.

FIG. 28A shows the structure of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 28B shows the structure of the thin film transistor TFT on the far side from the input terminal.

In this embodiment, the gate electrode GT of the thin film transistor TFT is provided to be branched from the gate signal line GL.

In this embodiment, a portion of the gate electrode GT of the thin film transistor TFT overlapping with the source electrode SD1 is
A notch pattern I3 is provided to provide a gate-source capacitance C
gs is adjusted to reduce the difference between the pixels of the potential decrease component ΔV of the pixel electrode. Therefore, in this embodiment, unlike the case where the projection is provided on the gate electrode GT made of the light-shielding metal film, the aperture ratio is not sacrificed.

In order to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal by the cutout pattern I3 provided in the gate electrode GT shown in FIGS. 28 (a) and 28 (b), The closer the pixel is to the input terminal, the larger the cutout amount of the cutout pattern I3 should be.

In the present embodiment shown in FIGS. 28A and 28B, the adjustment pattern I provided on the gate electrode GT is also used.
3 is provided away from the portion that defines the channel length l and the channel width W of the thin film transistor TFT, so that the driving capability of the thin film transistor TFT does not change by providing the adjustment pattern I3 on the gate electrode GT.

Embodiment 5 Next, a description will be given of an embodiment in which a countermeasure for reducing the difference of the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal is applied to the liquid crystal display device having a high aperture ratio of the pixel.

<< Configuration of Pixel Region >> FIG. 29A is a plan view showing a specific configuration of a pixel region corresponding to the dotted frame A in FIG. 2 in this embodiment.

A sectional view taken along line IV-IV in FIG. 29A is shown in FIG. 30, a sectional view taken along line VV in FIG.
FIG. 32 shows a cross-sectional view taken along line -VI.

As shown in FIG. 30, in the liquid crystal display panel, a thin film transistor TFT and a pixel electrode ITO1 are formed on the first transparent substrate SUB1 side on the basis of the liquid crystal LC, and a color filter FIL is formed on the second transparent substrate SUB2 side. , A black matrix pattern (first light shielding film) BM1 is formed.

In FIG. 30, POL1 is a first polarizing plate provided on a first transparent substrate SUB1, and POL2 is a second polarizing plate provided on a second transparent substrate SUB2.

First, a first transparent substrate S made of glass or the like is used.
A gate signal line GL extending in the x direction and juxtaposed in the y direction is formed on the liquid crystal side surface of UB1.

The gate signal line GL is formed of a conductive layer gl made of chromium, molybdenum, an alloy of chromium and molybdenum, aluminum, tantalum, titanium or the like. Further, in order to reduce the wiring resistance of the gate signal line GL, the gate signal line GL is formed using the above-described laminated film of the conductive film.
May be configured. When aluminum is used for the gate signal line GL, an alloy to which a small amount of metal such as tantalum, titanium, or niobium is added may be used to eliminate projections such as hillocks and whiskers.

A pixel electrode ITO1 made of a transparent conductive film (for example, Indium-Tin-Oxide) is formed in most of the pixel region surrounded by the gate signal line GL and a drain signal line DL described later. .

The gate signal line GL on the lower left side of the drawing in the pixel region
The upper part is a formation region of the thin film transistor TFT. The thin film transistor TFT includes, for example, a gate insulating film GI made of SiN, a semiconductor layer AS made of i-type amorphous Si, and a semiconductor layer d made of amorphous Si containing impurities.
0, a drain electrode SD2 and a source electrode SD1 are sequentially laminated.

Then, the drain electrode SD2 and the source electrode SD1 are formed simultaneously with the drain signal line DL.

As shown in FIG. 31, the drain signal line DL is formed on the insulating film GI, the semiconductor layer AS, and the semiconductor layer d0 made of amorphous Si containing impurities, and is made of chromium, molybdenum, or an alloy of chromium and molybdenum. , A single layer or a laminate of a conductive film such as aluminum, tantalum or titanium. The reason why the semiconductor layer AS and the semiconductor layer d0 containing the impurity are formed in the formation region of the drain signal line DL is that, for example, the disconnection of the drain signal line DL due to the step difference between the semiconductor layer AS and the semiconductor layer d0 containing the impurity is prevented. To do that.

The drain electrode S of the thin film transistor TFT
D2 is formed integrally with the drain signal line DL, and the source electrode SD1 is formed to be separated from the drain electrode SD2 by a predetermined channel length l.

The source electrode SD1 and the drain electrode SD2
Is provided with a protective film PSV1 made of an insulating film. The protective film PSV1 is a liquid crystal thin film transistor TFT
The characteristic deterioration caused by the direct contact with the substrate is avoided. The protective film PSV1 is made of a film having good moisture resistance such as a silicon nitride film or an organic resin film such as polyimide.
The pixel electrode ITO1 is formed on the protective film PSV1.

The protective film PSV1 on the source electrode SD1 is provided with a through hole CONT for electrically connecting the source electrode SD1 and the pixel electrode ITO1.

As shown in FIG. 32, the storage capacitance element Cadd has a gate signal line (another gate signal line adjacent to the gate signal line for driving the thin film transistor TFT) G
L is one electrode, the conductive layer formed simultaneously with the pixel electrode ITO1 is the other electrode, and the insulating film GI and the protective film PSV1 interposed therebetween are formed as a dielectric film.

The insulating film GI and the protective film PSV1 are formed simultaneously with their formation in the thin film transistor TFT, and the conductive layer, which is the other electrode, is formed simultaneously with the pixel electrode ITO1.

Further, an alignment film ORI1 for regulating the alignment of the liquid crystal is formed on the entire surface of the pixel electrode ITO1.

In this embodiment, since the protective film PSV1, which is an insulating film, exists between the pixel electrode ITO1 and the gate signal line GL and the drain signal line DL, the pixel electrode ITO1 and the gate signal line GL or the pixel electrode ITO1 are not connected. Even if the drain signal lines DL overlap in plan, no short circuit occurs. Therefore, in the present embodiment, the pixel electrode ITO1 can be formed large, so that the pixel electrode ITO1 has a feature that the aperture of the pixel becomes large, and the liquid crystal capacitance Cpix increases, so that the storage capacitance Cadd can be reduced.

The second transparent substrate SUB2 made of glass or the like
The first light-shielding film BM1,
The color filter FIL, the common transparent electrode COM, and the upper alignment film ORI2 are sequentially laminated.

The first light-shielding film BM1 is made of a light-shielding metal film such as chromium or aluminum, or a light-shielding organic film obtained by adding a dye, pigment, carbon, or the like to a resin film such as acryl. The common transparent electrode COM is ITO (Indium-Tin-Oxid
e) and the like.

The color filter FIL is formed by adding a dye or a pigment to a base made of an organic resin film such as acrylic.

In order to prevent the dye or pigment of the color filter FIL from contaminating the liquid crystal LC, a color filter protective film made of an organic resin film such as acryl is provided between the color filter FIL and the common transparent electrode COM. You may.

<< Second Light-Shielding Film BM2 >> In the present embodiment, FIG.
9A, as shown in FIG. 31, a second light-shielding film BM2 made of a light-shielding metal film is provided on the first transparent substrate SUB1 on which the drain signal lines DL are formed. Second
The light shielding film BM2 is a conductive film g1 forming the gate signal line GL.
And is formed in the same layer as the gate signal line GL.

The second light-shielding film BM2 has a planar structure of FIG.
As shown in FIG. 9A, the pixel electrode ITO1 is formed so as to overlap with the pixel electrode ITO1 along the drain signal line DL and not to overlap with the drain signal line DL. On the other hand, as for the sectional structure, as shown in FIG.
Are insulated and separated by a drain signal line DL and a gate insulating film GI. Therefore, the possibility that the second light-shielding film BM2 and the drain signal line DL are short-circuited is small. Further, the pixel electrode ITO1 and the second light shielding film BM2 are insulated and separated by the gate insulating film GI and the protective film PSV1.

The second light-shielding film BM2 has a function of improving the area of the transmission part of the pixel electrode for one pixel, that is, the aperture ratio, and improving the brightness of the display panel. In the display panel shown in FIG. 28, the backlight BL is set on one side of the first transparent substrate SUB1. The backlight BL may be provided on the second transparent substrate SUB2 side. However, in the following, for convenience, the backlight is irradiated from the first transparent substrate SUB1 side and observed from the second transparent substrate SUB2 side. Show. Irradiation light is applied to the first transparent substrate S
The light passes through UB1 and enters the liquid crystal LC from a portion of the first transparent substrate SUB1 where no light-shielding film (gate signal line GL, drain signal line DL, and second light-shielding film BM2) is formed. This light is controlled by a voltage applied between the common electrode COM formed on the second transparent substrate SUB2 and the pixel electrode ITO1 formed on the first transparent substrate SUB1.

In the normally white mode, in which the light transmittance of the display panel decreases when a voltage is applied to the pixel electrode ITO1, if the second light shielding film BM2 is not formed as in the present embodiment, the second It is necessary to widely cover the periphery of the pixel electrode ITO1 with the first light-shielding film BM1 provided on the transparent substrate SUB2. Otherwise, light that cannot be controlled by a voltage from the gap between the drain signal line DL or the gate signal line GL and the pixel electrode ITO1. Leaks, and the display contrast is reduced. Further, the second transparent substrate SUB2 and the first transparent substrate SUB1
Are bonded together with a liquid crystal interposed therebetween, and a large alignment margin is required. The aperture ratio is smaller than that in the present embodiment in which the second light-shielding film BM2 is provided on the first transparent substrate SUB1.

In this embodiment, the second light shielding film SUB2
Used the same light-shielding metal film g1 as the gate signal line GL, but any material capable of blocking light may be used. The light-shielding film was formed by adding a dye, pigment, carbon, or the like to a resin film such as acryl. Alternatively, an insulating light-shielding film may be used.

<< Method for Equalizing Potential Drop Component ΔV of Pixel Electrode >> FIG. 29A shows a planar structure of a pixel on the input terminal side.
FIG. 29B shows a part of a planar structure of a pixel farther from the input terminal (for example, the terminal side).

Also in this embodiment, the direction of the channel length 1 of the thin film transistor TFT is arranged perpendicular to the direction in which the gate signal line GL extends.

In the present embodiment, a portion 1 overlapping the gate signal line GL for selecting the pixel electrode ITO1 is provided in the pixel electrode ITO1, the gate-source capacitance Cgs is adjusted, and the pixel electrode potential drop component ΔV of the pixel electrode ITO1 is adjusted. The difference between them has been reduced.

In order to reduce the difference of the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal with the adjustment pattern I4 provided on the pixel electrode ITO1 shown in FIG.
The area where the adjustment pattern I4 and the gate signal line GL overlap each other should be larger by a predetermined amount d than the pixel closer to the input terminal as the pixel is farther from the input terminal.

In this embodiment, the gate-source capacitance Cg
In order to adjust s for each pixel, the pixel electrode ITO1 is provided so as to extend to a portion overlapping with the gate signal line GL for selecting the pixel electrode ITO1, so that the gate signal line GL made of a light-shielding metal is First light shielding film BM covering the edge of the electrode
Performs the same function as 1. Therefore, the first light-shielding film BM1 covering the overlapping portion 1 of the pixel electrode ITO1 and the gate signal line GL
Can be retracted in the direction of the gate signal line GL indicated by the arrow, and the aperture of the pixel can be enlarged.

In this embodiment, the portion of the storage capacitor Cadd provided in the portion where the pixel electrode ITO1 and the gate signal line GL of the adjacent pixel overlap also consists of a metal having a light-shielding property in the gate signal line GL of the adjacent pixel. The same function as the first light shielding film BM1 is performed. Therefore, the first light shielding film BM1 can be retracted to a position where the gate signal line GL is exposed, and the aperture of the pixel is improved.

Further, in this embodiment, the protective film PSV1 and the insulating film GI are used as the dielectric of the gate-source capacitance Cgs. Since it is extremely unlikely that a pinhole exists in the same place of the protective film PSV1 and the insulating film GI, the portion I4 for adjusting the gate-source capacitance Cgs has a pixel electrode IT4.
There is no problem that O1 and the gate signal line GL are short-circuited.

Embodiment 6 Next, another embodiment for adjusting the gate-source capacitance Cgs is shown in FIGS. 33 (a) and 33 (b).

FIGS. 33 (a) and 33 (b) show FIG.
The thin film transistor TFT in the plan view of the pixel shown in FIG.
FIG. 4 is a diagram showing a portion near the line. FIG. 33 (a) and FIG.
The configuration of the portion not described in FIG. 3B is the same as the configuration of the pixel illustrated in FIG.

FIG. 33A shows the structure of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 33B shows the structure of the thin film transistor TFT on the far side from the input terminal.

In this embodiment, the direction of the channel length 1 of the thin film transistor TFT is arranged perpendicular to the direction in which the gate signal line GL extends.

In this embodiment, the adjustment pattern I5 provided on the gate signal line GL at the portion overlapping the source electrode SD1 is provided.
Thus, the capacitance Cgs between the gate and the source is adjusted to reduce the difference between the pixels of the potential drop component ΔV of the pixel electrode.

In order to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal with the adjustment pattern I5 provided on the gate signal line GL shown in FIGS. 33 (a) and 33 (b), The overlapping area of the adjustment pattern I5 and the source electrode SD1 may be increased as the pixel becomes farther from the input terminal.

Embodiment 7 FIGS. 34 (a) and 34 (b) show another embodiment for adjusting the gate-source capacitance Cgs.

FIGS. 34 (a) and 34 (b) also show FIG.
The thin film transistor TFT in the plan view of the pixel shown in FIG.
FIG. 4 is a diagram showing a portion near the line. FIG. 34 (a) and FIG.
The configuration of the portion not described in FIG. 4B is the same as the configuration of the pixel shown in FIG.

FIG. 34A shows the structure of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 34B shows the structure of the thin film transistor TFT on the far side from the input terminal.

Also in this embodiment, the direction of the channel length 1 of the thin film transistor TFT is arranged perpendicular to the direction in which the gate signal line GL extends.

In the present embodiment, an adjustment pattern I6 is provided on the gate signal line GL so as to overlap the pixel electrode ITO1, and the gate-source capacitance Cgs is adjusted to reduce the difference between the pixels of the potential drop component ΔV of the pixel electrode. doing.

In order to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal with the adjustment pattern I6 provided on the gate signal line GL shown in FIGS. 34 (a) and 34 (b), The more the pixel is farther from the input terminal, the larger the overlapping area of the adjustment pattern I6 and the pixel electrode ITO1 should be than the area of the pixel closer to the input terminal.

Eighth Embodiment FIGS. 35A and 35B show another embodiment for adjusting the gate-source capacitance Cgs.

FIGS. 35A and 35B also show FIGS.
The thin film transistor TFT in the plan view of the pixel shown in FIG.
FIG. 4 is a diagram showing a portion near the line. FIG. 35 (a) and FIG.
The configuration of the portion not described in FIG. 5B is the same as the configuration of the pixel shown in FIG.

FIG. 35A shows the structure of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 35B shows the structure of the thin film transistor TFT on the far side from the input terminal.

In this embodiment, the gate electrode GT of the thin film transistor TFT is provided to be branched from the gate signal line GL.

In this embodiment, adjustment patterns I7 and I7 'are provided in two portions of the source electrode SD1 of the thin film transistor TFT which overlap the gate electrode GT to form a gate electrode.
The capacitance Cgs between the sources is adjusted to reduce the difference between the pixels of the potential drop component ΔV of the pixel electrode.

The adjustment patterns I7 and I7 'provided on the source electrode SD1 shown in FIGS. 35 (a) and 35 (b) reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal. May be obtained by increasing the total area of the adjustment patterns I7 and I7 'as the pixel becomes farther from the input terminal.

In the present embodiment shown in FIGS. 35A and 35B, the width of the semiconductor layer AS is smaller than the width of the source electrode SD1, and the channel width of the thin film transistor TFT is determined by the width of the semiconductor layer AS. W is specified. And a pattern I for adjusting the gate-source capacitance Cgs.
7 and I7 'are provided in portions not overlapping with the semiconductor layer AS, so that the adjustment patterns I7, I7' are provided on the source electrode SD1.
By providing 7 ', the driving ability of the thin film transistor TFT does not change.

In the embodiment shown in FIGS. 35 (a) and 35 (b), the semiconductor layer AS is planarly arranged to shield the semiconductor layer AS from light by the gate electrode GT and to prevent malfunction of the thin film transistor TFT. , Only in the region where the gate electrode GT exists. Therefore, when the semiconductor layer AS is completely shielded from light by the gate electrode GT, there is a portion without the semiconductor layer AS between the source electrode SD1 and the gate electrode GT, which has a disadvantage that the gate-source capacitance Cgs becomes large. However, in the present embodiment, the gate-source capacitance Cgs is adjusted to reduce the difference in the potential lowering component ΔV of the pixel electrode, so that the gate electrode GT completely shields the semiconductor layer AS from the gate electrode GT. The disadvantage that the source-to-source capacitance Cgs increases can be reduced.

Ninth Embodiment FIGS. 36A and 36B show another embodiment for adjusting the storage capacitance Cadd.

FIGS. 36A and 36B are diagrams showing the planar structure of the pixel of this embodiment.

FIGS. 36A and 36B also show FIGS.
It has the same structure as the liquid crystal display device having the pixel structure shown in FIG. Therefore, the configuration of a portion which is not particularly described in this embodiment is the same as the configuration of the pixel shown in FIG.

FIG. 36A shows a pixel on the input terminal side, and FIG.
(B) shows a configuration of a pixel far from the input terminal.

In this embodiment, the storage capacitor Cadd is adjusted by changing the area of the portion where the pixel electrode ITO1 and the gate signal line GL of the adjacent pixel overlap, and the difference between the pixels of the potential drop component ΔV of the pixel electrode is reduced. doing.

In order to adjust the storage capacitor Cadd shown in FIGS. 36 (a) and 36 (b) and reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal, the side near the input terminal must be adjusted. The overlap area between the gate signal line GL and the pixel electrode ITO1 of the pixel farther from the input terminal than the pixel of
The storage capacity Cadd may be reduced by reducing the storage capacity Cadd by a predetermined amount indicated by d.

Embodiment 10 FIGS. 37A and 37B show another embodiment for adjusting the liquid crystal capacitance Cpix.

FIGS. 37A and 37B are views showing the planar structure of the pixel of this embodiment.

FIGS. 37A and 37B also show FIGS.
It has the same structure as the liquid crystal display device having the pixel structure shown in FIG. Therefore, the configuration of a portion which is not particularly described in this embodiment is the same as the configuration of the pixel shown in FIG.

FIG. 37A shows a pixel on the input terminal side, and FIG.
(B) shows a configuration of a pixel far from the input terminal.

In this embodiment, the area of the pixel electrode ITO1 is changed, the area of the pixel electrode ITO1 overlapping with the common electrode COM is changed, the liquid crystal capacitance Cpix is adjusted, and the difference between the pixels of the pixel electrode potential drop component ΔV is reduced. ing.

To change the area of the pixel electrode ITO1 shown in FIGS. 37 (a) and 37 (b) to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal, the input terminal The liquid crystal capacitance Cpix may be reduced by reducing the area of the pixel electrode farther from the input terminal than the pixel on the near side by a predetermined amount indicated by d.

In this embodiment, FIG. 37 (a) and FIG.
Even if the area of the pixel electrode ITO1 is changed as shown in FIG.
The opening area of the first light-shielding film BM1 is the same for pixels near the input terminal and pixels far from the input terminal. Further, in this embodiment, the pixel electrode IT in a portion covered with the first light-shielding film BM1 is used.
Since the area of the pixel electrode is changed by changing the shape of O1, and the liquid crystal capacitance Cpix is adjusted, there is no difference in the aperture through which light passes between the pixel near the input terminal and the pixel far from the input terminal.
No luminance difference occurs.

Embodiment 11 FIGS. 38A and 38B show a second light shielding film BM2.
Is formed of a light-shielding metal film, and another example in which the overlapping area of the second light-shielding film BM2 and the pixel electrode ITO1 is adjusted.

FIGS. 38A and 38B are views showing the planar structure of the pixel of this embodiment.

FIGS. 38A and 38B also show FIGS.
It has the same structure as the liquid crystal display device having the pixel structure shown in FIG. Therefore, the configuration of a portion which is not particularly described in this embodiment is the same as the configuration of the pixel shown in FIG.

FIG. 38A shows a pixel on the input terminal side, and FIG.
(B) shows a configuration of a pixel far from the input terminal.

In this embodiment, the second light-shielding film BM2 and the gate signal line GL of the adjacent pixel are electrically connected, and the area where the second light-shielding film BM2 and the pixel electrode ITO1 overlap with each other is changed. The difference between the pixels of the potential drop component ΔV is reduced.

In this embodiment, since the second light-shielding film BM2 is electrically connected to the gate signal line GL of the adjacent pixel, the portion where the second light-shielding film BM2 and the pixel electrode ITO1 overlap is the storage capacitor Cadd. Works the same as.

[0286] The second one shown in FIG. 38 (a) and FIG.
In order to reduce the difference of the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal by changing the overlapping area of the light shielding film BM2 and the pixel electrode ITO1, the second light shielding film of the pixel closer to the input terminal The storage area Cadd may be increased by increasing the area where the BM2 and the pixel electrode ITO1 overlap with each other by a predetermined amount indicated by d as compared with the pixel farther from the input terminal.

In this embodiment, the second light shielding film B serving as a storage capacitor electrode is maintained without changing the area of the pixel electrode ITO1.
Since the area of the portion overlapping the pixel electrode ITO1 of M2 is changed, the liquid crystal capacitance Cpix does not change even if the storage capacitance Cadd changes for each pixel. Therefore, the holding capacity Ca
Since dd and the liquid crystal capacitance Cpix can be set independently,
Pixel design is easy.

The second light shielding film BM2 and the pixel electrode IT
If the overlapping area of O1 is changed, there is a problem that the aperture of the pixel changes. However, as shown in FIGS. 38A and 38B, the first light-shielding film BM1 provided on the second transparent substrate SUB2 is used. By changing the overlapping area of the second light-shielding film BM2 and the pixel electrode ITO1 in the region covered by the above, the problem that the aperture of the pixel changes can be solved.

In this embodiment, the example in which the second light-shielding film BM2 is electrically connected to the gate signal line GL has been described. However, the pixel electrode I is electrically connected to the second light-shielding film BM2 in a floating state.
Even if the area overlapping with TO1 is changed, it is possible to reduce the difference in the potential reduction component ΔV of the pixel electrode. When the second light-shielding film BM2 is in an electrically floating state, when the area overlapping with the pixel electrode ITO1 is changed, the capacitance Cds1 between the source and the drain or the capacitance Cds2 between the pixel electrode and the drain signal line is changed. Can be done. In this case, the second light-shielding film BM2 and the pixel electrode I become closer to the pixel closer to the input terminal.
What is necessary is just to increase the area which overlaps with TO1.

However, increasing the capacitance Cds1 between the source and the drain and the capacitance Cds2 between the pixel electrode and the drain signal line involves a problem of crosstalk between pixels.
8 (a) and FIG. 38 (b), the second light shielding film BM
2 is preferably connected to the gate signal line GL.

[0291]

As is apparent from the above description,
According to the liquid crystal display device of the present invention, it is possible to suppress the occurrence of flicker.

[Brief description of the drawings]

FIG. 1 is a plan view of an essential part showing one embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is an equivalent circuit diagram showing one embodiment of a liquid crystal display device according to the present invention.

FIG. 3 is a plan view showing one embodiment of a pixel region of the liquid crystal display device according to the present invention.

FIG. 4 is a sectional view taken along line IV-IV in FIG.

FIG. 5 is a sectional view taken along line VV of FIG. 3;

FIG. 6 is a sectional view taken along line VI-VI in FIG.

FIGS. 7A to 7D are explanatory views showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 8 is a plan view showing another embodiment of the liquid crystal display device according to the present invention.

FIGS. 9A and 9B are plan views showing another embodiment of the liquid crystal display device according to the present invention.

FIGS. 10A and 10B are plan views showing another embodiment of the liquid crystal display device according to the present invention.

FIGS. 11A and 11B are plan views showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 12 is an equivalent circuit diagram showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 13 is a plan view showing another embodiment of the pixel region of the liquid crystal display device according to the present invention.

FIG. 14 is a sectional view taken along line VI-VI of FIG.

FIG. 15 is a diagram showing an equivalent circuit of a unit pixel of a TFT active matrix liquid crystal display device.

FIG. 16 is a driving waveform diagram of the TFT active matrix liquid crystal display device.

FIG. 17 is an equivalent circuit of one line of a liquid crystal display panel.

18A is a diagram illustrating a terminal side, FIG. 18B is a diagram illustrating a center portion,
(C) is a driving waveform diagram of the thin film transistor TFT of the pixel on the terminal side.

FIG. 19 is a process chart illustrating a method for manufacturing the thin film transistor substrate SUB1.

FIG. 20 is a process chart showing a method for manufacturing the thin film transistor substrate SUB1.

FIG. 21 is a process chart showing a method for manufacturing the thin film transistor substrate SUB1.

22A is a diagram illustrating a method of forming a pattern on a thin film transistor substrate SUB1 by photolithography, and FIG. 22B is a diagram illustrating an example of a photomask pattern.

23A is a diagram showing another method of forming a pattern on a thin film transistor substrate SUB1 by photolithography, and FIG. 23B is a diagram showing another example of a photomask pattern.

FIG. 24 is an equivalent circuit of a liquid crystal display device according to another embodiment in which scanning signal line driving circuit portions 104 are provided at both left and right ends of a gate signal line.

FIG. 25 is a plan view showing a unit pixel of an in-plane switching mode active matrix liquid crystal display device to which the present invention is applied.

FIG. 26 is a view showing a cross section taken along line 3-3 of FIG. 25;

FIGS. 27A and 27B are plan views of a main part of a pixel, showing another embodiment of the liquid crystal display device according to the present invention.

FIGS. 28A and 28B are plan views of a main part of a pixel, showing another embodiment of the liquid crystal display device according to the present invention.

FIGS. 29A and 29B are plan views of a pixel portion showing another embodiment of the liquid crystal display device according to the present invention.

30 is a sectional view taken along line IV-IV in FIG.

FIG. 31 is a sectional view taken along line VV in FIG. 29;

32 is a sectional view taken along line VI-VI of FIG.

33 (a) and (b) are plan views of a main part of a pixel, showing another embodiment of the liquid crystal display device according to the present invention.

34 (a) and (b) are plan views of a main part of a pixel, showing another embodiment of the liquid crystal display device according to the present invention.

FIGS. 35A and 35B are plan views of a main part of a pixel, showing another embodiment of the liquid crystal display device according to the present invention.

36 (a) and (b) are plan views of a pixel showing another embodiment of the liquid crystal display device according to the present invention.

FIGS. 37 (a) and (b) are plan views of pixels showing another embodiment of the liquid crystal display device according to the present invention.

38 (a) and (b) are plan views of a pixel, showing another embodiment of the liquid crystal display device according to the present invention.

[Explanation of symbols]

GL: gate signal line, DL: drain signal line, ITO1
... Pixel electrode, TFT: Thin film transistor, GI: Gate insulating film, AS: Semiconductor layer, SD1: Source electrode, SD2
... Drain electrode.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hikaru Ito 3300 Hayano, Mobara-shi, Chiba Prefecture Inside the Electronic Devices Division, Hitachi, Ltd. (72) Inventor Tatsuo Kamei 3300, Hayano, Mobara-shi, Chiba Electronic Devices Business, Hitachi, Ltd. (72) Inventor Tetsuya Kawamura 3300 Hayano Mobara-shi, Chiba Pref.Electronic Device Division, Hitachi, Ltd. (72) Inventor Masataka Natori 3300 Hayano, Mobara-shi, Chiba Pref.Electronic Device Division, Hitachi, Ltd. (72) Inventor Hidetaka Hakoda 3300 Hayano Mobara-shi, Chiba Electronic Device Division, Hitachi, Ltd.

Claims (12)

[Claims] A first signal line provided on a first insulating substrate; a driving circuit electrically connected to the gate signal line to output a gate driving voltage; and a first electrode having a source electrode, a gate electrode, and a drain electrode.
And a second thin film transistor; a first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; and an electrically connected to one of a source electrode and a drain electrode of the second thin film transistor A second pixel electrode; a first video signal line electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor; and an electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor A second video signal line, wherein a gate electrode of the first thin film transistor is electrically connected to a first portion of the gate signal line, and a gate electrode of the second thin film transistor is a first electrode of the gate signal line. And electrically connected to a second portion farther from the drive circuit than the portion, the sources of the first and second thin film transistors The electrode is separated from the drain electrode by a channel length on the gate electrode, and is opposed to the drain electrode by a channel width. The channel length and the channel width of the second thin film transistor are the same as the channel length and the channel width of the first thin film transistor. A liquid crystal display wherein the capacitance between the second pixel electrode and the gate signal line is larger than the capacitance between the first pixel electrode and the gate signal line. apparatus. 2. The liquid crystal display device according to claim 1, wherein the length from the first portion to the second portion is 27 cm or more. 3. The liquid crystal display device is provided with a transparent second insulating substrate provided so as to overlap with the first insulating substrate, and at a position of the second insulating substrate facing the first and second pixel electrodes. 2. The liquid crystal display device according to claim 1, comprising: a transparent common electrode; and a liquid crystal provided between the common electrode and the first and second pixel electrodes. 4. A gate electrode provided on an insulating substrate, an insulating film provided on the gate electrode, a semiconductor layer provided on the insulating film, and a source electrode and a drain electrode provided on the semiconductor layer. A first pixel electrode electrically connected to a source electrode of the first thin film transistor; a second pixel electrode electrically connected to a source electrode of the second thin film transistor; A first video signal line electrically connected to a drain electrode of one thin film transistor; a second video signal line electrically connected to a drain electrode of the second thin film transistor; a gate signal line provided on the insulating substrate; A terminal electrically connected to the gate signal line for inputting a driving voltage, wherein a gate electrode of the first thin film transistor is connected to a first portion of the gate signal line. The gate electrode of the second thin film transistor is electrically connected to a second portion farther from the terminal than the first portion of the gate signal line, and the source electrodes of the first and second thin film transistors are The source electrode and the drain electrode are provided on the semiconductor layer so as to be opposed to the drain electrode with a distance therebetween, and the semiconductor layer of the first and second thin film transistors has an excessively formed portion that overlaps the gate electrode. A liquid crystal display provided near the source electrode except for a portion, wherein the area of the over-formed portion of the semiconductor layer of the second thin-film transistor is larger than the area of the over-formed portion of the semiconductor layer of the first thin-film transistor. apparatus. 5. A gate electrode provided on an insulating substrate, an insulating film provided on the gate electrode, a semiconductor layer provided on the insulating film, and a source provided on the semiconductor layer and / or the insulating film. A first and a second thin film transistor having an electrode and a drain electrode; a first pixel electrode electrically connected to a source electrode of the first thin film transistor; and a second pixel electrically connected to a source electrode of the second thin film transistor. An electrode, a first video signal line electrically connected to a drain electrode of the first thin film transistor, a second video signal line electrically connected to a drain electrode of the second thin film transistor, and provided on the insulating substrate. A gate signal line; a terminal electrically connected to the gate signal line for inputting a drive voltage; A gate electrode of the second thin film transistor is electrically connected to a second portion of the gate signal line farther from the terminal than the first portion; The source electrode of the second thin film transistor is separated from the drain electrode by a channel length on the gate electrode, and is provided so as to face the channel width. The channel length and the channel width of the second thin film transistor are the same as those of the first thin film transistor. And the area of a portion of the source electrode of the second thin film transistor overlapping the gate signal line is larger than the area of a portion of the source electrode of the first thin film transistor overlapping the gate signal line. A liquid crystal display device characterized by the above-mentioned. 6. The liquid crystal display device according to claim 5, wherein the semiconductor layer is provided in a plane in a region where the gate electrode is formed. 7. A first circuit comprising: a gate signal line provided on an insulating substrate; a driving circuit electrically connected to the gate signal line to output a gate driving voltage; and a first electrode having a source electrode, a gate electrode, and a drain electrode.
And a second thin film transistor; a first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; and an electrically connected to one of a source electrode and a drain electrode of the second thin film transistor A second pixel electrode; a first video signal line electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor; and an electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor A second video signal line, wherein a gate electrode of the first thin film transistor is electrically connected to a first portion of the gate signal line, and a gate electrode of the second thin film transistor is a first electrode of the gate signal line. The first and second pixel electrodes are electrically connected to a second portion farther from the drive circuit than the portion. A part where the signal line partially overlaps with the insulating film interposed therebetween, and an area of a part where the second pixel electrode and the gate signal line overlap is made larger than an area of a part where the first pixel electrode and the gate signal line overlap. Characteristic liquid crystal display device. 8. A first signal line having a gate signal line provided on an insulating substrate, a terminal electrically connected to the gate signal line for inputting a driving voltage, a source electrode, a gate electrode, and a drain electrode.
And a second thin film transistor; a first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; and an electrically connected to one of a source electrode and a drain electrode of the second thin film transistor A second pixel electrode; a first video signal line electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor; and an electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor A second video signal line, wherein a gate electrode of the first thin film transistor is electrically connected to a first portion of the gate signal line, and a gate electrode of the second thin film transistor is a first electrode of the gate signal line. And electrically connected to a second portion farther from the terminal than the portion, and a static electricity between the second pixel electrode and the gate signal line. The capacitance is larger than the capacitance between the first pixel electrode and the gate signal line, and the source electrodes of the first and second thin film transistors are separated from the drain electrode by a channel length on the gate electrode. The first and second thin film transistors are provided so as to be opposed to each other by a channel width, and one of the source electrode and the drain electrode of the first and second thin film transistors is connected to the pixel electrode and does not overlap with the gate electrode. A liquid crystal display device wherein a width between portions is smaller than a channel width of the first and second thin film transistors. 9. A drive circuit, wherein the first gate signal line is provided on an insulating substrate, the capacitor line is provided on the insulating substrate adjacent to the first gate signal line, and the drive circuit is electrically connected to the gate signal line. A first terminal having a terminal for inputting voltage, a source electrode, a gate electrode, and a drain electrode;
And a second thin film transistor; a first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; and an electrically connected to one of a source electrode and a drain electrode of the second thin film transistor A second pixel electrode; a first video signal line electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor; and an electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor A second video signal line, wherein a gate electrode of the first thin film transistor is electrically connected to a first portion of the first gate signal line, and a gate electrode of the second thin film transistor is connected to the first gate signal. A second portion of the line that is electrically farther from the terminal than the first portion; The source electrode is separated from the drain electrode by a channel length on the gate electrode and is provided so as to face the channel width. The channel length and the channel width of the second thin film transistor are the channel length and the channel of the first thin film transistor. The first and second pixel electrodes partially overlap with the capacitance line via an insulating film, and the area where the second pixel electrode and the capacitance line overlap with each other is equal to the first pixel electrode and the first pixel electrode. A liquid crystal display device characterized in that the area is smaller than the overlapping area of the capacitance lines. 10. An electrical connection between a first gate signal line provided on an insulating substrate, a second gate signal line provided on the insulating substrate adjacent to the first gate signal line, and an electrical connection to the first gate signal line. A driving circuit that is connected in series and outputs a gate driving voltage; and a first circuit having a source electrode, a gate electrode, and a drain electrode.
And a second thin film transistor; a first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; and an electrically connected to one of a source electrode and a drain electrode of the second thin film transistor A second pixel electrode; a first video signal line electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor; and an electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor A second video signal line, wherein a gate electrode of the first thin film transistor is electrically connected to a first portion of the first gate signal line, and a gate electrode of the second thin film transistor is connected to the first gate signal. A second portion of the line farther from the drive circuit than the first portion;
The first and second thin film transistors are electrically connected to each other, and the source electrodes of the first and second thin film transistors are separated from the drain electrode by a channel length on the gate electrode by a channel width, and are provided opposite to each other by a channel width. A channel length and a channel width of the first thin film transistor are substantially equal to a channel length and a channel width of the first thin film transistor. The first and second pixel electrodes partially overlap with the second gate signal line via an insulating film. A liquid crystal display device, wherein an area where two pixel electrodes overlap the second gate signal line is smaller than an area where the first pixel electrode overlaps the second gate signal line. 11. A first circuit comprising: a gate signal line provided on an insulating substrate; a driving circuit electrically connected to the gate signal line to output a gate driving voltage; and a source electrode, a gate electrode, and a drain electrode.
And a second thin film transistor; a first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; and an electrically connected to one of a source electrode and a drain electrode of the second thin film transistor A second pixel electrode; a first video signal line electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor; and an electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor A second video signal line, wherein a gate electrode of the first thin film transistor is electrically connected to a first portion of the gate signal line, and a gate electrode of the second thin film transistor is a first electrode of the gate signal line. Between the second pixel electrode and the second video signal line. Wherein the capacitance between the first pixel electrode and the first video signal line is larger than the capacitance between the first pixel electrode and the first video signal line. 12. A semiconductor device comprising: a gate signal line provided on a first insulating substrate; a terminal electrically connected to the gate signal line for inputting a gate drive voltage; a source electrode, a gate electrode, and a drain electrode. 1
And a second thin film transistor; a first pixel electrode electrically connected to one of a source electrode and a drain electrode of the first thin film transistor; and an electrically connected to one of a source electrode and a drain electrode of the second thin film transistor A second pixel electrode; a first video signal line electrically connected to the other of the source electrode and the drain electrode of the first thin film transistor; and an electrically connected to the other of the source electrode and the drain electrode of the second thin film transistor A second video signal line, a transparent second insulating substrate provided so as to overlap the first insulating substrate, and a transparent second insulating substrate provided at a position facing the first and second pixel electrodes on the second insulating substrate. A common electrode; a liquid crystal provided between the common electrode and the first and second pixel electrodes; and a first and second pixel provided on the second insulating substrate. A light-shielding film covering the periphery of the pole; a gate electrode of the first thin-film transistor is electrically connected to a first portion of the gate signal line; and a gate electrode of the second thin-film transistor is connected to a first portion of the gate signal line. A portion of the second pixel electrode that is electrically connected to a second portion that is farther from the terminal than a portion of the first portion and that is covered by the light-shielding film of the second pixel electrode; A liquid crystal display device characterized in that the area is smaller than the area of the liquid crystal display.