JP3677160B2 - Liquid crystal display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a liquid crystal display device, and more particularly to a method of manufacturing an active matrix type liquid crystal display device.
[0002]
[Prior art]
This type of liquid crystal display device includes a gate signal line extending in the x direction and arranged in parallel in the y direction on a liquid crystal side surface of one transparent substrate of a pair of transparent substrates arranged to face each other via a liquid crystal. A drain signal line extending in the y direction and arranged in parallel in the x direction is provided, and each region surrounded by these signal lines is defined as a pixel region.
[0003]
Each pixel region includes a thin film transistor that is turned on by a scanning signal from the gate signal line, and a pixel electrode to which a video signal from the drain signal line is applied via the turned on thin film transistor. ing.
[0004]
Such a liquid crystal display device can be configured with good contrast, and has become an indispensable technique particularly for color liquid crystal display devices.
[0005]
Japanese Patent Laid-Open No. 9-258261 discloses a prior art in which the TFT size increases toward the end of the gate bus line in order to prevent the TFT driving capability near the end from being lowered due to waveform distortion of the gate bus line. There is. However, the above prior art has no idea of making the amount of voltage (ΔV) entering the pixel electrode constant through the gate-source capacitance (Cgs) without changing the size of the TFT.
[0006]
Therefore, in the prior art described above, since the size of the TFT is different for each place of the display region, the driving condition of the TFT is different for each place, and it is difficult to find the optimum driving condition of the liquid crystal display device. There is a problem that the design of the system becomes complicated.
[0007]
[Problems to be solved by the invention]
However, in such a liquid crystal display device, a flickering of a screen called a so-called flicker has occurred as a problem that cannot be ignored due to the trend toward larger size and higher definition in recent years. In particular, it has become a problem that cannot be ignored in a liquid crystal display device having a diagonal length of 34 cm (13 type) or more in the display area.
[0008]
Accordingly, as a result of pursuing the cause of flicker, the present inventors have found the following.
[0009]
First, since the gate signal line must be formed long, the waveform distortion occurs due to the influence of the resistance and capacitance of the signal line, and the scanning signal line input to the terminal signal side.
[0010]
This waveform distortion delays the gate-off timing of the thin film transistor and reduces the source electrode potential lowering component due to the voltage jumping through the gate-source capacitance when the gate is turned off. This means that the source electrode potential on the termination side becomes higher than the input terminal side of the gate signal line.
[0011]
For this reason, the electrode (common electrode) opposed to the pixel electrode via the liquid crystal is applied with a constant potential uniformly within the display surface, so that the voltage applied to the liquid crystal is the input terminal of the gate signal line. Will be different on the side and end side.
[0012]
In order to avoid polarization of the liquid crystal, alternating drive is performed to invert the potential applied to the liquid crystal, so that the magnitude relationship between the applied voltage of the liquid crystal is changed between the input terminal side and the termination side of the gate signal line. Inversion occurs every half cycle of the drive, resulting in flickering of the screen due to luminance changes.
[0013]
Particularly, a 13-type liquid crystal display device has a display area of 20 cm in length and 27 cm in width, the length of the gate signal line is 27 cm or more, and the gate-source capacitance is increased on the input terminal side and the termination side of the gate signal line. The difference between the voltages jumping in through the circuit becomes so large that it cannot be ignored.
[0014]
Therefore, in a liquid crystal display device having a gate signal line length of 27 cm or more (13 type or more), it has become difficult to completely eliminate flicker only by adjusting the potential of the common electrode.
[0015]
In addition, when forming each signal line and thin film transistor by selective etching using photolithography technology, the pattern of the thin film transistor in each pixel region is completely uniform due to distortion of the optical system of the exposure apparatus or deflection of the transparent substrate. It has become difficult.
[0016]
In this case, if the gate-source capacitance of the thin film transistor is not uniform due to the variation in the pattern, the amount of decrease in the source potential due to the gate-source capacitance when the gate is turned off is not constant in the screen.
[0017]
Therefore, even in this case, the screen flickers due to the luminance change for the same reason as described above.
[0018]
The present invention has been made based on such circumstances, and an object of the present invention is to provide a method of manufacturing a liquid crystal display device capable of completely suppressing the occurrence of flicker even in a liquid crystal display device having a large display screen.
[0019]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
[0020]
That is, a method for manufacturing a liquid crystal display device according to the present invention includes a plurality of pixels and a scanning signal line for grouping some of these pixels and responsible for driving the pixels in each group. As a sample,
Obtaining a correction value for making the capacitance in each pixel constant along the extending direction of the scanning signal line in relation to the extending distance of the scanning signal line;
Determining each section that defines the extension distance of the scanning signal line corresponding to each section that defines the correction value; and
And a step of performing capacitance correction according to the correction value of the section corresponding to each of the pixels corresponding to each section of the extension distance of the scanning signal line.
[0021]
The manufacturing method of the liquid crystal display device configured as described above can determine the required capacitance correction value for each section that divides the extension distance of the scanning signal line based on the above-described sample, and the capacitance correction. The capacity can be corrected based on the value.
[0022]
For this reason, it becomes possible to make the capacitance of each pixel formed along the extending direction of the scanning signal line substantially uniform by a very simple method.
[0023]
Therefore, it is possible to obtain a liquid crystal display device that can completely suppress the occurrence of flicker even in a liquid crystal display device having a large display screen.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a liquid crystal display device according to the present invention will be described with reference to the drawings.
[0025]
Embodiment 1
<< Equivalent circuit of LCD panel >>
FIG. 2 is a circuit diagram showing an equivalent circuit on one transparent substrate (TFT substrate) side among the transparent substrates constituting the liquid crystal display panel. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement.
[0026]
On the surface of the TFT substrate TFT-LCD in FIG. 2 on the liquid crystal side, there are gate signal lines (also referred to as scanning signal lines) GL extending in the x direction and arranged in parallel in the y direction, and these gate signal lines GL. A drain signal line (also referred to as a video signal line) DL that is insulated, extends in the y direction, and is juxtaposed in the x direction is formed.
[0027]
A rectangular region surrounded by the gate signal line GL and the drain signal line DL constitutes a pixel region, and a scanning signal (voltage) from one gate signal line GL is supplied to each pixel region. And a pixel electrode ITO1 to which a video signal (voltage) supplied from one drain signal line is applied via the turned-on thin film transistor TFT.
[0028]
The pixel electrode ITO1 is composed of a transparent conductive layer made of, for example, Indium-Tin-Oxide.
[0029]
Further, an additional capacitance element Cadd is provided between the pixel electrode ITO1 and the other gate signal line GL so that a video signal applied to the pixel electrode ITO1 can be accumulated for a long time when the thin film transistor TFT is turned off. ing.
[0030]
Note that each pixel electrode ITO1 is marked with one of R, G, and B, which indicates the three primary colors red, green, and blue, and the corresponding color in each pixel region. Is supposed to be in charge. Specifically, a filter of a color corresponding to the filter substrate (second transparent substrate SUB2) side disposed to face the TFT substrate (first transparent substrate SUB1) is formed.
[0031]
In such a display panel, a scanning signal line drive circuit unit 104 and a video signal line drive circuit unit 103 are connected as external circuits.
[0032]
A scanning signal is sequentially input from the scanning signal line driving circuit 104 to each gate signal line, and a video signal is input from the video signal line driving circuit unit 103 to each drain signal line in accordance with the timing.
[0033]
Further, a power supply unit 102 and a controller unit 101 are connected to the scanning signal line drive circuit unit 104 and the video signal line drive circuit unit 103 so that power is supplied to each circuit unit and signals are transmitted. It has become.
[0034]
A black matrix layer is formed on the surface of the liquid crystal side of another transparent substrate (filter substrate) arranged opposite to the TFT substrate TFT with the liquid crystal in this way so as to frame the frame of the pixel region. A color filter is formed so as to cover the pixel region and to have its periphery superimposed on the black matrix layer BM.
[0035]
And the common electrode which consists of a transparent conductive layer is formed through the protective film formed also covering these black matrix layers and a color filter.
[0036]
Further, an alignment film for regulating the alignment of the liquid crystal is formed on the upper surface of the common electrode.
[0037]
<Pixel area configuration>
FIG. 3 is a plan view showing a specific configuration of the pixel region corresponding to the dotted frame A in FIG.
[0038]
3 is a sectional view taken along line IV-IV in FIG. 3, FIG. 5 is a sectional view taken along line V-V, and FIG. 6 is a sectional view taken along line VI-VI.
[0039]
First, gate signal lines GL extending in the x direction and arranged in parallel in the y direction are formed on the liquid crystal side surface of the transparent substrate SUB1.
[0040]
This gate signal line GL is made of a material in which an aluminum oxide film AOF (formed by anodization) is formed on the surface of a conductive layer gl made of, for example, aluminum.
[0041]
A pixel electrode ITO1 made of a transparent conductive film (for example, Indium-Tin-Oxide) is formed in most of the pixel region surrounded by the gate signal line GL and a drain signal line DL described later.
[0042]
A part of the pixel region on the gate signal line GL on the lower left side of the drawing is a formation region of the thin film transistor TFT. In this region, for example, a gate insulating film GI made of SiN, a semiconductor layer made of i-type amorphous Si The AS, the drain electrode SD2, and the source electrode SD1 are sequentially stacked.
[0043]
It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so that the source and drain are interchanged during operation. However, in this specification, the electrode directly connected to the pixel electrode ITO1 is expressed as a source electrode.
[0044]
The drain electrode SD2 and the source electrode SD1 are formed simultaneously with the drain signal line DL.
[0045]
That is, the drain signal line DL is formed in the formation region on the gate insulating film GI of the thin film transistor TFT, the insulating film GI formed simultaneously with the formation of the semiconductor layer AS, and the semiconductor layer AS. It is formed of a laminate (see FIG. 5). The reason why the insulating film GI and the semiconductor layer AS are formed in the formation region of the drain signal line DL is, for example, to reduce the step over the drain signal line DL.
[0046]
The drain electrode SD2 of the thin film transistor TFT is formed integrally with the drain signal line DL, and the source electrode SD1 is formed apart from the drain electrode SD2 by a predetermined channel length and extends to a part of the pixel electrode ITO1. It is formed by being directly superimposed.
[0047]
Further, as shown in FIG. 6, the additional capacitor element Cadd forms a gate signal line (another gate signal line adjacent to the gate signal line for driving the thin film transistor TFT) GL simultaneously with one electrode and the drain signal line DL. The conductive layer ITO2 formed simultaneously with the conductive layer d1 and the pixel electrode ITO1 is used as the other electrode, and an aluminum oxide film AOF (silicon nitride film GI) that is an insulating film interposed therebetween may be used. ) As a dielectric film.
[0048]
The insulating film GI and the semiconductor layer AS are formed simultaneously with their formation in the thin film transistor TFT, and the conductive layer d1 which is the other electrode extends directly to a part of the pixel electrode ITO1 and directly. Overlaid.
[0049]
A protective film PSV1 made of SiN is formed on the surface of the pixel region configured in this way, so as to avoid characteristic deterioration due to direct contact of the liquid crystal with the thin film transistor TFT.
[0050]
In addition, an alignment film (not shown) for regulating the alignment of the liquid crystal is formed over the entire surface of the protective film PSV1.
[0051]
<< TFT operation >>
FIG. 15 is a diagram showing an equivalent circuit of a unit pixel of the TFT active matrix liquid crystal display device.
[0052]
The thin film transistor TFT is turned on by biasing the gate electrode with a positive voltage with respect to the source electrode (the resistance value between the source and the drain is reduced), and turned off by making the bias supplied to the gate electrode close to zero. It has a transfer characteristic that the state, that is, the resistance value between the source and the drain becomes large.
[0053]
FIG. 16 is a waveform diagram for explaining an example of the operation of the liquid crystal display device shown in FIG.
[0054]
It should be noted that the signals VG, VD and the voltage PXV of the pixel PIX shown in FIG. 16 are the same as those of the signals VG, VD and PXV in order to prevent the distinction between the waveforms due to their overlapping. They are drawn in time order.
[0055]
The video signal (drain signal) VD supplied from the video signal line DL is written to the pixel PIX coupled to the gate signal line Gi (GL) selected according to the high level of the scanning signal (gate signal) VG. . At this time, as indicated by a dotted line in FIG. 16, the voltage PXV of the pixel PIX corresponds to the fact that the TFT to be turned on has a resistance component and the pixel PIX is the capacitive element Cpix. Stand up according to a constant. In FIG. 16, initially, a video signal VD of a positive level that brings a pixel (or a liquid crystal cell) to a high gradation state is shown. In response to the selection of the next gate signal line Gi + 1 (GL), the scanning signal VG shown in FIG. 16 is changed from the high level selection level to the low level non-selection level. As a result, the TFT is turned off, so that the written video signal VD is held in the pixel PIX acting as the capacitive element Cpix. In response to the switching of the scanning signal VG from the high level to the low level, the pixel voltage PXV is changed to the pixel PIX (or an electrode connected to the pixel electrode among the source electrode or drain electrode of the TFT. ) And a parasitic capacitance Cgs between the gate electrodes of the TFTs causes a potential drop component ΔV. Note that the voltage jumping into the pixel PIX due to the gate-source coupling Cgs by switching the scanning signal VG from low level to high level can be canceled by writing the video signal VD from the drain line Xi (DL). The voltage jumping into the pixel PIX when the scanning signal VG is switched from the high level to the low level cannot be canceled by writing the video signal VD.
[0056]
In FIG. 16, the video signal VD having a low gradation level is supplied for one frame thereafter.
[0057]
In general, since the liquid crystal display device performs AC driving, the polarity of the video signal VD is switched between positive and negative for each cycle of the scanning signal VG.
[0058]
That is, as shown in FIG. 16, when the scanning signal VG is again set to the high level selection level, the video signal VD is set to the desired negative gradation level. FIG. 16 shows an example in which the negative polarity high gradation level is used. Also in this case, since the TFT to be turned on has a resistance component and the pixel PIX is the capacitive element Cpix, the voltage PXV of the pixel falls according to a time constant corresponding thereto. In response to selection of the next gate signal line Gi + 1 (not shown), the scanning signal VG shown in FIG. 16 is changed from the high level selection level to the low level non-selection level. As a result, the TFT is turned off, so that the video signal VD is held in the pixel PIX acting as the capacitive element Cpix.
[0059]
In response to the switching of the scanning signal VG from the high level to the low level, the voltage PXV of the pixel has a potential drop component ΔV similar to the above due to the parasitic capacitance Cgs between the gate electrode and the source electrode of the TFT. As in the case of the positive polarity, when the scanning signal VG is switched from the low level to the high level, the voltage jumping into the pixel PIX due to the gate-source coupling Cgs is canceled by the writing of the video signal VD from the drain signal line Xi. However, the voltage jumping into the pixel PIX when the scanning signal VG is switched from the high level to the low level cannot be canceled by the writing of the video signal VD. Accordingly, even in the negative polarity, the voltage jumping into the pixel PIX due to the gate-source coupling Cgs similarly to the positive polarity lowers the pixel voltage PXV in the negative direction.
[0060]
In FIG. 16, the video signal VD having a low negative polarity gradation level is supplied for one frame thereafter.
[0061]
As described above, when the scanning signal VG changes from the high level to the low level in both the positive polarity and the negative polarity of the liquid crystal AC drive, the pixel voltage PXV is written by the parasitic capacitance Cgs between the gate electrode and the source electrode of the TFT. With respect to the level of the video signal VD at the time, as shown by a dotted line in FIG.
[0062]
Accordingly, the bias voltage Vcom applied to the common electrode COM of the liquid crystal display panel is a substantially intermediate level between the positive polarity and the negative polarity of the voltage PXV of the pixel, as shown by a two-dot chain line in FIG. Optimal common electrode voltage). That is, the liquid crystal can be substantially AC driven by applying an optimal common electrode voltage in consideration of the potential drop ΔV of the pixel voltage PXV to the common electrode COM.
[0063]
If the bias voltage Vcom applied to the common electrode COM deviates from the optimum common electrode voltage described above, a difference occurs in the voltage Vlc applied to the liquid crystal during the period of the positive polarity and negative polarity of the liquid crystal AC drive, and flicker and This causes a periodic luminance change, and the display image quality is significantly reduced.
[0064]
<Operation of storage capacitor>
In FIG. 15, Cgs is a parasitic capacitance formed between the gate electrode and the source electrode of the thin film transistor TFT described above. The dielectric of the parasitic capacitance Cgs is an interlayer insulating film between the gate electrode and the source electrode. Cpix is a liquid crystal capacitance formed between the transparent pixel electrode PIX and the common transparent pixel electrode COM. The dielectric film of the liquid crystal capacitor Cpix is a liquid crystal and an alignment film. Vlc is a voltage applied to the liquid crystal.
[0065]
The storage capacitor element Cadd serves to reduce the influence of the potential change ΔVG of the scanning signal on the pixel electrode potential PXV when the thin film transistor TFT is switched. When this state is expressed by an expression, expression 1 is obtained.
[0066]
[Expression 1]
ΔV = {Cgs / (Cgs + Cds1 + Cds2 + Cadd + Cpix)} × ΔVG Equation 1
Here, ΔV represents the potential lowering component of the pixel voltage PXV due to the potential change ΔVG of the scanning signal described above. This potential lowering component ΔV causes a direct current component applied to the liquid crystal. However, as the storage capacitor Cadd is increased, the potential lowering component ΔV of the pixel voltage PXV can be reduced. In addition, the storage capacitor element Cadd also has an action of extending the discharge time, and accumulates video information after the thin film transistor TFT is turned off. Reduction of the DC component applied to the liquid crystal can improve the life of the liquid crystal and reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.
[0067]
15 and Formula 1, Cds1 is a parasitic capacitance between the source electrode SD1 and the drain electrode SD2 of the thin film transistor, and is also a capacitance between the pixel electrode PIX and the drain signal line Di.
[0068]
Cds2 represents the parasitic capacitance between the pixel electrode PIX and the drain signal line Di + 1 adjacent thereto, and Cgd represents the parasitic capacitance between the gate electrode and the drain electrode.
[0069]
As shown in FIG. 3, since the gate electrode GL is enlarged so as to cover the i-type semiconductor layer AS, an overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and thus the parasitic capacitance Cgs is increased. The electrode potential PXV has the adverse effect of being easily affected by the scanning signal VG. However, the provision of the storage capacitor element Cadd has an effect that the pixel electrode potential PXV is hardly affected by the parasitic capacitance Cgs.
[0070]
In this embodiment, since the capacitance of the pixel is approximately 150 fF, the capacitance of the storage capacitor element Cadd is set to approximately 100 fF in consideration of writing characteristics. Since the parasitic capacitance Cgs is approximately 15 fF, the capacitance of the storage capacitor element Cadd is 6 times or more of the parasitic capacitance Cgs.
[0071]
2, 3, and 6, an example of the additional capacitance method in which the storage capacitor Cadd is formed by overlapping a part of the gate signal line GL of the adjacent pixel and the pixel electrode ITO <b> 1 through an insulating film. Although the storage capacitor Cadd is not limited to this, as shown in FIGS. 12, 13, and 14, a capacitor line CL is provided separately from the gate signal line GL to insulate the capacitor line CL from the pixel electrode ITO1. A storage capacitor method in which the storage capacitor Cadd is formed by overlapping with a film may be used. In this embodiment, the additional capacitance method has an advantage that the aperture ratio can be increased and a disadvantage that the distributed capacitance of the gate signal line GL is increased. Further, in this embodiment, the storage capacitor method has an advantage that the distributed capacity of the gate signal line GL can be reduced, a disadvantage that the aperture ratio is reduced by providing the capacitor line CL, and a manufacturing process is increased.
[0072]
<< Measures to prevent variation in parasitic capacitance Cgs >>
Conventionally, since the display area of the liquid crystal display device was smaller than the 10 type (diagonal 25.4 cm), there was little variation in manufacturing the parasitic capacitance Cgs between the gate electrode and the source electrode, and the optimum common applied to the common electrode COM The electrode voltage Vcom is uniquely determined.
[0073]
However, when the display area of the liquid crystal display device is larger than 13 type (diagonal 34 cm), the manufacturing variation of the parasitic capacitance Cgs increases, and the optimum common electrode voltage Vcom applied to the common electrode COM is different for each part of the display area. However, there is a problem that it cannot be determined uniquely.
[0074]
In order to solve the above problem, in this embodiment, in particular, in the source electrode SD1 of the thin film transistor TFT, as shown in FIG. 1 which is an enlarged view thereof, the portion connected to the pixel electrode ITO1 and the gate electrode The width of the overlapping portion is smaller than the channel width w of the thin film transistor.
[0075]
That is, in the figure, the drain electrode SD2 is formed to extend from the drain signal line DL on the gate signal line GL along the traveling direction thereof and then bend toward the pixel electrode ITO1.
[0076]
In this case, it is a bent portion directed toward the pixel electrode ITO1 that substantially functions as the drain electrode SD2, and its length determines the channel width w of the thin film transistor TFT.
[0077]
The source electrode SD1 is arranged opposite to the bent portion of the drain electrode SD2 and spaced apart by an amount corresponding to the channel length l, and is extended to the pixel electrode ITO1 side as it is to be connected to the pixel electrode ITO1. It is illustrated.
[0078]
Therefore, the length of the side of the source electrode SD1 facing the drain electrode SD2 is the channel width.
[0079]
Here, the length of the width w0 perpendicular to the extending direction of the source electrode SD1 is smaller than the channel width w.
[0080]
Even when the source electrode SD1 configured as described above is formed, for example, by being displaced in the y direction in the drawing, the area of the overlapping portion of the source electrode SD1 with respect to the gate signal line GL varies greatly. Never do. This is because the width w0 perpendicular to the extending direction of the source electrode SD1 is formed to be relatively small.
[0081]
Further, when a positional shift occurs in the x direction in the figure, there is no change in the area of the overlapping portion of the source electrode SD1 with respect to the gate signal line GL.
[0082]
For this reason, even if a positional shift occurs in the rotation direction θ, the area of the overlapping portion of the source electrode SD1 with respect to the gate signal line GL does not change greatly.
[0083]
Therefore, the thin film transistor TFT in each pixel region can form the capacitance Cgs between the gate electrode and the source electrode almost uniformly, and the occurrence of flicker can be suppressed.
[0084]
Such an effect is not obtained only by the pattern of the drain electrode SD2 and the source electrode SD1 shown in FIG. 1, but for example, as shown in FIG. 7A to FIG. 7D. Needless to say, the pattern can be obtained similarly.
[0085]
In this case, in the above-described embodiment, the source electrode SD1 is configured to have a symmetrical relationship with the drain electrode SD2 except for an extending portion for connection to the pixel electrode ITO1.
[0086]
However, as shown in FIG. 8, the source electrode SD1 may be formed so as to extend in the direction opposite to the pixel electrode ITO1 for connecting to the source electrode SD1 so as to exceed the gate signal line GL. Needless to say.
[0087]
In this case, in order to avoid that the source electrode SD1 is connected to the pixel electrode ITO1 in the adjacent pixel region, the gate signal line GL is provided with a partially cutout GLC. It is configured to exceed.
[0088]
In other words, the source electrode SD1 formed integrally with another portion that does not substantially function as an electrode is formed so as to intersect the gate signal line GL.
[0089]
Even if the source electrode SD1 configured in this way is formed with a positional shift in the y direction as well as the x direction in the drawing, for example, the gate signal line GL of the source electrode SD1 is formed. The area of the overlapped portion with respect to does not change at all.
[0090]
For this reason, even if a positional shift occurs in the rotation direction θ, the area of the overlapping portion of the source electrode SD1 with respect to the gate signal line GL does not change at all.
[0091]
Therefore, the thin film transistor TFT in each pixel region can uniformly form the capacitance Cgs between the gate electrode and the source electrode, and the occurrence of flicker can be greatly suppressed.
[0092]
Further, in this embodiment, in particular, in each thin film transistor TFT arranged along the gate signal line GL, the capacitance Cgs between the gate electrode (gate signal line GL) and the source electrode SD1 is equal to that of the gate signal line. It is configured to be small on the input terminal side and large on the termination side.
[0093]
9A shows a thin film transistor on the input terminal side of the gate signal line GL, and FIG. 9B shows a thin film transistor on the terminal side of the gate signal line GL.
[0094]
As is clear from FIGS. 9A and 9B, the semiconductor layer AS on the source electrode SD1 side of the thin film transistor TFT shown in FIG. 9B is formed larger than that shown in FIG. 9A. As a result (the excess is indicated by symbol I), the capacitance Cgs between the gate signal line GL and the source electrode SD1 of the thin film transistor TFT on the termination side is increased.
[0095]
That is, the area in which the semiconductor layer AS in the vicinity of the source electrode of the thin film transistor on the terminal side overlaps with the gate signal line GL is larger than the area in which the semiconductor layer AS in the vicinity of the source electrode of the thin film transistor on the input terminal side overlaps with the gate signal line GL. Yes.
[0096]
In this case, the capacitance Cgs of each thin film transistor TFT from the input terminal side to the termination side of the gate signal line GL may be configured to increase sequentially, or a plurality of adjacent thin film transistors may be sequentially grouped to form these groups. You may comprise so that it may become large sequentially every time.
[0097]
With this configuration, the shift of the potential of the pixel electrode ITO1 in the positive direction due to the waveform distortion of the scanning signal to the gate signal line GL is shifted in the negative direction of the potential of the pixel electrode ITO1 depending on the capacitance Cgs of the jump voltage. The voltage applied to the liquid crystal on the input terminal side and the terminal side of the gate signal line GL is equalized by canceling out the shift to.
For this reason, flickering of the screen due to luminance change can be suppressed.
[0098]
In general, the writing time for one line in the liquid crystal panel is completed within a time determined by the width of the TFT on signal output from the scanning signal line driving circuit unit 104.
[0099]
However, the TFT on signal is a rectangular pulse whose width is uniquely determined by the horizontal scanning frequency. Generally, a rectangular pulse has a large amount of current change (di / dt) at its rise and fall. It is easily affected by the time constant in the path, and the actual rising and falling waveform is a curved waveform along the time constant curve (hereinafter, this curved waveform is called “waveform distortion” and has a large curvature) In addition, the waveform distortion increases as it approaches the end of the signal path, and therefore the potential drop component ΔV of the pixel voltage PXV becomes the end of the scanning signal line. As a result, the pixel voltage (source electrode potential) on the termination side becomes higher than the input terminal side of the scanning signal line.
[0100]
Such a problem is particularly noticeable when the number of pixels is increased or when the screen size (especially the size in the scanning line direction) is increased.
[0101]
This is because the distributed capacity (Cgs, Cadd, Cgd, etc.) in FIG. 15 increases in proportion to the number of pixels and the screen size.
[0102]
The above problem will be specifically described below.
FIG. 17 is an equivalent circuit for one line of the liquid crystal display panel. In this figure, GTM is an input terminal for a TFT on signal (ie, a terminal connected to the output of the scanning signal line driving circuit 104 in FIG. 2), and this terminal GTM is connected to the scanning signal line driving circuit 104 and the liquid crystal display panel. The wiring 11 is connected to the gate signal line GL of the liquid crystal display panel. R11 and C11 represent a resistance component and a capacitance component of the wiring 11, respectively. The gate signal line GL is equivalent to a pixel unit, and R12 and C12 of each pixel respectively represent a resistance component and a capacitance component (also referred to as distributed capacitance, corresponding to Cgs + Cadd + Cgd) of each pixel.
[0103]
Now, paying attention to the two points a and c of the gate signal line GL, the waveform distortion of the TFT on signal at each point is considered. a is the point closest to the terminal GTM. The TFT on signal at this point a is referred to as VGa for convenience. c is a point farthest from the terminal GTM (in other words, at the end of the scanning signal line). The TFT on signal at this point c is VGc for convenience.
[0104]
18A is a terminal side, FIG. 18B is a central portion, and FIG. 18C is a diagram showing a driving waveform of a TFT on the terminal side. Both signals VGa and VGc are rectangular pulses that change from rising to falling in a predetermined writing period Tx allocated within one horizontal scanning period. The waveform distortion of the signal VGa is very small caused by the time constants of R11 and C11. The waveform distortion of the signal VGc is further increased by adding R12 and C12 of the number of pixels of one line to the time constant of R11 and C11. It is a big thing caused by the time constant included. For this reason, the fall tfr of the signal VGc is considerably delayed compared to the fall tfl of the signal VGa. The degree of delay becomes more prominent as the number of pixels increases and the screen size increases. This is because the above-described distributed capacity (that is, C12) increases.
[0105]
That is, a relationship of tfr> tfl is established, and the difference mainly depends on the size of the distributed capacity.
[0106]
Therefore, from the relationship of Equation 1 described above, the terminal-side pixel voltage drop component ΔVl is larger than the terminal-side pixel voltage drop component ΔVr.
[0107]
Conventionally, it has been common knowledge that the parasitic capacitances (Cgs, Cds1, Cds2) and storage capacitance (Cadd) of a unit pixel are designed to be constant everywhere in the display area in order to equalize the driving conditions of the pixel electrode. It was. Therefore, in the prior art, the optimum common electrode voltage Vcom described above is actually different between the terminal side and the terminal side of the gate signal line GL.
[0108]
However, in the past, the size of the display screen was smaller than 10 type (length 15 cm, width 21 cm) and the gate signal line GL was not long (21 cm or less), so between the pixel on the input terminal side and the pixel on the termination side, The difference in the potential drop component ΔV of the pixel electrode is negligibly small and the drive margin of the liquid crystal display device (especially the margin of the optimum common electrode voltage Vcom) has a margin, so that the problem to be solved by the present invention can be recognized. I could not do it.
[0109]
Therefore, in the conventional technique, when the number of pixels in one line is large, or when the length of the display area in the gate signal line direction becomes long (at least in a liquid crystal display device having a gate signal line length of 27 cm or more), It has become impossible to optimize the voltage applied to the common electrode for all the pixels.
[0110]
In order to solve the above problems, in the above-described embodiments, the capacitance Cgs is made different by making the size of the semiconductor layer AS on the source electrode SD1 side of the thin film transistor TFT different.
[0111]
In the above-described embodiment, since the size of the semiconductor layer AS is changed in a portion other than the channel formation region (region between the source electrode SD1 and the drain electrode SD2) of the thin film transistor TFT, the gate-source capacitance Cgs is input. By changing between the terminal side and the terminal side, the TFT size (specifically, channel length l and channel width w) does not change, and the design of the liquid crystal display device is easy.
[0112]
Further, as is apparent from Equation 1, the method of adjusting the potential drop component ΔV of the pixel electrode so as to reduce the difference between the pixels is a method of adjusting the gate-source capacitance Cgs as in the above-described embodiment. The method of adjusting the storage capacitor element Cadd, the method of adjusting the liquid crystal capacitor Cpix (specifically, the area of the pixel electrode ITO1 or the distance between the pixel electrode ITO1 and the common electrode COM (not shown)), A method of adjusting the inter-drain capacitance Cds1 or a method of adjusting the parasitic capacitance Cds2 between the pixel electrode ITO1 and the drain signal line DL adjacent thereto may be used.
[0113]
However, in the above-described embodiment in which the gate-source capacitance Cgs is adjusted, as is clear from the fact that the numerator of Formula 1 is composed of only the gate-source capacitance Cgs, the gate-source capacitance Cgs is small. With the amount of change, the potential drop component ΔV of the pixel electrode can be adjusted with a wide dynamic range. Therefore, in the above-described embodiment, the space for changing the gate-source capacitance Cgs is small, so that the aperture ratio of the pixel can be increased.
[0114]
Further, if the gate-source capacitance Cgs, the holding capacitance element Cadd, the liquid crystal capacitance Cpix, the source-drain capacitance Cds1, and the pixel electrode drain signal line capacitance Cds2 are adjusted in combination, the potential lowering component of the pixel electrode can be achieved with a wider dynamic range. ΔV can be adjusted.
[0115]
When the potential drop component ΔV of the pixel electrode is adjusted by the storage capacitor element Cadd, the liquid crystal capacitor Cpix, the source / drain capacitor Cds1 or the pixel electrode drain signal line capacitor Cds2, these capacitors constitute the denominator of Equation 1. As is clear from the above, the pixel (a) on the input terminal side in which the capacitance is reduced in the pixel (c) on the terminal side where the distortion of the scanning signal driving waveform is large and the distortion in the scanning signal driving waveform is small. And increase their capacity.
[0116]
Further, the method of adjusting the gate-source capacitance Cgs is not limited to adjusting the overlapping area of the semiconductor layer AS with the gate signal line GL. As shown in FIG. 10, the source electrode SD1 with respect to the gate signal line GL The gate signal line GL in the overlap region is formed by extending a projection GLP as shown in the figure, and the area of the projection GLP is small on the input terminal side of the gate signal line GL and large on the termination side. However, the same effect can be obtained.
[0117]
Furthermore, as shown in FIG. 11, it goes without saying that the overlap region of the source electrode SD1 with respect to the gate signal line GL may be made different by changing the length in the width direction of the gate signal line GL.
[0118]
That is, each pixel region arranged along the gate signal line GL is grouped into a plurality of adjacent pixel regions, and the gate signal line GL of each grouped pixel region is connected from the input terminal side to the termination side. The width is gradually widened (the width of the source electrode SD1 on the side connected to the pixel electrode ITO1 is widened).
[0119]
In the case of a liquid crystal display device adopting the storage capacitor method for the storage capacitor Cadd shown in FIGS. 12, 13, and 14, the area where the pixel electrode ITO1 and the capacitor line CL overlap is changed from the input terminal side to the termination side. The potential decreasing component ΔV of the pixel electrode can also be adjusted by gradually increasing the width. In the embodiment shown in FIGS. 13 and 14, the potential lowering component ΔV is adjusted by adjusting the width W3 of the capacitance line CL.
[0120]
The storage capacitor type liquid crystal display device has a feature that the influence of the waveform distortion of the scanning signal VG can be reduced because the distribution capacity of the gate signal line GL is small. However, even in the storage capacitor type liquid crystal display device, the gate-source capacitance Cgs and the holding capacitor Cadd are adjusted to reduce the difference between the potential drop component ΔV between the input terminal side and the termination side as in the above-described embodiment. Since the influence of the waveform distortion of the scanning signal VG can be completely eliminated, a liquid crystal display device having the largest display screen can be realized.
[0121]
Further, the distortion of the signal waveform input to the gate signal line GL monotonously increases from the input end to the end.
[0122]
The part b in FIG. 17 shows the central part of the gate signal line (scanning signal line) GL, and the TFT drive waveform of that part is shown in FIG. FIG. 18A shows the TFT drive waveform on the input terminal side shown in FIG. 17A, and FIG. 18C shows the TFT drive waveform on the termination side shown in c of FIG. As is clear from comparison between FIGS. 18A, 18B, and 18C, the falling time tf of the scanning signal VGb in the central portion is equal to the falling time tfl on the input terminal side and the rising time on the termination side. It is during the down time tfr. That is, there is a relationship of tfl <tf <tfr. Therefore, in the conventional liquid crystal display device designed so that the parasitic capacitance is the same for all pixels, the potential drop component ΔV of the pixel electrode in the central portion is the potential drop component ΔVl on the input terminal side and the potential on the output terminal side. It is between the lowering components ΔVr. That is, there is a relationship of ΔVl> ΔV> ΔVr.
[0123]
Therefore, the amount of shift in the positive direction of the voltage of the pixel electrode ITO corresponding to the central portion of the gate signal line GL is larger than that of the pixel electrode ITO corresponding to the input end of the gate signal line GL, and the end of the gate signal line GL Less than the corresponding pixel electrode ITO.
[0124]
Therefore, the capacitance Cgs between the gate electrode of the thin film transistor TFT connected to the central portion of the gate signal line GL and the source electrode SD1 is larger than the capacitance Cgs of the thin film transistor TFT connected to the input terminal of the gate signal line GL, By making it smaller than the capacitance Cgs of the thin film transistor TFT connected to the terminal of the line GL, the leakage component of the gate signal jumping into the pixel electrode ITO at the input end and the terminal and the pixel electrode ITO at the center can be made uniform. The common electrode voltage does not differ between the input end and terminal pixels and the central pixel, and flicker does not occur in the central portion of the display area.
[0125]
Note that here, the pixel electrode ITO1 at the input end and the terminal end of the gate signal line is discussed in terms of the pixel electrode ITO1 that contributes to display, such as the pixel electrode ITO1 shielded by the light shielding film and the pixel electrode of an incomplete pixel. Needless to say, the pixel electrode ITO1 that does not contribute to the display is considered to be excluded because it is not related to flicker.
[0126]
However, the pixel C corresponding to the pixel electrode ITO1 that is shielded from light by the pixel electrode ITO1 at the input end and the terminal end of the gate signal line also has the capacitance Cgs of the thin film transistor TFT on the end side rather than the capacitance Cgs of the thin film transistor TFT on the input end side. By adopting a large configuration, a direct current component is not added to the liquid crystal, and the effect of improving the life of the liquid crystal can be achieved.
[0127]
In this embodiment, there is provided a liquid crystal display device provided with a countermeasure for preventing flicker due to waveform distortion of a scanning signal input to the gate signal line GL and a countermeasure for preventing flicker due to positional deviation of the source electrode SD1 due to distortion of the optical system of the exposure apparatus. Although described, it goes without saying that any one of these preventive measures may be taken.
[0128]
However, the liquid crystal display device in which the countermeasure for preventing flicker due to the positional deviation of the source electrode SD1 is applied to the flicker prevention countermeasure due to the waveform distortion of the scanning signal input to the gate signal line GL, thereby reducing the potential drop component ΔV of the pixel electrode. Adjustment can be performed with high accuracy, and even when the display area is expanded to the maximum level, a drive margin (particularly, a margin for the common electrode voltage Vcom) of the liquid crystal display panel can be sufficiently secured.
[0129]
<Capacity correction method>
Next, an embodiment of a method for correcting the capacitance of each pixel and making the capacitance of each pixel uniform along the extending direction of the scanning signal line will be described with reference to FIG.
[0130]
FIG. 5A is a graph showing a capacitance correction value (in this case, Cgs as an example) when the horizontal direction is the scanning signal line extending direction.
[0131]
Here, this graph is, for example, data from a liquid crystal display device (sample) in which each pixel is formed as a uniform pattern, but it is not necessarily limited to a liquid crystal display device having pixels having a uniform pattern. There is no. This is because the capacity may be further corrected using the liquid crystal display device whose capacity is corrected as a sample. A method for obtaining this graph will be described in detail later.
[0132]
FIG. 5B shows the display area (pixel aggregate) AR of the liquid crystal display device to be subjected to capacitance correction in association with the graph.
[0133]
First, in FIG. 4A, the correction values are divided at regular intervals, for example. In this embodiment, the correction value is divided into six equal parts. However, the number of partitions is not necessarily limited to this value. However, the number of sections is small when the characteristic curve of FIG. 39A is gentle, and when it is abrupt, it is sufficient to prevent the occurrence of flicker on the display area surface.
[0134]
Then, the display area is divided into six areas from the A area to the F area in accordance with the scanning signal line extending method according to the section of the correction value. Here, for example, taking the A region as an example, all the A regions are in the extending direction of the video signal lines orthogonal to the scanning signal lines. This is based on the reason that each pixel formed in the extending direction of the video signal line has substantially the same condition in terms of capacitance.
[0135]
In each section of the scanning signal line extending method, the correction amount for the A region of the B region, the correction amount for the B region of the C region, the correction amount for the C region of the D region, the correction amount for the D region of the E region, The correction amounts for the F region and the E region are all the same. This is because each of these areas is an area obtained by dividing the correction values at equal intervals and corresponding to the sections.
[0136]
FIG. 40 shows an example in which the patterns of the source electrode SD1, the semiconductor layer AS, and the gate insulating film GI of the thin film transistor TFT are changed in each of these regions. 40 is a diagram corresponding to FIG. 1, and is not limited thereto. Needless to say, the present invention can be applied to each of the above-described embodiments and each of the embodiments described later.
[0137]
In the figure, for example, (a) shows the pattern of the thin film transistor TFT in the B region, (b) shows the pattern of the thin film transistor TFT in the C region, and (c) shows the pattern of the E region.
[0138]
In FIG. 4A, the source electrode SD1, the semiconductor layer AS, and the gate insulating film GI of the thin film transistor TFT each have a protrusion PR protruding outward, and the area corresponding to the protrusion PR is increased. ing.
[0139]
Here, the protrusion PS corresponds to a minimum unit pattern (a pattern determined arbitrarily by a designer, not a reference minimum unit) used in capacity correction according to the present embodiment. And serves as a reference pattern for correcting the capacitance of each thin film transistor TFT in the C region, D region, E region, and F region.
[0140]
That is, in FIG. 8B, the source electrode SD1, the semiconductor layer AS, and the gate insulating film GI of the thin film transistor TFT are respectively formed with protrusions PR protruding outward, as in FIG. However, the area of the protrusion PR is doubled as compared with FIG. In other words, each of the source electrode SD1, the semiconductor layer AS, and the gate insulating film GI of the thin film transistor TFT is provided with two pieces having the same area as the protrusion PR shown in FIG.
[0141]
In FIG. 8C, the source electrode SD1, the semiconductor layer AS, and the gate insulating film GI of the thin film transistor TFT each have an area PR of the protrusion protruding outward, which is four times that of FIG. It has become.
[0142]
That is, as is clear from this, one projection PR (minimum pattern) for each of the B region, the C region, the D region, the E region, and the F region with reference to each pattern shown in FIG. Is in an increasing relationship.
[0143]
This means that when designing and creating a photomask by changing the pattern of each pixel in order to correct the capacity of each pixel, the change takes into account the area of each pattern (in other words, a significant change in the pattern shape). Needless to say, this method has a great effect of avoiding the complicated work.
[0144]
In the above-described embodiment, the capacity correction values are divided at equal intervals when divided, but needless to say, they need not be equal intervals. For example, depending on the state of the characteristic curve, it may be appropriate to avoid a flicker that occurs in the display area, for example, by setting a certain segment to be a multiple of the other segment.
[0145]
In the above-described embodiment, the photomask is designed and created when changing the pattern of each pixel. However, the present invention is not limited to this, and it goes without saying that the pattern of the pixel may be changed by movement (concept including rotation) of the exposure pattern (photomask) with respect to the light source.
[0146]
For example, FIG. 41A shows a pattern grid diagram of a gate and a source of a thin film transistor TFT for forming Cgs. Normally, as shown in the figure, the gate and source pattern grids coincide with each other, so that the same pixel is formed in an arbitrary portion unless the pixel pattern is changed by a photomask.
[0147]
Here, in the photolithography process at the time of pattern formation, the same effect can be obtained by forming the source pattern grid with an offset from the gate pattern grid, as shown in FIG.
[0148]
In this case, each pattern changes almost continuously in the adjacent region, and it is not possible to clearly separate the region. However, in any part, the Cgs of the pixel on the input side of the scanning signal line is Cgs1, and the pixel on the main side of the scanning signal line is When Cgs is Cgs2, a relationship of Cgs2> cgs1 can be obtained.
[0149]
In addition, when a single photomask is formed for a plurality of adjacent pixels and this photomask is selectively exposed while being so-called step-and-repeat within the display region, the photomask is applied to each of the regions A to F. It goes without saying that the photomask may be appropriately moved (a concept including rotation) with respect to the light source.
[0150]
Further, in the above-described embodiment, the extension distance of the scanning signal line is partitioned corresponding to each section that divides the correction value. However, the present invention is not limited to this. Needless to say, for example, as shown in FIG. 42, the correction value may be defined corresponding to each segment defining the extension distance of the scanning signal line. .
[0151]
In this case, it is effective when the area that needs to be corrected is divided from the display area surface.
[0152]
Further, in the above-described embodiment, the correction of Cgs is described. However, in the case of Cadd, Csd, etc., the characteristic (capacity correction amount with respect to the extension distance of the scanning signal line) as shown in FIG. 43 can be obtained. Based on this characteristic, the same process as described above is performed. Then, the capacity may be corrected.
[0153]
Here, an embodiment of a method for obtaining a graph (FIG. 39A) showing the capacitance correction value of Cgs when the extending direction of the scanning signal line is taken on the horizontal axis will be described.
[0154]
(1) The optimum Vcom in the display area is measured by optical measurement.
[0155]
First, in order to measure the optimum Vcom, a pattern in which a halftone of a specific gradation and black are spatially decomposed is displayed. The spatially decomposed pattern includes a checkered pattern or a stripe line as shown in the figure.
[0156]
In these patterns, luminance smoothing due to inversion driving is cancelled, so that luminance changes or flickers when Vcom changes.
[0157]
45 (b) and 45 (b ') show that the brightness change occurs due to the change in Vcom with respect to (a) and (a').
[0158]
For this reason, by changing Vcom and measuring the time variation of luminance (with a spectroanalyzer or the like), an optimum Vcom is obtained as shown in FIG. 46, and this is measured at each point on the display area surface.
[0159]
(2) Vcom fluctuation due to finish
Then, the pattern of the thin film transistor TFT at each point in the plane measured in the step (1) is confirmed.
[0160]
First, the area of the pattern constituting Cgs, Cadd, and Cpx is calculated from the pattern.
[0161]
Then, the capacitance is obtained from the relative dielectric constant of the dielectric film. Further, the jump voltage ΔVs at each point is calculated from this capacity.
[0162]
(3) Vcom correction
The Vcom distribution obtained in (1) and the jump voltage ΔVs distribution obtained in (2) are compared (see FIG. 47), and the jump voltage ΔVs distribution is removed from the Vcom in-plane distribution (see FIG. 48).
[0163]
Thus, the Vcom in-plane distribution is obtained (see FIG. 49). Thereafter, the calculated Vcom distribution is flattened to obtain the jump voltage ΔVs distribution (see FIG. 50), and from this, the Cgs distribution is obtained (see FIG. 51).
[0164]
Needless to say, the characteristics in the case of Cadd and Csd can be calculated in the same manner.
[0165]
<< Method for Manufacturing Transparent Substrate SUB1 >>
Next, a manufacturing method on the first transparent insulating substrate (thin film transistor substrate) SUB1 side of the liquid crystal display device shown in FIG. 3 will be described with reference to FIGS. In the figure, the center letter is an abbreviation of the process name, the processing flow as viewed from the cross-sectional shape of the thin film transistor TFT (IV-IV cutting line) on the left side and the holding capacitor Cadd (VI-VI cutting line) on the right side. Indicates. Except for Steps B and D, Steps A to G are divided according to each photo (photo) process, and each cut view of each process has been processed after the photo process and the photoresist is removed. Is shown. In this description, the photographic process is a series of operations from application of a photoresist to selective exposure using a mask and development thereof, and repetitive description is avoided. The description will be made according to the following divided processes.
[0166]
Process A, FIG.
After silicon oxide films SIO are provided on both surfaces of the first transparent insulating substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. This SIO film is formed to alleviate the surface unevenness of the transparent insulating film SUB1, but this step can be omitted when the unevenness is small. A first conductive film g1 made of Al-Ta, Al-Ti-Ta, Al-Pd, or the like having a thickness of 2800 mm is provided by sputtering. After the photo treatment, the first conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, and glacial acetic acid.
[0167]
Process B, FIG.
After direct drawing of the resist (after the formation of the anodic oxidation pattern described above), a solution prepared by diluting 3% tartaric acid to pH 6.25 ± 0.05 with ammonia was diluted 1: 9 with an ethylene glycol solution into an anodic oxidation solution. Substrate SUB1 is immersed and the formation current density is 0.5 mA / cm.²(Constant current formation). Next, anodic oxidation (anodization) is performed until the formation voltage of 125 V necessary for obtaining a predetermined Al2O3 film thickness is reached. Then, it is desirable to hold for several tens of minutes in this state (constant voltage formation). This is important for obtaining a uniform Al 2 O 3 film. As a result, the conductive film g1 is anodized, and an anodic oxide film AOF having a thickness of 1800 mm is formed on the scanning signal line (gate line) GL and on the side surface in a self-aligned manner, and a part of the gate insulating film of the thin film transistor TFT is formed. Become.
[0168]
Process C, FIG. 19
A conductive film ITO made of an ITO film having a thickness of 1400 mm is provided by sputtering. After the photo treatment, the conductive film ITO is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming one electrode of the storage capacitor Cadd and the transparent pixel electrode ITO1.
[0169]
Process D, FIG.
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a silicon nitride film having a thickness of 2000 mm, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form an i-type amorphous Si film having a thickness of 2000 mm. After providing the film, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to provide an N + type amorphous Si film d0 having a thickness of 300 mm. This film formation is performed continuously by changing the reaction chamber in the same CVD apparatus.
[0170]
Process E, FIG. 20
After the photo treatment, the N + type amorphous Si film d0 and the i type amorphous Si film AS are etched using SF6 and BC1 as dry etching gases. Subsequently, the Si nitride film GI is etched using SF6. Of course, the N + type amorphous Si film d0, the i type amorphous Si film AS, and the Si nitride film GI may be continuously etched with SF6 gas.
[0171]
Thus, by continuously etching the three-layer CVD film with a gas containing SF6 as a main component, the sidewalls of the i-type amorphous Si film AS and the Si nitride film GI can be processed into a tapered shape. Due to the tapered shape, the probability of disconnection is significantly reduced even when the source electrode SD1 is formed thereon. The taper angle of the N + type amorphous Si film d0 is close to 90 degrees, but since the thickness is as thin as 300 mm, the probability of disconnection at this step is very small. Accordingly, the planar patterns of the N + type amorphous Si film d0, the i type amorphous Si film AS, and the Si nitride film GI are not strictly the same pattern, and the cross section has a forward tapered shape. The Si film d0, i-type amorphous Si film AS, and Si nitride film GI have large patterns in this order.
[0172]
Process F, FIG.
A first conductive film d1 made of Cr having a thickness of 600 mm is provided by sputtering. After the photo treatment, the first conductive film d1 is etched with a second ceric ammonium nitrate solution to form the drain signal line DL, the source electrode SD1, and the drain electrode SD2.
[0173]
Here, in this embodiment, as shown in step E, the N + type amorphous Si film d0, the i type amorphous Si film AS, and the nitrided Si film GI are forward tapered. Even if it is formed by only one conductive film d1, the source electrode SD1 does not break.
[0174]
Next, SF6 and BC1 are introduced into a dry etching apparatus to etch the N + type amorphous Si film d0, thereby selectively removing the N + type semiconductor film d0 between the source and the drain.
[0175]
Process G, FIG.
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a Si nitride film having a thickness of 0.6 μm. After the photo treatment, the protective film PSV1 is formed by etching using SF6 as a dry etching gas. As the protective film, not only a SiN film formed by CVD but also a film using an organic material can be used.
[0176]
《Photomask design》
The pattern of each layer of the first substrate SUB1 is formed by photolithography.
FIG. 22A shows an example of a pattern forming method.
[0177]
MSK1 is a photomask on which a pattern PAT for transfer to a substrate is formed. There is one MSK1, and all the patterns of one layer of the liquid crystal display panel are formed.
[0178]
SUB1 is a substrate having a main surface coated with a photoresist. In the example of FIG. 22A, an example in which one liquid crystal display panel pattern is formed on one substrate SUB1 is shown. However, a plurality of liquid crystal display panel patterns may be formed on one mother glass substrate.
[0179]
An alignment mark ALM is provided on the photomask, and alignment between the layers of the first substrate SUB1 is performed by aligning the alignment mark ALM ′ provided on the substrate with the alignment mark ALM of the photomask.
[0180]
Light such as ultraviolet rays generated by the light source LIT such as a mercury lamp is processed into a uniform surface light source by the lens optical system LEN and sent to the reflecting mirror MIR.
[0181]
The light sent to the reflecting mirror MIR is reflected toward the slit SLT, and the light passing through the slit SLT becomes linear light and illuminates the photomask MSK1.
[0182]
The linear light transmitted through the photomask MSK1 hits the substrate SUB1 and sensitizes the photoresist.
[0183]
At this time, the pattern PAT of the photomask MSK1 is transferred onto the substrate SUB1 only in the portion e which is exposed to light.
[0184]
The pattern PAT of the photomask MSK1 is transferred as the pattern PAT ′ of the substrate SUB1 by moving the slit SLT and the reflecting mirror MIR relative to the substrate and the photomask in the direction shown by the arrow in FIG. .
[0185]
FIG. 22B is used in the method shown in FIG. An example of the pattern PAT of the photomask MSK1 is shown.
[0186]
Describing based on the embodiment shown in FIG. 9, the pattern of the semiconductor layer AS is formed in the photomask MSK1 shown in FIG.
[0187]
If the extending direction of the gate signal line GL is x, a in FIG. 22B indicates the pattern of the semiconductor layer AS on the input terminal side, and b indicates the pattern of the semiconductor layer AS on the termination side. Part I in FIG. 22B is a pattern for adjusting the gate-source capacitance Cgs described above.
[0188]
Method of forming a desired pattern (for example, semiconductor layer AS) of substrate SUB1 by forming an entire pattern of one layer of a liquid crystal display panel on one photomask MSK1 shown in FIGS. 22 (a) and 22 (b) Since the pattern on the input terminal side and the terminal side can be formed under the same exposure conditions, the pattern I for adjusting the potential lowering component ΔV of the pixel electrode can be formed with high accuracy.
[0189]
Therefore, since the potential drop component ΔV can be controlled with high accuracy, the margin when driving the liquid crystal display panel (particularly the margin of the common electrode voltage Vcom) is improved.
[0190]
As shown in FIG. 22A, the pattern PAT ′ on the substrate SUB1 is exposed by moving the reflecting mirror MIR and the slit SLT. The pattern PAT ′ may be distorted.
[0191]
However, the width W0 orthogonal to the extending direction of the source electrode SD1 shown in FIGS. 1, 7A to 7D and 8 is formed to be smaller than the channel width W. As a result, the variation in the gate-source capacitance Cgs due to misalignment between the source electrode SD1 and the gate signal line GL is reduced, so that the influence of distortion in the exposure process can be reduced.
[0192]
FIG. 23A shows another example of a method for forming a pattern on the first substrate SUB1.
[0193]
The difference from FIG. 22A is that the pattern PAT ′ on the substrate SUB1 is divided into a plurality of block patterns PATi, PATii, PATiii, and PATiv, and one photomask MSKi, MSKii, MSKiii, and MSKiv is used for each block. It is.
[0194]
FIG. 23B shows an example of patterns of a plurality of photomasks MSKi, MSKii, MSKiii, and MSKiv used in the method shown in FIG.
[0195]
Referring to the embodiment shown in FIG. 9, FIG. 23B shows an example of a photomask for the semiconductor layer AS. If the extending direction of the gate signal line GL is x, the photomasks MSKi and MSKiv indicate the photomasks on the input terminal side, and the photomasks MSKii and MSKiii indicate the photomasks on the end side. In FIG. 23B, a represents the pattern of the semiconductor layer AS on the input terminal side, and b represents the pattern of the semiconductor layer AS on the termination side. Part I in FIG. 23B is a pattern for adjusting the gate-source capacitance Cgs described above.
[0196]
Other points that are not particularly described are the same as those in the embodiment shown in FIGS. 22 (a) and 22 (b).
[0197]
According to the embodiment shown in FIG. 23 (a), one layer pattern PAT 'of one liquid crystal display device is formed by a plurality of photomasks MSKi, MSKii, MSKiii, MSKiv, so that a liquid crystal display device having a large display screen can be obtained. I can make it.
[0198]
However, in the embodiment shown in FIG. 23A, since the pattern I for adjusting the potential lowering component ΔV needs to be formed with different photomasks on the input terminal side and the terminal side, the potential lowering component ΔV is adjusted with high accuracy. Difficult to do.
[0199]
Further, in the embodiment shown in FIG. 23A, the boundary region between the block patterns PATi ′, PATii ′, PATiii ′, and PATiv ′ of the substrate SUB1 is exposed multiple times, so that the pattern is different from the other. Thinner than the part.
[0200]
Therefore, it is necessary to provide a pattern I for adjusting the potential lowering component ΔV in a portion that avoids a portion that is exposed multiple times.
[0201]
On the other hand, in the embodiment shown in FIG. 22A, the entire pattern PAT ′ of one layer of the liquid crystal display device is formed by one photomask MSK1, so that there is no boundary region and the pattern for adjusting the potential lowering component ΔV. There are few restrictions for providing I.
[0202]
However, in the case of manufacturing a liquid crystal display device having the largest display area, the embodiment shown in FIG. 23A is more suitable if the accuracy of the pattern I for adjusting the potential lowering component ΔV is not considered. .
[0203]
In the pattern formation method shown in FIGS. 22A, 22B, 23A, and 23B described above, the pattern I for adjusting the potential lowering component ΔV is provided in the semiconductor layer AS. However, the pattern I for adjusting the potential lowering component ΔV may be provided in other layers.
[0204]
For example, in the embodiments shown in FIGS. 10 and 11, the photomask in the step of forming the gate signal line GL (first photo) is shown in FIG. 22A, FIG. 22B or FIG. The pattern forming method shown in FIG. 23 (b) may be used. In addition, the pattern forming method shown in FIGS. 22A, 22B, 23A, and 23B is used for the photomask used in the step of forming the source electrode SD1 (fourth photo). Also good.
[0205]
<< When the gate signal line GL is driven at both ends >>
FIG. 24 is an equivalent circuit of an example of a liquid crystal display device in which scanning signal line driving circuit units 104 are provided at both left and right ends of the gate signal line GL in order to reduce waveform distortion of the scanning signal line driving waveform VG. In the liquid crystal display device having the configuration shown in FIG. 24, the termination of the gate signal line GL does not exist.
[0206]
However, even in the liquid crystal display device having the configuration shown in FIG. 24, the waveform distortion of the scanning signal VG of the central pixel B far from the two scanning signal line driving circuit units 104 is closer to the two scanning signal line driving circuit units 104. It is larger than the waveform distortion of the scanning signal VG of the pixels A and C.
[0207]
Therefore, even in the liquid crystal display device driven on both sides shown in FIG. 24, the gate-source capacitance Cgs of the pixel B far from the input terminal is larger than the gate-source capacitance Cgs of the pixels A and C closer to the input terminal. By increasing it, it is possible to reduce the difference in the potential drop component ΔV of the pixel electrode due to waveform distortion of the scanning signal VG.
[0208]
A specific method for adjusting the gate-source capacitance Cgs is the same as the embodiment shown in FIGS.
[0209]
In the double-sided liquid crystal display device shown in FIG. 24, the method of reducing the difference in the potential drop component ΔV of the pixel electrode is not limited to adjusting the gate-source capacitance Cgs, but the holding capacitance Cadd and the liquid crystal capacitance Cpix. The source-drain capacitance Cds1 or the pixel electrode drain signal line capacitance Cds2 may be adjusted.
[0210]
In this embodiment, the thin film transistor TFT having an inverted stagger structure formed in the order of gate electrode formation, gate insulating film formation, semiconductor layer formation, and source / drain electrode formation is shown.
[0211]
However, the present invention is not limited to a liquid crystal display device using a thin film transistor TFT having an inverted stagger structure, but a liquid crystal display device using a thin film transistor TFT having a normal stagger structure in which a gate electrode is formed on a semiconductor layer via a gate insulating film. The present invention may be applied to.
[0212]
Embodiment 2
In the present invention, a so-called vertical electric field type liquid crystal display device is described as an example. However, in the case of a lateral electric field method (In Plain Switching method) in which a pair of electrodes facing each other is provided on the liquid crystal side surface of one transparent substrate and an electric field is generated between these electrodes in parallel with the transparent substrate. Since the situation is completely the same, the present invention can also be applied to this lateral electric field type liquid crystal display device.
[0213]
FIG. 25 is a plan view showing one pixel of a horizontal electric field type active matrix color liquid crystal display device to which the present invention is applied and its periphery.
[0214]
FIG. 26 is a view showing a cross section taken along line 3-3 of FIG. As shown in FIGS. 25 and 26, the thin film transistor TFT, the storage capacitor Cstg, the pixel electrode PX, and the counter electrode COM2 are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC, and the upper transparent glass substrate SUB2 side is formed. Are formed with a color filter FIL and a black matrix pattern BM for light shielding.
[0215]
In addition, alignment films ORI1 and ORI2 for controlling the initial alignment of the liquid crystal are provided on the inner surfaces (liquid crystal LC side) of the transparent glass substrates SUB1 and SUB2, and the outer sides of the transparent glass substrates SUB1 and SUB2. Is provided with a polarizing plate in which the polarization axes are arranged orthogonally (crossed Nicols arrangement).
[0216]
As shown in FIG. 25, each pixel includes a gate signal line (scanning signal line or horizontal signal line) GL, a counter voltage signal line (common electrode wiring) COM1, and two adjacent drain signal lines (video signal line or video signal line). The vertical signal line (DL) is arranged in a region intersecting with DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode COM2. The gate signal line GL and the counter voltage signal line COM1 extend in the left-right direction in the figure, and a plurality of gate signal lines GL and counter voltage signal lines COM1 are arranged in the up-down direction. The drain signal lines DL extend in the vertical direction, and a plurality of drain signal lines DL are arranged in the horizontal direction. The pixel electrode PX is connected to the thin film transistor TFT, and the counter electrode COM2 is integrated with the counter voltage signal line COM1.
[0217]
Two pixels that are vertically adjacent to each other along the drain signal line DL have a configuration in which the planar configurations overlap when bent along the A line in FIG. This is because the common voltage signal line COM1 is shared by two pixels vertically adjacent to each other along the drain signal line DL, and the electrode width of the common voltage signal line COM1 is increased, thereby reducing the resistance of the common voltage signal line COM1. Because. Thereby, it becomes easy to sufficiently supply the counter voltage from the external circuit to the counter electrode COM2 of each pixel in the left-right direction.
[0218]
The pixel electrode PX and the counter electrode COM2 face each other, and the optical state of the liquid crystal LC is controlled by the electric field between each pixel electrode PX and the counter electrode COM2, thereby controlling the display. The pixel electrode PX and the counter electrode COM2 are formed in a comb-teeth shape, and are each an elongated electrode in the vertical direction of the figure.
[0219]
The gate width of the gate signal line GL is set so as to satisfy a resistance value sufficient to apply a scanning voltage to the gate electrode GT of the pixel on the end side. Further, the counter voltage signal line COM1 also sets the electrode width so as to satisfy a resistance value sufficient to apply the counter voltage to the counter electrode COM2 of the pixel on the terminal side.
[0220]
In FIG. 25, a portion indicated by reference numeral I is a portion for adjusting the potential lowering component ΔV of the pixel electrode. The portion indicated by the symbol I is formed integrally with the pixel electrode Px, and forms a gate-source capacitance Cgs by overlapping with the gate signal line GL via the insulating film GI.
[0221]
Therefore, in the embodiment shown in FIG. 25, the area where the gate-source capacitance adjustment pattern I overlaps with the gate signal line GL is reduced at the pixels closer to the input terminal and larger at the pixels farther from the input terminal. As a result, the difference between the pixels of the potential lowering component ΔV of the pixel electrode is reduced.
[0222]
A horizontal electric field type liquid crystal display device has a wide viewing angle characteristic. Therefore, by adopting the horizontal electric field method for a liquid crystal display device having a large display area, the conventional problem that a part of the screen cannot be seen due to narrow viewing angle characteristics can be solved.
[0223]
Therefore, by applying the present invention to a horizontal electric field type liquid crystal display device, it is possible to reduce the influence of the drive waveform distortion due to the length of the gate signal line GL, so that a liquid crystal display device having the largest display area is realized. I can do it.
[0224]
Also in the horizontal electric field type liquid crystal display device, the method of adjusting the potential drop component ΔV of the pixel electrode is not limited to the method of adjusting the gate-source capacitance Cgs, but the holding capacitance Cadd, the liquid crystal capacitance Cpix, and the source-drain capacitance Cds1. Alternatively, the pixel electrode drain signal line capacitance Cds2 may be adjusted.
[0225]
Embodiment 3
Next, another embodiment for adjusting the gate-source capacitance Cgs is shown in FIGS. 27 (a) and 27 (b).
[0226]
FIGS. 27A and 27B are diagrams showing a portion in the vicinity of the thin film transistor TFT in the plan view of the pixel shown in FIG. The configuration of the part not shown in FIGS. 27A and 27B is the same as the configuration of the pixel shown in FIG.
[0227]
FIG. 27A shows the configuration of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 27B shows the configuration of the thin film transistor TFT on the side far from the input terminal.
[0228]
In this embodiment, the direction of the channel length l of the thin film transistor TFT is arranged perpendicular to the direction in which the gate signal line GL extends.
[0229]
In this embodiment, the gate-source capacitance Cgs is adjusted by two portions of the adjustment pattern I1 provided in the semiconductor layer AS and the adjustment pattern I2 provided in the source electrode SD1, and the pixel of the potential lowering component ΔV of the pixel electrode is adjusted. The difference between them is reduced. Therefore, in this embodiment, since the adjustment pattern I1 and the adjustment pattern I2 can be provided in a narrow area, the aperture ratio of the pixel can be improved.
[0230]
Further, as shown in FIGS. 27A and 27B, in this embodiment, the adjustment pattern I2 provided on the source electrode SD1 is provided apart from the portion defining the channel length l and the channel width W of the thin film transistor TFT. Therefore, the drive capability of the thin film transistor TFT is not changed by providing the adjustment pattern I2 on the source electrode SD1.
[0231]
Embodiment 4
FIG. 28A and FIG. 28B show another embodiment for adjusting the gate-source capacitance Cgs.
[0232]
FIGS. 28A and 28B are also diagrams showing a portion in the vicinity of the thin film transistor TFT in the plan view of the pixel shown in FIG. The configuration of the part not shown in FIGS. 28A and 28B is the same as the configuration of the pixel shown in FIG.
[0233]
FIG. 28A shows the configuration of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 28B shows the configuration of the thin film transistor TFT on the side far from the input terminal.
[0234]
In this embodiment, the gate electrode GT of the thin film transistor TFT is branched from the gate signal line GL.
[0235]
In this embodiment, a notch pattern I3 is provided in the portion of the gate electrode GT of the thin film transistor TFT that overlaps the source electrode SD1 to adjust the gate-source capacitance Cgs, so that the pixel electrode potential decrease component ΔV is different between pixels. Is reduced. Therefore, in this embodiment, the aperture ratio is not sacrificed, unlike the case where the projection is provided on the gate electrode GT made of the light-shielding metal film.
[0236]
In order to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal, the notch pattern I3 provided in the gate electrode GT shown in FIGS. What is necessary is just to increase the notch amount of the notch pattern I3, so that it is nearer.
[0237]
Also in this embodiment shown in FIGS. 28A and 28B, the adjustment pattern I3 provided on the gate electrode GT is provided apart from the portion defining the channel length l and the channel width W of the thin film transistor TFT. Therefore, the driving capability of the thin film transistor TFT is not changed by providing the adjustment pattern I3 on the gate electrode GT.
[0238]
Embodiment 5
Next, a description will be given of an embodiment in which a countermeasure for reducing the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal is applied to the liquid crystal display device in which the aperture ratio of the pixel is increased.
[0239]
<Pixel area configuration>
FIG. 29A is a plan view showing a specific configuration of the pixel region corresponding to the dotted line frame A in FIG. 2 according to the present embodiment.
[0240]
A sectional view taken along line IV-IV in FIG. 29A is shown in FIG. 30, a sectional view taken along line VV is shown in FIG. 31, and a sectional view taken along line VI-VI is shown in FIG.
[0241]
As shown in FIG. 30, in the liquid crystal display panel, a thin film transistor TFT and a pixel electrode ITO1 are formed on the first transparent substrate SUB1 side based on the liquid crystal LC, and a color filter FIL and a black matrix are formed on the second transparent substrate SUB2 side. A pattern (first light shielding film) BM1 is formed.
[0242]
In FIG. 30, POL1 is a first polarizing plate provided on the first transparent substrate SUB1, and POL2 is a second polarizing plate provided on the second transparent substrate SUB2.
[0243]
First, gate signal lines GL extending in the x direction and arranged in parallel in the y direction are formed on the liquid crystal side surface of the first transparent substrate SUB1 made of glass or the like.
[0244]
The gate signal line GL is composed of a conductive layer gl made of chromium, molybdenum, an alloy of chromium and molybdenum, aluminum, tantalum, titanium, or the like. Further, in order to reduce the wiring resistance of the gate signal line GL, the gate signal line GL may be configured by using the above-described laminated film of conductive films. When aluminum is used for the gate signal line GL, an alloy to which a small amount of metal such as tantalum, titanium or niobium is added may be used in order to eliminate protrusions such as hillocks and whiskers.
[0245]
A pixel electrode ITO1 made of a transparent conductive film (for example, Indium-Tin-Oxide) is formed in most of the pixel region surrounded by the gate signal line GL and a drain signal line DL described later.
[0246]
A part of the pixel region on the gate signal line GL on the lower left side of the drawing is a formation region of the thin film transistor TFT. In the thin film transistor TFT, for example, a gate insulating film GI made of SiN, a semiconductor layer AS made of i-type amorphous Si, a semiconductor layer d0 made of amorphous Si containing impurities, a drain electrode SD2 and a source electrode SD1 are sequentially laminated. Is formed.
[0247]
The drain electrode SD2 and the source electrode SD1 are formed simultaneously with the drain signal line DL.
[0248]
As shown in FIG. 31, the drain signal line DL is formed on the insulating film GI, the semiconductor layer AS, and the semiconductor layer d0 made of amorphous Si containing impurities, and is made of chromium, molybdenum, an alloy of chromium and molybdenum, aluminum, It is formed of a single layer or a laminate of conductive films such as tantalum or titanium. The reason why the semiconductor layer AS and the semiconductor layer d0 including the impurity are formed in the formation region of the drain signal line DL is, for example, that the drain signal line DL is prevented from being disconnected due to a step between the semiconductor layer AS and the semiconductor layer d0 including the impurity. It is to do.
[0249]
The drain electrode SD2 of the thin film transistor TFT is formed integrally with the drain signal line DL, and the source electrode SD1 is formed apart from the drain electrode SD2 by a predetermined channel length l.
[0250]
A protective film PSV1 made of an insulating film is provided on the source electrode SD1 and the drain electrode SD2. The protective film PSV1 avoids deterioration of characteristics due to direct contact of liquid crystal with the thin film transistor TFT. The protective film PSV1 is made of a film having good moisture resistance such as a silicon nitride film or an organic resin film such as polyimide.
A pixel electrode ITO1 is formed on the protective film PSV1.
[0251]
The protective film PSV1 on the source electrode SD1 is provided with a through hole CONT for electrically connecting the source electrode SD1 and the pixel electrode ITO1.
[0252]
In addition, as shown in FIG. 32, the storage capacitor element Cadd is formed with a gate signal line (another gate signal line adjacent to the gate signal line driving the thin film transistor TFT) GL at the same time as one electrode and the pixel electrode ITO1. The conductive layer is used as the other electrode, and the insulating film GI and the protective film PSV1 interposed therebetween are used as the dielectric film.
[0253]
The insulating film GI and the protective film PSV1 are formed simultaneously with their formation in the thin film transistor TFT, and the conductive layer as the other electrode is formed simultaneously with the pixel electrode ITO1.
[0254]
An alignment film ORI1 for regulating the alignment of the liquid crystal is formed over the entire surface of the pixel electrode ITO1.
[0255]
In this embodiment, since the protective film PSV1 which is an insulating film exists between the pixel electrode ITO1 and the gate signal line GL and the drain signal line DL, the pixel electrode ITO1 and the gate signal line GL or the pixel electrode ITO1 and the drain signal line. Even if the DLs overlap in a plane, there is no short circuit. Therefore, in this embodiment, the pixel electrode ITO1 can be formed large, and therefore, the pixel opening is increased, and the liquid crystal capacitance Cpix is increased, so that the holding capacitance Cadd can be reduced.
[0256]
A first light shielding film BM1, a color filter FIL, a common transparent electrode COM, and an upper alignment film ORI2 are sequentially stacked on the inner surface (liquid crystal LC side) of the second transparent substrate SUB2 made of glass or the like. .
[0257]
The first light-shielding film BM1 is made of a light-shielding metal film such as chromium or aluminum, or a light-shielding organic film obtained by adding a dye, pigment, carbon, or the like to a resin film such as acrylic.
The common transparent electrode COM is made of a transparent conductive film such as ITO (Indium-Tin-Oxide).
[0258]
The color filter FIL is formed by adding a dye or a pigment to a base material made of an organic resin film such as acrylic.
[0259]
In order to prevent the dye or pigment of the color filter FIL from contaminating the liquid crystal LC, a color filter protective film made of an organic resin film such as acrylic may be provided between the color filter FIL and the common transparent electrode COM. .
[0260]
<< Second light shielding film BM2 >>
In this embodiment, as shown in FIGS. 29A and 31, a second light shielding film BM2 made of a light shielding metal film is provided on the first transparent substrate SUB1 on which the drain signal line DL is formed. It has been. The second light shielding film BM2 is made of the same material as the conductive film g1 constituting the gate signal line GL and is formed in the same layer as the gate signal line GL.
[0261]
As shown in FIG. 29A, the second light shielding film BM2 is formed so as to overlap the pixel electrode ITO1 along the drain signal line DL and not overlap with the drain signal line DL. Yes. On the other hand, as shown in FIG. 31, the second light shielding film SUB2 is insulated and separated by the drain signal line DL and the gate insulating film GI as shown in FIG. For this reason, the possibility that the second light shielding film BM2 and the drain signal line DL are short-circuited is small. Further, the pixel electrode ITO1 and the second light shielding film BM2 are insulated and separated by the gate insulating film GI and the protective film PSV1.
[0262]
The second light shielding film BM2 has a function of improving the area of the transmissive portion of the pixel electrode with respect to one pixel, that is, the aperture ratio, and improving the brightness of the display panel. In the display panel shown in FIG. 28, the backlight BL is set on one side of the first transparent substrate SUB1. Although the backlight BL may be provided on the second transparent substrate SUB2 side, in the following, for example, the backlight is irradiated from the first transparent substrate SUB1 side and observed from the second transparent substrate SUB2 side as an example. Show. Irradiation light is transmitted through the first transparent substrate SUB1, and liquid crystal is emitted from a portion where the light-shielding films (gate signal line GL, drain signal line DL, and second light-shielding film BM2) on the first transparent substrate SUB1 are not formed. Enter LC. This light is controlled by a voltage applied between the common electrode COM formed on the second transparent substrate SUB2 and the pixel electrode ITO1 formed on the first transparent substrate SUB1.
[0263]
In the normally white mode, where the display panel applies a voltage to the pixel electrode ITO1, the light transmittance decreases. When the second light-shielding film BM2 is not formed as in this embodiment, the second transparent substrate SUB2 It is necessary to widely cover the periphery of the pixel electrode ITO1 with the first light shielding film BM1 provided on the electrode, otherwise light that cannot be controlled by voltage leaks from the drain signal line DL or the gap between the gate signal line GL and the pixel electrode ITO1, Display contrast decreases. In addition, the second transparent substrate SUB2 and the first transparent substrate SUB1 are bonded to each other with the liquid crystal interposed therebetween, and it is necessary to provide a large alignment margin. In this embodiment, the second light-shielding film BM2 is provided on the first transparent substrate SUB1. The aperture ratio is smaller than
[0264]
In the present embodiment, the second light-shielding film SUB2 uses the same light-shielding metal film g1 as the gate signal line GL. However, any material that can block light may be used. An insulating light-shielding film that contains a pigment or carbon to form a light-shielding film may be used.
[0265]
<< Method for making the potential drop component ΔV of the pixel electrode uniform >>
FIG. 29A shows a planar structure of the pixel on the input terminal side, and FIG. 29B shows a part of the planar structure of the pixel far from the input terminal (for example, the termination side).
[0266]
Also in this embodiment, the direction of the channel length l of the thin film transistor TFT is arranged perpendicular to the direction in which the gate signal line GL extends.
[0267]
In this embodiment, the pixel electrode ITO1 is provided with a portion 1 that overlaps the gate signal line GL for selecting the pixel electrode ITO1, the gate-source capacitance Cgs is adjusted, and the pixel electrode potential decrease component ΔV is different between pixels. Is reduced.
[0268]
In the adjustment pattern I4 provided on the pixel electrode ITO1 shown in FIG. 29A, in order to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal, the adjustment pattern becomes more distant from the input terminal. The area where I4 and the gate signal line GL overlap with each other may be increased by a predetermined amount d than the pixel closer to the input terminal.
[0269]
In this embodiment, in order to adjust the gate-source capacitance Cgs for each pixel, the pixel electrode ITO1 is provided so as to extend to a portion overlapping the gate signal line GL for selecting the pixel electrode ITO1, so that the light shielding property is provided. The gate signal line GL made of the above metal performs the same function as the first light shielding film BM1 covering the edge of the pixel electrode. Therefore, the first light-shielding film BM1 that covers the portion 1 where the pixel electrode ITO1 and the gate signal line GL overlap can be moved back in the direction of the gate signal line GL indicated by the arrow, and the pixel opening can be enlarged.
[0270]
In the present embodiment, the storage capacitor Cadd provided in the portion where the pixel electrode ITO1 and the gate signal line GL of the adjacent pixel overlap is also the first light blocking because the gate signal line GL of the adjacent pixel is made of a light-shielding metal. Performs the same function as the membrane BM1. Therefore, the first light-shielding film BM1 can be retracted to the position where the gate signal line GL is exposed, and the aperture of the pixel is improved.
[0271]
In this embodiment, the protective film PSV1 and the insulating film GI are used as the dielectric of the gate-source capacitance Cgs. Since there is very little possibility that a pinhole exists in the same place of the protective film PSV1 and the insulating film GI, there is no problem that the pixel electrode ITO1 and the gate signal line GL are short-circuited in the portion I4 for adjusting the gate-source capacitance Cgs. .
[0272]
Embodiment 6
Next, another embodiment for adjusting the gate-source capacitance Cgs is shown in FIGS. 33 (a) and 33 (b).
[0273]
FIG. 33A and FIG. 33B are diagrams showing a portion in the vicinity of the thin film transistor TFT in the plan view of the pixel shown in FIG. The configuration of the part not shown in FIGS. 33A and 33B is the same as the configuration of the pixel shown in FIG.
[0274]
FIG. 33A shows the configuration of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 33B shows the configuration of the thin film transistor TFT on the side far from the input terminal.
[0275]
In this embodiment, the direction of the channel length l of the thin film transistor TFT is arranged perpendicular to the direction in which the gate signal line GL extends.
[0276]
In this embodiment, the gate-source capacitance Cgs is adjusted by the adjustment pattern I5 provided on the gate signal line GL in the portion overlapping the source electrode SD1, thereby reducing the difference between the pixels in the potential drop component ΔV of the pixel electrode. ing.
[0277]
In order to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal, the adjustment pattern I5 provided on the gate signal line GL shown in FIGS. The farther the pixel, the larger the area where the adjustment pattern I5 and the source electrode SD1 overlap.
[0278]
Embodiment 7
34 (a) and 34 (b) show another embodiment for adjusting the gate-source capacitance Cgs.
[0279]
34 (a) and 34 (b) are also diagrams showing a portion in the vicinity of the thin film transistor TFT in the plan view of the pixel shown in FIG. 29 (a). The configuration of the part not shown in FIGS. 34A and 34B is the same as the configuration of the pixel shown in FIG.
[0280]
34A shows the configuration of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 34B shows the configuration of the thin film transistor TFT on the side far from the input terminal.
[0281]
Also in this embodiment, the direction of the channel length l of the thin film transistor TFT is arranged perpendicular to the direction in which the gate signal line GL extends.
[0282]
In this embodiment, the gate signal line GL is provided with an adjustment pattern I6 that overlaps with the pixel electrode ITO1, and the gate-source capacitance Cgs is adjusted to reduce the difference between the pixels in the potential drop component ΔV of the pixel electrode. .
[0283]
In order to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal with the adjustment pattern I6 provided on the gate signal line GL shown in FIGS. 34 (a) and 34 (b), from the input terminal. The farther away the pixel, the larger the area where the adjustment pattern I6 and the pixel electrode ITO1 overlap than the pixel closer to the input terminal.
[0284]
Embodiment 8
FIG. 35A and FIG. 35B show another embodiment for adjusting the gate-source capacitance Cgs.
[0285]
FIGS. 35A and 35B are also diagrams showing a portion in the vicinity of the thin film transistor TFT in the plan view of the pixel shown in FIG. The configuration of the part not shown in FIGS. 35A and 35B is the same as the configuration of the pixel shown in FIG.
[0286]
FIG. 35A shows the configuration of the thin film transistor TFT of the pixel on the input terminal side, and FIG. 35B shows the configuration of the thin film transistor TFT on the side far from the input terminal.
[0287]
In this embodiment, the gate electrode GT of the thin film transistor TFT is branched from the gate signal line GL.
[0288]
In this embodiment, adjustment patterns I7 and I7 ′ are provided at two portions of the source electrode SD1 of the thin film transistor TFT that overlap with the gate electrode GT to adjust the gate-source capacitance Cgs, thereby reducing the potential drop component ΔV of the pixel electrode. The difference between the pixels is reduced.
[0289]
In order to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal, the adjustment patterns I7 and I7 ′ provided on the source electrode SD1 shown in FIG. 35A and FIG. The total area of the adjustment patterns I7 and I7 ′ may be increased as the pixel is farther from the terminal.
[0290]
In this embodiment shown in FIGS. 35A and 35B, the width of the semiconductor layer AS is made smaller than the width of the source electrode SD1, and the channel width W of the thin film transistor TFT is defined by the width of the semiconductor layer AS. doing. Since the patterns I7 and I7 ′ for adjusting the gate-source capacitance Cgs are provided in a portion not overlapping with the semiconductor layer AS, the driving capability of the thin film transistor TFT is provided by providing the adjustment patterns I7 and I7 ′ on the source electrode SD1. Will not change.
[0291]
In the embodiment shown in FIGS. 35A and 35B, the semiconductor layer AS is shielded from light by the gate electrode GT, and the semiconductor layer AS is planarly arranged in order to prevent malfunction of the thin film transistor TFT. It is provided only in the region where GT exists. Therefore, when the semiconductor layer AS is completely shielded by the gate electrode GT, there is a portion where the semiconductor layer AS is not provided between the source electrode SD1 and the gate electrode GT, which has a demerit that the gate-source capacitance Cgs is increased. However, in this embodiment, the gate-source capacitance Cgs is adjusted to reduce the difference in the potential drop component ΔV of the pixel electrode, so that the gate- The disadvantage that the inter-source capacitance Cgs is increased can be reduced.
[0292]
Embodiment 9
FIG. 36A and FIG. 36B show another embodiment for adjusting the storage capacitor Cadd.
[0293]
FIG. 36A and FIG. 36B are diagrams showing the planar structure of the pixel of this example.
[0294]
FIGS. 36A and 36B also have the same structure as the liquid crystal display device having the pixel structure shown in FIG. Therefore, the configuration of the part not specifically described in the present embodiment is the same as the configuration of the pixel shown in FIG.
[0295]
FIG. 36A shows a configuration of a pixel on the input terminal side, and FIG. 36B shows a configuration of a pixel far from the input terminal.
[0296]
In this embodiment, the storage capacitor Cadd is adjusted by changing the area of the portion where the gate signal line GL of the pixel adjacent to the pixel electrode ITO1 overlaps, thereby reducing the difference between the pixels in the potential decrease component ΔV of the pixel electrode. .
[0297]
In order to reduce the difference in the potential drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal by adjusting the storage capacitor Cadd shown in FIGS. 36A and 36B, the pixel closer to the input terminal is used. However, the area where the gate signal line GL of the pixel far from the input terminal overlaps with the pixel electrode ITO1 may be reduced by a predetermined amount indicated by d to reduce the storage capacitor Cadd.
[0298]
Embodiment 10
FIGS. 37A and 37B show another embodiment for adjusting the liquid crystal capacitance Cpix.
[0299]
FIG. 37A and FIG. 37B are diagrams showing the planar structure of the pixel of this example.
[0300]
FIG. 37A and FIG. 37B also have the same structure as the liquid crystal display device having the pixel structure shown in FIG. Therefore, the configuration of the part not specifically described in the present embodiment is the same as the configuration of the pixel shown in FIG.
[0301]
FIG. 37A shows a configuration of a pixel on the input terminal side, and FIG. 37B shows a configuration of a pixel far from the input terminal.
[0302]
In this embodiment, the area of the pixel electrode ITO1 is changed, the area overlapping the common electrode COM is changed, the liquid crystal capacitance Cpix is adjusted, and the difference between the pixels in the potential drop component ΔV of the pixel electrode is reduced.
[0303]
In order to reduce the difference in the voltage drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal by changing the area of the pixel electrode ITO1 shown in FIGS. 37 (a) and 37 (b), The liquid crystal capacitance Cpix may be reduced by reducing the area of the pixel electrode farther from the input terminal than the pixel by a predetermined amount indicated by d.
[0304]
In this embodiment, as shown in FIGS. 37A and 37B, even if the area of the pixel electrode ITO1 is changed, the opening area of the first light shielding film BM1 is far from the input terminal and the pixels near the input terminal. Same pixel. Furthermore, in this embodiment, the area of the pixel electrode is changed by changing the shape of the part of the pixel electrode ITO1 covered with the first light shielding film BM1, and the liquid crystal capacitance Cpix is adjusted. There is no difference in the aperture through which light passes between pixels far from the input terminal, and no luminance difference occurs.
[0305]
Embodiment 11
FIG. 38A and FIG. 38B show another embodiment in which the second light shielding film BM2 is formed of a light shielding metal film and the area where the second light shielding film BM2 and the pixel electrode ITO1 overlap is adjusted. Show.
[0306]
FIG. 38A and FIG. 38B are diagrams showing the planar structure of the pixel of this example.
[0307]
FIG. 38A and FIG. 38B also have the same structure as the liquid crystal display device having the pixel structure shown in FIG. Therefore, the configuration of the part not specifically described in the present embodiment is the same as the configuration of the pixel shown in FIG.
[0308]
FIG. 38A shows a configuration of a pixel on the input terminal side, and FIG. 38B shows a configuration of a pixel far from the input terminal.
[0309]
In this embodiment, the second light-shielding film BM2 is electrically connected to the gate signal line GL of the adjacent pixel, and the area where the second light-shielding film BM2 and the pixel electrode ITO1 overlap is changed to reduce the potential reduction component of the pixel electrode. The difference between the pixels of ΔV is reduced.
[0310]
In this embodiment, since the second light shielding film BM2 is electrically connected to the gate signal line GL of the adjacent pixel, the overlapping portion of the second light shielding film BM2 and the pixel electrode ITO1 has the same function as the storage capacitor Cadd. do.
[0311]
In order to reduce the difference in the voltage drop component ΔV of the pixel electrode due to the waveform distortion of the scanning signal by changing the overlapping area of the second light-shielding film BM2 and the pixel electrode ITO1 shown in FIGS. Increases the area where the second light-shielding film BM2 and the pixel electrode ITO1 of the pixel closer to the input terminal overlap by a predetermined amount shown by d than the pixel farther from the input terminal, thereby increasing the storage capacitor Cadd. do it.
[0312]
In this embodiment, the area of the second light-shielding film BM2 that functions as the storage capacitor electrode is changed without changing the area of the pixel electrode ITO1, so that the storage capacitor Cadd changes for each pixel. However, the liquid crystal capacitance Cpix does not change. Therefore, since the storage capacitor Cadd and the liquid crystal capacitor Cpix can be set independently, the pixel design is easy.
[0313]
If the area where the second light shielding film BM2 and the pixel electrode ITO1 overlap is changed, there is a problem that the aperture of the pixel changes. As shown in FIGS. 38 (a) and 38 (b), the second transparent substrate By changing the area where the second light shielding film BM2 and the pixel electrode ITO1 overlap in the region covered with the first light shielding film BM1 provided on the SUB2, it is possible to solve the problem of changing the pixel aperture.
[0314]
In this embodiment, the second light shielding film BM2 is electrically connected to the gate signal line GL. However, the second light shielding film BM2 overlaps with the pixel electrode ITO1 in a state where the second light shielding film BM2 is electrically floated. Even if the area is changed, it is possible to reduce the difference in the potential drop component ΔV of the pixel electrode. When the second light-shielding film BM2 is in an electrically floating state, the source-drain capacitance Cds1 or the pixel electrode-drain signal line capacitance Cds2 is changed when the area overlapping the pixel electrode ITO1 is changed. I can do it. In this case, the area where the second light shielding film BM2 and the pixel electrode ITO1 overlap is increased as the pixel is closer to the input terminal.
[0315]
However, increasing the source-drain capacitance Cds1 and the pixel electrode drain signal line capacitance Cds2 has a problem of crosstalk between the pixels. Therefore, as shown in FIG. 38 (a) and FIG. It is preferable to connect the light shielding film BM2 to the gate signal line GL.
[0316]
【The invention's effect】
As is apparent from the above description, according to the method of manufacturing a liquid crystal display device according to the present invention, the occurrence of flicker can be suppressed with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a plan view of an essential part showing an embodiment of a liquid crystal display device according to the present invention.
FIG. 2 is an equivalent circuit diagram showing an embodiment of a liquid crystal display device according to the present invention.
FIG. 3 is a plan view showing one embodiment of a pixel region of a liquid crystal display device according to the present invention.
4 is a cross-sectional view taken along line IV-IV in FIG.
5 is a cross-sectional view taken along line VV in FIG. 3. FIG.
6 is a cross-sectional view taken along line VI-VI in FIG.
7A to 7D are explanatory views showing another embodiment of the liquid crystal display device according to the present invention.
FIG. 8 is a plan view showing another embodiment of the liquid crystal display device according to the present invention.
9A and 9B are plan views showing another embodiment of the liquid crystal display device according to the present invention.
10A and 10B are plan views showing another embodiment of the liquid crystal display device according to the present invention.
FIGS. 11A and 11B are plan views showing another embodiment of the liquid crystal display device according to the present invention. FIGS.
FIG. 12 is an equivalent circuit diagram showing another embodiment of the liquid crystal display device according to the present invention.
FIG. 13 is a plan view showing another embodiment of the pixel region of the liquid crystal display device according to the present invention.
14 is a cross-sectional view taken along line VI-VI in FIG.
FIG. 15 is a diagram showing an equivalent circuit of a unit pixel of a TFT active matrix liquid crystal display device.
FIG. 16 is a drive waveform diagram of the TFT active matrix liquid crystal display device.
FIG. 17 is an equivalent circuit for one line of a liquid crystal display panel.
18A is a driving waveform diagram of a thin film transistor TFT of a pixel on the terminal side, FIG. 18B is a central portion, and FIG. 18C is a terminal side pixel.
FIG. 19 is a process diagram showing the method of manufacturing the thin film transistor substrate SUB1.
FIG. 20 is a process diagram showing the method of manufacturing the thin film transistor substrate SUB1.
FIG. 21 is a process diagram showing the method of manufacturing the thin film transistor substrate SUB1.
22A is a diagram showing a method of forming a pattern on the thin film transistor substrate SUB1 by photolithography, and FIG. 22B is a diagram showing an example of a photomask pattern.
FIG. 23A is a view showing another method for forming a pattern on the thin film transistor substrate SUB1 by photolithography, and FIG. 23B is a view showing another example of a photomask pattern.
FIG. 24 is an equivalent circuit of a liquid crystal display device according to another embodiment in which scanning signal line drive circuit sections 104 are provided at both left and right ends of a gate signal line.
FIG. 25 is a plan view showing a unit pixel of a lateral electric field type active matrix liquid crystal display device to which the present invention is applied.
26 is a view showing a cross section taken along the line 3-3 in FIG. 25. FIG.
FIGS. 27A and 27B are plan views of main parts of a pixel showing another embodiment of the liquid crystal display device according to the present invention. FIGS.
FIGS. 28A and 28B are plan views of main parts of a pixel, showing another embodiment of the liquid crystal display device according to the present invention. FIGS.
FIGS. 29A and 29B are plan views of a pixel portion showing another embodiment of the liquid crystal display device according to the present invention. FIGS.
30 is a cross-sectional view taken along line IV-IV in FIG. 29. FIG.
31 is a cross-sectional view taken along line VV in FIG. 29. FIG.
32 is a cross-sectional view taken along line VI-VI in FIG. 29. FIG.
33 (a) and 33 (b) are plan views of main parts of a pixel showing another embodiment of the liquid crystal display device according to the present invention.
34 (a) and 34 (b) are plan views of the main part of the pixel showing another embodiment of the liquid crystal display device according to the present invention.
35 (a) and 35 (b) are plan views of main parts of a pixel showing another embodiment of the liquid crystal display device according to the present invention.
36 (a) and 36 (b) are plan views of pixels showing another embodiment of the liquid crystal display device according to the present invention.
FIGS. 37A and 37B are plan views of pixels showing another embodiment of the liquid crystal display device according to the present invention. FIGS.
FIGS. 38A and 38B are plan views of pixels showing another embodiment of the liquid crystal display device according to the present invention. FIGS.
FIG. 39 is an explanatory diagram showing an example of a manufacturing method of a liquid crystal display device according to the present invention.
FIG. 40 is a plan view showing one embodiment of a pixel pattern obtained by the method for manufacturing a liquid crystal display device according to the present invention.
FIG. 41 is an explanatory view showing another embodiment of a method for producing a liquid crystal display device according to the present invention.
FIG. 42 is an explanatory view showing another embodiment of a method for producing a liquid crystal display device according to the present invention.
FIG. 43 is an explanatory diagram showing another embodiment of a method for manufacturing a liquid crystal display device according to the present invention.
FIG. 44 is an explanatory diagram showing one process for obtaining the characteristics of a sample in manufacturing a liquid crystal display device according to the present invention;
FIG. 45 is an explanatory diagram showing one process for obtaining the characteristics of a sample in manufacturing a liquid crystal display device according to the present invention;
FIG. 46 is an explanatory diagram showing one process for obtaining characteristics of a sample in manufacturing a liquid crystal display device according to the present invention;
FIG. 47 is an explanatory diagram showing one process for obtaining the characteristics of a sample in manufacturing a liquid crystal display device according to the present invention;
FIG. 48 is an explanatory diagram showing one process for obtaining the characteristics of a sample in manufacturing a liquid crystal display device according to the present invention;
FIG. 49 is an explanatory diagram showing one process for obtaining the characteristics of a sample in manufacturing a liquid crystal display device according to the present invention;
FIG. 50 is an explanatory diagram showing one process for obtaining characteristics of a sample in manufacturing a liquid crystal display device according to the present invention;
FIG. 51 is an explanatory diagram showing one process for obtaining characteristics of a sample in manufacturing a liquid crystal display device according to the present invention;
[Explanation of symbols]
GL ... Gate signal line, DL ... Drain signal line, ITO1 ... Pixel electrode, TFT ... Thin film transistor, GI ... Gate insulating film, AS ... Semiconductor layer, SD1 ... Source electrode, SD2 ... Drain electrode.

Claims (3)

A plurality of scanning signal lines; a plurality of video signal lines; a plurality of pixels; a thin film transistor and a pixel electrode provided in each pixel; the thin film transistor including a source electrode connected to the pixel electrode and the video signal line In a liquid crystal display device having a drain electrode and a semiconductor layer connected to each other ,
An adjustment pattern is provided in the region on the scanning signal line through an insulating film and provided on the semiconductor layer and the source electrode so as to be separated from a portion that defines a channel length and a channel width. A liquid crystal display device characterized by being larger on the terminal side than on the input terminal side of the line. A plurality of adjacent thin film transistors among the thin film transistors are sequentially grouped, and the sizes of the semiconductor layer and the source electrode increase sequentially for each group from the input terminal side to the termination side of the scanning signal line. The liquid crystal display device according to claim 1 .   The liquid crystal display device according to claim 2, wherein an area allocated to each group is sequentially increased from an input terminal side to a termination side of the scanning signal line.

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