JP2007121485A - Flickering prevention adjustment method of liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flickering prevention adjustment method of an active matrix liquid crystal display. <P>SOLUTION: In a liquid crystal display so constituted that a parasitic capacity (Cgs) of a TFT element is made large as the distance from a gate driver is longer to attain flatness of a common electrode voltage V<SB>COM</SB>, flickering in the all display region is prevented by setting a voltage level of the V<SB>COM</SB>so that flickering in a display center part is prevented and then adjusting the magnitude of a turn-on voltage Vgh of a gate signal voltage so that flickering in a display peripheral part is prevented. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a method for preventing flicker and image sticking of the active matrix liquid crystal display device, according to the particular V _COM adjustment method.

In each pixel of an active matrix LCD (liquid crystal display device) configuration including a TFT switching element, a voltage for driving the liquid crystal is applied between the pixel electrode and the common electrode when the TFT element is turned on. A signal (data) voltage is applied to the pixel electrode, and a constant common voltage _VCOM is applied to the common electrode. In the scanning format of line sequential driving, each row of the matrix is sequentially scanned, and an address voltage (gate signal voltage) that turns on all TFT elements on one row line being scanned by V _H in one horizontal scanning period. Is applied to the address line. That is, the signal voltage is applied to the pixel electrode only during the V _H period, and the signal voltage in the remaining period of one frame period is maintained by the charge accumulated in the storage capacitor parallel to the pixel electrode. When scanned in the next frame, the stored charge is updated with the next data.

Since the life of the liquid crystal is shortened when driven by a DC voltage, the polarity inversion driving method is generally adopted. FIG. 1 shows the waveform of the voltage applied to the liquid crystal in the frame inversion common DC driving method. That is, a signal voltage with polarity inversion of positive and negative is applied for each frame. If the frame F _i is positive, the frame F _{i + 1} is negative. During the _VH period when the TFT element is on, the signal voltage is directly applied to the pixel electrode via the TFT element, and at the same time, the storage capacitor is charged to the signal voltage. After that, when the TFT element is turned off, the charge voltage corresponding to the signal voltage should be maintained as it is for the remaining frame period, but between the gate and source (or gate and drain) coupled to the pixel electrode. When the signal voltage is positive, the charging voltage decreases by ΔVg ′, while when the signal voltage is negative, the signal voltage decreases by ΔV wave. This ΔVg is called a penetration voltage. Since the amount of decrease in ΔVg differs depending on the polarity of the signal voltage, the charging voltage, which is the voltage of the pixel electrode, becomes asymmetric between positive and negative, and so-called “flicker” occurs. In order to compensate for this asymmetry, the voltage level of the common voltage V _COM of the common electrode is set by shifting ΔV _COM from the center level of the signal voltage to the negative polarity side, and symmetry is established between the positive and negative signal voltages. Flicker is suppressed.

That is, the charging voltage penetrates both the positive and negative signal voltages, and decreases by the voltage ΔVg. In the case of TN, the liquid crystal capacity is different between black display and white display, so the optimum V _COM value of the penetration voltage is different between white display and black display. Usually, flicker is suppressed by performing flicker adjustment in intermediate gradation display.

On the other hand, the source electrode (or drain electrode) of the TFT element of each pixel is formed so as to overlap with the gate (address) wiring, and forms a parasitic capacitance Cgs of the gate wiring. This Cgs becomes a cause of delaying the gate pulse as the distance from the vicinity of the gate driver side in the gate line (or the waveform of the gate pulse becomes distorted). This affects the magnitude of the punch-through voltage ΔVg, and ΔVg decreases as the pixel becomes farther from the gate driver. As described above, V _{COM that} is set by shifting so as to obtain the objectivity of the positive and negative electrode characteristics of the signal voltage in order to eliminate flicker depends on the magnitude of ΔVg.

Then, the ΔVg the influence of the parasitic capacitance Cgs is varies with the position of the gate line, the voltage level values to be set is V _COM to eliminate flicker means that varies with the position of the gate line. Thus, when there is a delay in the gate line, the V _COM value with respect to the position of the gate line for eliminating flicker is shown by a solid line in FIG. In order to eliminate flicker, ΔVg expressed by the following equation should be constant and this V _COM value should be flat as shown by the dotted line in FIG.

ΔVg = (Vgh Vgl) x Cgs / (Cgs + Clc + Cs)
Vgh: Gate voltage on level
Vgl: Gate voltage off level
Cgs: parasitic capacitance between gate and source
Clc: Pixel capacity
Cs: Storage capacity

  For this reason, it has been proposed to compensate for the decrease in ΔVg associated with the gate line delay by increasing Cgs for the TFT element located far from the gate driver. For this reason, the channel width W / channel length of the TFT element is proposed. Is adopted (Japanese Patent Laid-Open No. 10-206823).

However, just increasing Cgs (increasing the channel width) in this way, V _COM is sufficient due to manufacturing variations such as the gate and signal line widths and the gate insulating film thickness. It was not possible to make it flat. Accordingly, an object of the present invention is to provide a method for improving an insufficient V _COM flattening due to manufacturing variations as described above by adjustment.

JP-A-10-206823

Liquid crystal disposed between the first and second substrates, gate lines and data lines defining a display region, arranged in a matrix on the first substrate, on the first substrate; A pixel electrode formed in a pixel region defined at each intersection of the gate line and the data line, formed on the first or second substrate so as to apply a liquid crystal driving voltage between the pixel electrode and the pixel electrode. A common electrode, provided outside the display region, and a gate driver that applies a signal to the gate line so as to sequentially scan each gate line, and a data driver provided outside the display region and that applies a data signal to each data line Active matrix liquid crystal comprising TFT elements provided in each of the pixel regions and TFT elements for applying a data signal on the data line to the pixel electrode when turned on by a gate signal on the gate line A flicker adjustment method shown device,
In an active matrix liquid crystal display device in which a gate-source parasitic capacitance of a TFT element arranged far from the position of the gate driver is larger than a gate-source parasitic capacitance of a TFT element arranged nearby. The flicker prevention adjustment method of the invention is performed.

In the adjustment method of the present invention, the voltage level is set by adjusting the voltage level of the common electrode voltage V _COM so as to prevent flicker at the center of the display unit of the liquid crystal display device, and the display unit of the liquid crystal display device The magnitude of the gate turn-on voltage Vgh of the gate signal voltage from the gate driver is adjusted so as to prevent flicker in the periphery of the gate driver.

According to the adjustment method of the present invention, even when the V _COM characteristics are not sufficiently flattened over the entire display area due to variations in gate line and signal line width, gate insulating film thickness, etc. It is possible to prevent flicker over the entire display area of the liquid crystal display device.

  FIG. 3 shows a structure in one pixel region in an active matrix LCD configuration as an object for implementing the adjustment method of the present invention. A TFT element and a pixel electrode are formed in one pixel region defined by the gate line (address line) 10 and the data line 20. The TFT element includes an amorphous semiconductor region (patch) 30, a drain electrode 40, and a source electrode 50, and the gate electrode includes a protruding portion 10 a extending from the gate line 10. The drain electrode 40 is connected to the data line 20, and the source electrode 50 is connected to the pixel electrode 60 through a contact hole. A part of the pixel electrode 60 overlaps with the next gate line 10 to form a storage capacitor Cs in the region 60.

  FIG. 4 shows a cross section of a TN liquid crystal display device including a TFT element structure. The gate wiring 10 and the protruding portion 10a are formed on the substrate a, the amorphous semiconductor patch 30 is formed on the insulating layer b, and the drain electrode 40 and the source electrode 50 are formed on the left and right sides of the n + α Si film c as a contact layer. Formed through. A protective film d covering them is attached, and the pixel electrode 60 is connected to the source electrode 50 through the contact hole e. A black matrix h, a color filter i, and a counter (common) electrode j are provided on the counter substrate g with the liquid crystal f interposed therebetween.

As a feature of the active matrix LCD configuration as an object for carrying out the adjustment method of the present invention, the gate-source parasitic capacitance Cgs of the TFT element is made larger as the distance from the gate driver side increases. As a specific example, the channel width W of each TFT element is increased with increasing distance from the gate driver side. In this way, V _COM is flattened for the time being.

  For one example of the TFT structure, FIG. 5 shows a TFT configuration at a position close to the gate driver, and FIG. 6 shows a TFT configuration at a far position. 5 and 6, 30 'and 30 "are amorphous semiconductor patches, 40' and 40" are drain electrodes, and 50 'and 50 "are source electrodes, and gate line protrusions 10a' and 10a serving as gate electrodes. ″ It is formed on top. In FIG. 5, the amorphous semiconductor patch 30 'is shown as a shaded area. In order to reduce the number of masks in the TFT element manufacturing process, the patch 30 'is formed on the same boundary line as the drain electrode 40' and coincides with the outline of the drain electrode 40 '.

  5 and 6, the source electrodes 50 ′ and 50 ″ and surrounding dot areas form a gate-source parasitic capacitance Cgs. The parasitic capacitance Cgs is larger in FIG. 6 than in FIG. 5. For this reason, the width of the source electrode is wide for the TFT far from the gate driver in Fig. 6. On the other hand, the channel width of the TFT element is shown as W 'in Fig. 5 and W "in Fig. 6. The channel gap of the TFT element is indicated by L ′ in FIG. 5 and L ″ in FIG. 6. According to the present invention, the channel width and channel gap of the TFT element are kept the same even if the parasitic capacitance Cgs is changed. That is, the source electrode and the drain electrode are designed so that W ′ = W ″ and L ′ = L ″.

5 and 6 has a basic structure in which a source electrode is contained in a nested drain electrode. In FIG. 6, the width of the source electrode is increased to increase the parasitic capacitance Cgs, so that the sides on both sides of the drain electrode are shortened so that the channel length is constant (ie, W ′ = W ″). In addition, the width of the recessed portion of the drain electrode is increased in order to make the channel gap constant (that is, L ′ = L ″). Further, the width of the lower side of the drain electrode is widened so that the channel gap L is constant. In this way, the parasitic capacitance Cgs is changed to make the punch-through voltage ΔVg constant for the gate line (address line) from the near end to the far end of the gate driver so that flicker does not occur even if V _COM is constant across the gate line. However, since the channel width W and the gap L are constant, the turn-on current Ion and the turn-off current Ioff of the TFT element are also constant, and there is no design problem caused by changing the parasitic capacitance Cgs.

  Specifically, first, the width of the source electrode 50 ″ is determined so as to obtain a desired Cgs, and the widths of I, II, III, IV, and V shown in FIG. Is realized.

As described above, the change in the parasitic capacitance Cgs (channel width W) results in a constant V _COM with respect to the distance from the gate driver. The characteristics vary from one production to another, and flicker cannot be suppressed sufficiently. In the V _COM adjustment method of the present invention, setting is performed by adjusting the V _COM level so as to suppress flicker at the center of the display of the LCD display device. If flickering occurs in the periphery due to the setting, then Vgh / Vgl (Vgh: gate voltage on level, Vgl: gate voltage off level) is set in order to perform peripheral flicker adjustment.

As shown in FIGS. 7 and 8, the V _COM characteristics in the LCD display device having a change in the parasitic capacitance Cgs (channel width W) are the line width between the gate line and the signal line in manufacturing, the film thickness of the gate insulating film, and the like. Deviations due to variations. FIG. 7 occurs when the line width of the gate line or the signal line is reduced, or when the thickness of the gate insulating film is increased. In this case, if Vgh is increased, the V _COM lined down like the dotted line can be adjusted to flat. FIG. 8 occurs when the line width of the gate line or the signal line is increased, or when the thickness of the gate insulating film is decreased. In this case, if Vgh is made smaller, V _COM that runs downward as shown by a single diagonal line can be adjusted to be flat. That is, the present inventor has found that the warpage of the V _COM characteristic can be adjusted by Vgh.

According to the inventor's recognition, in an LCD display device in which the parasitic capacitance Cgs (or channel width W) of the TFT element is constant from the distance of the gate driver, even if Vgh is changed, the “sled” of the V _COM characteristic can be adjusted. It was virtually impossible. Therefore, the V _COM characteristic adjustment method for preventing flicker is applied to an active matrix LCD display device of a type in which the parasitic capacitance Cgs (or channel width W) of the TFT element is changed.

  As an embodiment of the present invention, the TN liquid crystal display device in which the pixel electrode and the common electrode are respectively formed on different substrates has been described, but the gate line and the data line are formed on the first substrate (array substrate). It is apparent that the present invention can be applied to a TFT structure of a liquid crystal display device in which a common electrode is formed together with a pixel electrode, that is, it can be applied to a TN, IPS, FFS, or MVA type liquid crystal display device.

It is a figure which shows a pixel electrode voltage and a _VCOM voltage. It is a figure which shows the V _COM level for flicker prevention. It is a figure which shows the TFT element and pixel electrode in a pixel area | region in the liquid crystal display device to which the adjustment method of this invention is applied. It is a figure which shows the cross section of the liquid crystal display device in the liquid crystal display device to which the adjustment method of this invention is applied. It is a figure which shows the example of the structure of the TFT element near a gate driver on a gate line. It is a figure which shows the example of the structure of a TFT element far from the gate driver on a gate line. It is a figure which shows flattening of the V _COM characteristic by the adjustment method of this invention about a near end part V _COM characteristic. It is a figure which shows flattening of the V _COM characteristic by the adjustment method of this invention about a far end part V _COM characteristic.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Gate line 10a ... Gate line protrusion part 20 ... Data line 30 ... Amorphous semiconductor patch 40 ... Drain electrode 50 ... Source electrode 60 ... Pixel electrode 60a ... Storage capacitor part

Claims (2)

Liquid crystal disposed between the first and second substrates, gate lines and data lines defining a display region, arranged in a matrix on the first substrate, on the first substrate; A pixel electrode formed in a pixel region defined at each intersection of the gate line and the data line, formed on the first or second substrate so as to apply a liquid crystal driving voltage between the pixel electrode and the pixel electrode. A common electrode, provided outside the display area, and a gate driver for applying a signal to the gate line so as to sequentially scan each of the gate lines, provided outside the display area, and applying a data signal to each data line And a TFT element provided in each pixel region, and an active TFT comprising a TFT element that applies a data signal on the data line to the pixel electrode when turned on by a gate signal on the gate line. Matrit A scan liquid crystal display device,

Flicker adjustment of an active matrix liquid crystal display device formed so that the gate-source parasitic capacitance of a TFT element arranged far from the position of the gate driver is larger than the gate-source parasitic capacitance of a TFT element arranged nearby In the method

To prevent flicker in the central portion of the display portion of the liquid crystal display device, by adjusting the voltage level of the voltage V _COM of the common electrode, to set the voltage level, and

A flicker adjustment method comprising adjusting a magnitude of a gate turn-on voltage Vgh of a gate signal voltage from a gate driver so as to prevent flicker in a peripheral portion of a display portion of the liquid crystal display device.
2. The flicker adjustment method according to claim 1, wherein the channel width W of the TFT element is configured to increase as the TFT element moves away from the gate driver.

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