JP4856399B2 - TFT element electrode shape of liquid crystal display device - Google Patents
TFT element electrode shape of liquid crystal display device Download PDFInfo
- Publication number
- JP4856399B2 JP4856399B2 JP2005192589A JP2005192589A JP4856399B2 JP 4856399 B2 JP4856399 B2 JP 4856399B2 JP 2005192589 A JP2005192589 A JP 2005192589A JP 2005192589 A JP2005192589 A JP 2005192589A JP 4856399 B2 JP4856399 B2 JP 4856399B2
- Authority
- JP
- Japan
- Prior art keywords
- tft element
- gate
- width
- electrode
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 22
- 230000003071 parasitic effect Effects 0.000 claims description 17
- 239000011159 matrix material Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000035515 penetration Effects 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
Description
本発明は、アクティブマトリックス液晶表示装置に係り、特にＴＦＴ素子の電極構造に関する。 The present invention relates to an active matrix liquid crystal display device, and more particularly to an electrode structure of a TFT element.
ＴＦＴスイッチング素子を含むアクティブマトリックスＬＣＤ（液晶表示装置）構成の各画素において、ＴＦＴ素子がオンの際に画素電極と共通電極との間に液晶を駆動する電圧が与えられる。画素電極には信号（データ）電圧、共通電極には一定の共通電圧VCOMが印加される。線順次駆動の走査形式では、マトリックスの各行を順次に走査し、走査されている1つの行ライン上の全てのＴＦＴ素子を一水平走査期間のＶＨだけオンにするアドレス電圧（ゲート電圧）がアドレス線に印加される。即ち、ＶＨ期間の間だけ信号電圧が画素電極に印加され、１フレーム期間の残りの期間における信号電圧は、画素電極に並列な蓄積容量に蓄積された電荷により維持される。次のフレームにおいて走査されたとき、その蓄積電荷は次のデータにより更新される。 In each pixel of an active matrix LCD (liquid crystal display device) configuration including a TFT switching element, a voltage for driving the liquid crystal is applied between the pixel electrode and the common electrode when the TFT element is turned on. A signal (data) voltage is applied to the pixel electrode, and a constant common voltage VCOM is applied to the common electrode. In the scanning method of line sequential driving, an address voltage (gate voltage) that sequentially scans each row of the matrix and turns on all TFT elements on one row line being scanned by V H in one horizontal scanning period is used. Applied to the address line. That is, the signal voltage is applied to the pixel electrode only during the V H period, and the signal voltage in the remaining period of one frame period is maintained by the charge accumulated in the storage capacitor parallel to the pixel electrode. When scanned in the next frame, the stored charge is updated with the next data.
液晶は直流電圧で駆動すると寿命が短くなること等から、極性反転駆動方式が一般的に採用され、図１にフレーム反転コモンＤＣ駆動方式での液晶に印加される電圧の波形を示す。即ち、フレーム毎に正と負の極性反転の信号電圧を印加する。フレームＦｉで正極性なら、フレームＦｉ＋１で負極性とする。ＴＦＴ素子がオンであるＶＨ期間、信号電圧がＴＦT素子を介して画素電極に直接印加されると同時に、蓄積容量が信号電圧まで充電される。その後ＴＦＴ素子がオフになったとき、本来は信号電圧に対応する充電電圧が残りのフレーム期間そのまま維持されるべきであるが、画素電極に結合されているゲート・ソース（又はゲート・ドレイン）間の寄生容量Cgsに対し流れ又は流れ込み、信号電圧が正極性においては充電電圧がΔVgだけ低下し、一方信号電圧が負極性においては、+ΔVgだけ上昇する。このΔVgは突き抜け電圧と称される。信号電圧の極性によってこのΔVgは充電電圧を低下させる方向又は上昇させる方向に作用するから、画素電極の電圧である充電電圧は正と負極性で非対称となり、いわゆる“フリッカ”が生ずる。この非対称性を補うため、共通電極の共通電圧VCOMは、信号電圧の中心レベルから負極性側にΔVCOMだけシフトさせて正と負極性の信号電圧に対称性を取り、フリッカを抑制している。 Since the life of the liquid crystal is shortened when driven by a DC voltage, the polarity inversion driving method is generally adopted. FIG. 1 shows the waveform of the voltage applied to the liquid crystal in the frame inversion common DC driving method. That is, a signal voltage with polarity inversion of positive and negative is applied for each frame. If the frame F i is positive, the frame F i + 1 is negative. During the VH period when the TFT element is on, the signal voltage is directly applied to the pixel electrode via the TFT element, and at the same time, the storage capacitor is charged to the signal voltage. After that, when the TFT element is turned off, the charge voltage corresponding to the signal voltage should be maintained as it is for the remaining frame period, but between the gate and source (or gate and drain) coupled to the pixel electrode. When the signal voltage is positive, the charging voltage decreases by ΔVg, while when the signal voltage is negative, the signal voltage increases by + ΔVg. This ΔVg is called a penetration voltage. Depending on the polarity of the signal voltage, this ΔVg acts in the direction of decreasing or increasing the charging voltage, so that the charging voltage, which is the voltage of the pixel electrode, becomes asymmetrical between positive and negative, and so-called “flicker” occurs. In order to compensate for this asymmetry, the common voltage V COM of the common electrode is shifted by ΔV COM from the center level of the signal voltage to the negative polarity side to obtain symmetry between the positive and negative signal voltages and suppress flicker. Yes.
即ち、信号電圧が正極性、負極性共に充電電圧が突き抜け電圧ΔVgだけ低下する。又、TNの場合、黒表示と白表示で液晶容量が違うので、白表示と黒表示で突き抜け電圧の最適Vcomの値が違う。通常、中間階調表示でフリッカ調整を行うことでフリッカを抑制している。 That is, the charging voltage penetrates both the positive and negative signal voltages, and decreases by the voltage ΔVg. In the case of TN, since the liquid crystal capacity is different between black display and white display, the optimum Vcom value of the penetration voltage differs between white display and black display. Usually, flicker is suppressed by performing flicker adjustment in intermediate gradation display.
一方、各画素のＴＦＴ素子のソース電極（又はドレイン電極）はゲート（アドレス）配線と重なって形成され、ゲート配線の寄生容量Cgsを形成する。このCgsは、ゲート線においてゲートドライバ側の近くから遠くになるにつれてゲートパルスを遅延させる原因となる（又はゲートパルスの波形がなまってくる）。これは、突き抜け電圧ΔVgの大きさに影響を与え、ゲートドライバから遠い画素になるにつれてΔVgが小さくなる。前述のように、フリッカをなくすために信号電圧の正・負電極性での対象性を得るようシフトして設定したVCOMは、ΔVgの大きさに依存する。 On the other hand, the source electrode (or drain electrode) of the TFT element of each pixel is formed so as to overlap with the gate (address) wiring, and forms a parasitic capacitance Cgs of the gate wiring. This Cgs becomes a cause of delaying the gate pulse as the distance from the vicinity of the gate driver side in the gate line (or the waveform of the gate pulse becomes distorted). This affects the magnitude of the punch-through voltage ΔVg, and ΔVg decreases as the pixel becomes farther from the gate driver. As described above, V COM that is set by shifting so as to obtain the objectivity of the positive and negative electrode characteristics of the signal voltage in order to eliminate flicker depends on the magnitude of ΔVg.
そうすると、寄生容量Cgsの影響でΔVgがゲート線の位置で変わってくることは、フリッカをなくすためにVCOMが設定すべき値はゲート線の位置で変わってくることを意味する。このように、ゲート線に遅延がある際に、フリッカをなくすためのゲート線の位置に対するVCOM値を図２に示す。フリッカをなくすには、以下の式で示されるΔVgを一定にしてこのVCOM値がフラットであるべきである。 Then, the ΔVg the influence of the parasitic capacitance Cgs is varies with the position of the gate line means that the value to be set is V COM to eliminate the flicker varies in position of the gate line. FIG. 2 shows the V COM value for the position of the gate line for eliminating flicker when there is a delay in the gate line. In order to eliminate flicker, this V COM value should be flat with a constant ΔVg expressed by the following equation.
ΔVg = (Vgh Vgl) x Cgs / (Cgs + Clc + Cs)
Vgh：ゲート電圧のオンレベル
Vgl：ゲート電圧のオフレベル
Cgs：ゲート・ソース間の寄生容量
Clc：画素容量
Cs：蓄積容量
ΔVg = (Vgh Vgl) x Cgs / (Cgs + Clc + Cs)
Vgh: Gate voltage on level
Vgl: Gate voltage off level
Cgs: parasitic capacitance between gate and source
Clc: Pixel capacity
Cs: Storage capacity
このために、ゲートドライバから遠くなる位置のＴＦＴ素子について、Cgsを大きくすることでゲート線遅延に伴うΔVgが小さくなることを補償することが提案され、そのためにＴＦＴ素子のチャネル幅Ｗ／チャネル長を大きくしていくことが採用されている（特開平１０−２０６８２３号）。 For this reason, it has been proposed to compensate for the decrease in ΔVg associated with the gate line delay by increasing Cgs for TFT elements located far from the gate driver. Is adopted (Japanese Patent Laid-Open No. 10-206823).
一方、ゲート線への負荷容量を減少させるべく、ゲートドライバから遠くなる位置の、ゲート線と画素電極との間に形成される容量Csを徐々に小さくしていくことも提案されている（特開平２００２−３０３８８２号）。 On the other hand, in order to reduce the load capacitance to the gate line, it has also been proposed to gradually reduce the capacitance Cs formed between the gate line and the pixel electrode at a position far from the gate driver. (Kaihei 2002-303882).
しかしながら、上述のような従来技術では、ＴＦＴ素子のＷとＬが変わることによりゲート線の負荷容量が増えたり、ＴＦＴ素子のターンオン電流Ion、ターンオフ電流Ioffが変わるという副作用を伴い、設計上の困難さがあった。 However, the conventional techniques as described above have difficulty in designing due to the side effect that the load capacity of the gate line is increased by changing W and L of the TFT element, and the turn-on current Ion and the turn-off current Ioff of the TFT element are changed. There was.
本発明の課題は、そのような設計上の困難さが軽減された、フリッカ防止の手法を提供することにある。 An object of the present invention is to provide a flicker prevention technique in which such design difficulties are reduced.
第１と第２の基板間に配置された液晶、第１の基板上でマトリックス上に配置された、表示領域を画成しているゲート線とデータ線、第１の基板上で、ゲート線とデータ線の交点各々に規定された画素領域内に形成された画素電極、第１又は第２の基板上で、画素電極との間に液晶駆動電圧を印加するよう形成された共通電極、表示領域の外側に設けられ、ゲート線各々を逐次操作するよう、ゲート線に信号を印加するゲートドライバ、表示領域の外側に設けられ、データ線各々にデータ信号を印加するデータドライバ及び、画素領域各々に設けられたＴＦＴ素子であって、ゲート線上のゲート信号によってオンになったとき、データ線上のデータ信号を画素電極に印加するＴＦＴ素子とからなるアクティブマトリックス液晶表示装置において、ＴＦＴ素子は、ゲートライン上に配置されたアモルファス半導体パッチ、パッチ上に配置されたドレイン電極とソース電極とからなり、ゲートドライバの位置から遠くに配置されたＴＦＴ素子のゲート−ソース寄生容量Cgs″が、近くに配置されたＴＦＴ素子のゲート−ソース寄生容量Cgs′より大きくなるが、ＴＦＴ素子のチャネル幅Ｗとチャネルギャップはゲートドライバの位置からの距離に関わらず一定であるようドレイン電極とソース電極の形状・寸法が形成されている。 A liquid crystal disposed between the first and second substrates, a gate line and a data line defining a display region disposed on a matrix on the first substrate, and a gate line on the first substrate; And a pixel electrode formed in a pixel region defined at each intersection of the data line, a common electrode formed on the first or second substrate so as to apply a liquid crystal driving voltage to the pixel electrode, and a display A gate driver for applying a signal to the gate line so as to sequentially operate each of the gate lines provided outside the region, a data driver for applying a data signal to each of the data lines provided outside the display region, and each pixel region In the active matrix liquid crystal display device, the TFT element is provided with a TFT element that, when turned on by a gate signal on the gate line, applies a data signal on the data line to the pixel electrode. The TFT element includes an amorphous semiconductor patch disposed on the gate line, a drain electrode and a source electrode disposed on the patch, and a gate-source parasitic capacitance Cgs of the TFT element disposed far from the position of the gate driver. ″ Is larger than the gate-source parasitic capacitance Cgs ′ of the TFT element disposed in the vicinity, but the channel width W and the channel gap of the TFT element are set to be constant regardless of the distance from the position of the gate driver. The shape and dimensions of the source electrode are formed.
以上述べたように、本発明のアクティブマトリックスＬＣＤでは、寄生容量Cgsがゲートドライバから遠くになるにつれて大きくなるようにし、フリッカ防止のためのVCOMカーブを略一定にしているが、チャネル幅Ｗ、チャネルギャップＬを一定に維持しているので、ＴＦＴ素子のターンオン電流Ion、ターンオフ電流Ioffが各ＴＦＴ素子で一定であり、Cgsを変化させることによる他の設計事項に与える問題が少ない。又、このように変化するＴＦＴ素子構造をとっても、ゲート線に与える負荷容量が一定となるようにしているので、VCOMの設定値の選択に困難性がない。 As described above, in the active matrix LCD of the present invention, the parasitic capacitance Cgs is increased as the distance from the gate driver increases, and the V COM curve for preventing flicker is substantially constant. Since the channel gap L is kept constant, the turn-on current Ion and the turn-off current Ioff of the TFT element are constant in each TFT element, and there are few problems given to other design items by changing Cgs. Even if the TFT element structure changes in this way, the load capacitance applied to the gate line is made constant, so there is no difficulty in selecting the V COM set value.
本発明の実施例としてのアクティブマトリックスＬＣＤ構成における１画素領域での構造を図３に示す。ゲート線（アドレス線）１０とデータ線２０が画成する１画素領域に、ＴＦＴ素子と画素電極が形成される。ＴＦＴ素子はアモルファス半導体領域（パッチ）３０、ドレイン電極４０、ソース電極５０を含み、ゲート電極はゲート線１０から延在する突出部１０ａで構成される。ドレイン電極４０はデータ線２０に接続され、ソース電極５０はコンタクトホールを介して画素電極５０に接続されている。画素電極５０の一部は次のゲート線１０と重複して領域６０で蓄積容量Csを形成している。
FIG. 3 shows a structure in one pixel region in an active matrix LCD configuration as an embodiment of the present invention. A TFT element and a pixel electrode are formed in one pixel region defined by the gate line (address line) 10 and the
図４は、ＴＦＴ素子構造部を含むＴＮ型液晶表示装置の断面を示す。基板ａ上にゲート配線１０とその突出部１０ａが形成され、絶縁層ｂ上にアモルファス半導体パッチ３０が形成され、その左右にドレイン電極４０とソース電極３０が接触層としてのn + α Si膜ｃを介して形成される。それらをカバーする保護膜dがつけられ、コンタクトホールeを介して画素電極６０がソース電極５０に接続されている。液晶fをはさみ、対向基板g上にブラックマトリクスh、カラーフィルタi、対向（共通）電極jが設けられる。
FIG. 4 shows a cross section of a TN liquid crystal display device including a TFT element structure. The
発明に従うＴＦＴ構造について、ゲートドライバに近い位置にあるＴＦＴ構成を図５、遠い位置にあるＴＦＴ構成を図６に示す。図５と図６において、３０′と３０″はアモルファス半導体パッチ、４０′と４０″はドレイン電極、そして５０′と５０″はソース電極であり、ゲート電極となるゲート線突出部１０ａ′と１０ａ″上に形成されている。図５において、アモルファス半導体パッチ３０′は斜線区域として示されている。ＴＦＴ素子製造工程でマスク枚数を減らすため、パッチ３０′はドレイン電極４０′と同一境界線で形成され、ドレイン電極４０′の外郭と一致している。
For the TFT structure according to the invention, FIG. 5 shows a TFT configuration at a position close to the gate driver, and FIG. 6 shows a TFT configuration at a distant position. 5 and 6, 30 'and 30 "are amorphous semiconductor patches, 40' and 40" are drain electrodes, and 50 'and 50 "are source electrodes, and
図５と図６において、ソース電極５０′、５０″とその周辺の点区域がゲート・ソース寄生容量Cgsを形成する。寄生容量Cgsは図５のものに対し、図６のものが大きくなっている。このため、ソース電極の幅は図６のゲートドライバから遠い位置のＴＦＴのものが広くなっている。一方、ＴＦＴ素子のチャネル幅は図５においてＷ′、図６においてＷ″として示され、ＴＦＴ素子のチャネルギャップは図５においてＬ′、図６においてＬ″として示されている。本発明によると、寄生容量Cgsを変えてもＴＦＴ素子のチャネル幅とチャネルギャップは同じに維持される。即ち、Ｗ′＝Ｗ″、Ｌ′＝Ｌ″となるように、ソース電極とドレイン電極が設計される。
5 and 6, the
図５と図６の実施例では、入れ子状に凹形のドレイン電極の中にソース電極が入っている基本構造をしている。図６で寄生容量Cgsを大きくするためソース電極の幅を広くした分、チャネル長を一定（即ちＷ′＝Ｗ″）にすべくドレイン電極の両側の辺は短くなっている。即ちIVの長さを大きくしている。又、チャネルギャップを一定（即ちＬ′＝Ｌ″）にすべく、ドレイン電極のへこみ部の横幅は広くしている。又、チャネルギャップＬを一定にすべくドレイン電極の下辺の幅を広くしている。このように、寄生容量Cgsを変えて突き抜け電圧ΔVgをゲート線（アドレス線）についてゲートドライバの近端から遠端にわたって一定にし、VCOMをゲート線にわたって一定であってもフリッカが生じないようにしているが、チャネル幅ＷとギャップＬを一定にしているので、ＴＦＴ素子のターンオン電流Ion、ターンオフ電流Ioffも一定になり、寄生容量Cgsを変化させることによる設計上の弊害がない。 5 and 6 has a basic structure in which a source electrode is contained in a nested drain electrode. In FIG. 6, the width of the source electrode is increased to increase the parasitic capacitance Cgs, so that the sides on both sides of the drain electrode are shortened so that the channel length is constant (ie, W ′ = W ″). In addition, the width of the recessed portion of the drain electrode is increased in order to make the channel gap constant (that is, L ′ = L ″). Further, the width of the lower side of the drain electrode is widened so that the channel gap L is constant. In this way, the parasitic capacitance Cgs is changed to make the punch-through voltage ΔVg constant for the gate line (address line) from the near end to the far end of the gate driver so that flicker does not occur even if V COM is constant across the gate line. However, since the channel width W and the gap L are constant, the turn-on current Ion and the turn-off current Ioff of the TFT element are also constant, and there is no design problem caused by changing the parasitic capacitance Cgs.
具体的には、先ず所望のCgsを得るようソース電極５０″の幅を決め、図６に示すＩ、II、III、IV及びVの幅を適宜選択することで、一定のチャネル長とチャネルギャップを実現している。
Specifically, first, the width of the
ＴＦＴ素子構造がゲート線に与える負荷容量は、ゲート線上のアモルファス半導体パッチの面積（図５の斜線領域）による。負荷容量がゲート線の位置で変わると、遅延の量が変化してVCOM部分に影響する。このため、突き抜け電圧ΔVgがCgs/(Cs + Clc + Cgs)だけで決まらず、仮にCgsを適当に変えてもΔVgを精度良く一定にすることが困難になる。つまり、最適改善ポイントとなる寄生容量Cgsの変化の仕方、又VCOMの設定値の選択が困難となる。 The load capacitance given to the gate line by the TFT element structure depends on the area of the amorphous semiconductor patch on the gate line (shaded area in FIG. 5). As the load capacitance changes with the gate line position, the amount of delay changes and affects the V COM portion. For this reason, the punch-through voltage ΔVg is not determined only by Cgs / (Cs + Clc + Cgs), and it becomes difficult to make ΔVg accurate and constant even if Cgs is appropriately changed. In other words, the manner of change of the parasitic capacitance Cgs that the optimum improvement point, also the selection of V COM setting becomes difficult.
図５と図６の実施例では、前述のようにアモルファス半導体パッチは、ドレイン電極外郭と一致している。従って、寄生容量Cgsを変える際にゲート線に与える負荷容量を一定に保つには、ドレイン電極外郭サイズ（特にドレイン電極の横幅）を一定に保ちながら、図６に示すＩ、II、III、IV、及びＶを調節することが必要である。 5 and 6, the amorphous semiconductor patch coincides with the drain electrode outline as described above. Therefore, in order to keep the load capacitance applied to the gate line constant when changing the parasitic capacitance Cgs, the drain electrode outline size (especially the lateral width of the drain electrode) is kept constant while I, II, III, IV shown in FIG. , And V need to be adjusted.
図７に示すＴＦＴ素子構造は、アモルファス半導体パッチの露光工程専用のマスクを用いるもので、アモルファス半導体パッチ３０（斜線領域）がドレイン電極外郭より大きくなっているタイプである。このタイプでは、アモルファス半導体パッチ３０の面積はドレインとソース電極の形状に関わりなく一定であるので、チャネル幅Ｗ、チャネルギャップＬを維持しながら寄生容量Cgsを変えるようドレインとソース電極の形状を変えても、ＴＦＴ素子構造がゲート線に与える負荷容量は変わらないことになる。
The TFT element structure shown in FIG. 7 uses a mask dedicated to the exposure process of the amorphous semiconductor patch, and is a type in which the amorphous semiconductor patch 30 (shaded area) is larger than the drain electrode outline. In this type, since the area of the
従って、本発明の図５と図６の実施例ではドレイン電極の横幅のＤを略一定に保つようにしている。このため、本発明実施例ではＴＦＴ素子のアモルファス半導体パッチのサイズを一定にしている。即ち、Ｄを一定に保ちながら図６のＩ、II、III、IV及びＶで示す長さを調節して、寄生容量Cgsを大きくしてもＴＦＴ素子各々のゲート線に与える負荷容量が一定になるようにしている。図６の場合では、幅Ｄを一定にして幅Ｖを大きくした分、ドレイン電極の両側辺の幅ＩとIIが細くなっている。 Therefore, in the embodiment of FIGS. 5 and 6 of the present invention, the width D of the drain electrode is kept substantially constant. For this reason, in the embodiment of the present invention, the size of the amorphous semiconductor patch of the TFT element is made constant. That is, while maintaining D constant, the lengths indicated by I, II, III, IV and V in FIG. 6 are adjusted so that the load capacitance applied to the gate line of each TFT element is constant even if the parasitic capacitance Cgs is increased. It is trying to become. In the case of FIG. 6, the widths I and II on both sides of the drain electrode are narrowed by increasing the width V while keeping the width D constant.
本発明の実施例として、画素電極と共通電極が対向する異なる基板上にそれぞれ形成されているＴＮ型液晶表示装置において説明されたが、第１の基板（アレイ基板）上にゲート線、データ線、画素電極と共に共通電極が形成される液晶表示装置のＴＦＴ構造にも適用できることは明らかであり、即ち、ＴＮ、ＩＰＳ、ＦＦＳ、ＭＶＡ型の液晶表示装置に適用できるものである。 As an embodiment of the present invention, the TN liquid crystal display device in which the pixel electrode and the common electrode are respectively formed on different substrates has been described, but the gate line and the data line are formed on the first substrate (array substrate). It is apparent that the present invention can be applied to a TFT structure of a liquid crystal display device in which a common electrode is formed together with a pixel electrode, that is, it can be applied to a TN, IPS, FFS, or MVA type liquid crystal display device.
１０・・・ゲート線
１０ａ・・ゲート線突出部
２０・・・データ線
３０・・・アモルファス半導体パッチ
４０・・・ドレイン電極
５０・・・ソース電極
６０・・・画素電極
６０ａ・・蓄積容量部
DESCRIPTION OF
Claims (2)
前記第１の基板上でマトリックス状に配置された、表示領域を画成しているゲート線とデータ線、
前記第１の基板上で、前記ゲート線とデータ線の交点各々に規定された画素領域内に形成された画素電極、
前記第１又は第２の基板上で、前記画素電極との間に液晶駆動電圧を印加するよう形成された共通電極、
前記表示領域の外側に設けられ、前記ゲート線各々を順次走査するよう、前記ゲート線にゲート信号を印加するゲートドライバ、
前記表示領域の外側に設けられ、前記データ線各々にデータ信号を印加するデータドライバ、及び
前記画素領域各々に設けられたＴＦＴ素子であって、前記ゲート線上のゲート信号によってオンになったとき、前記データ線上のデータ信号を前記画素電極に印加するＴＦＴ素子とからなるアクティブマトリックス液晶表示装置において、
前記ＴＦＴ素子は、前記ゲート線上に配置されたアモルファス半導体パッチ、前記パッチ上に配置されたドレイン電極とソース電極とからなり、
前記ドレイン電極の形状は、互いに向き合う第１及び第２の側面、前記第１及び第２の側面を接続する第３の側面、並びに第１乃至第３の辺によって囲まれたへこみ部分を含む凹形であり、
前記ソース電極の少なくとも一部は、前記ドレイン電極のへこみ部分に入り、
前記ＴＦＴ素子は、前記ゲートドライバから第１の距離で配置されている第１のＴＦＴ素子及び前記ゲートドライバから第１の距離より長い第２の距離で配置されている第２のＴＦＴ素子を含み、
前記第２のＴＦＴ素子が前記第１のＴＦＴ素子より大きいゲート・ソース寄生容量を有するように、前記第２のＴＦＴ素子のソース電極の幅は前記第１のＴＦＴ素子のソース電極の幅より広く、
前記第２のＴＦＴ素子のチャネルギャップＬ″が前記第１のＴＦＴ素子のチャネルギャップＬ′と同じになるように、前記第２のＴＦＴ素子のドレイン電極の第１及び第２の辺の幅は、前記第１のＴＦＴ素子のドレイン電極の第１及び第２の辺の幅より狭くて、前記第２のＴＦＴ素子のドレイン電極の第３の辺の幅は、前記第１のＴＦＴ素子のドレイン電極の第３の辺の幅より狭く、
前記第２のＴＦＴ素子のチャネル幅Ｗ″が前記第１のＴＦＴ素子のチャネル幅Ｗ′と同じになるように、前記第２のＴＦＴ素子のドレイン電極の第１及び第２の辺の長さは、前記第１のＴＦＴ素子のドレイン電極の第１及び第２の辺の長さより短く、
前記第１及び第２のＴＦＴ素子のドレイン電極が同じ幅Ｄを有するように、前記第２のＴＦＴ素子のドレイン電極の第１及び第２の辺は、前記第１のＴＦＴ素子のドレイン電極の第１及び第２の辺より長い距離互いに離れて配置されているアクティブマトリックス液晶表示装置。 A liquid crystal disposed between the first and second substrates;
The first are arranged in a matrix form on a substrate, a gate line that defines a display area and a data line,
The first on the substrate, the gate line and the data line intersections each defined pixel pixel electrodes formed in the region of,
The first or second substrate, a common electrode formed so as to apply a liquid crystal driving voltage between the pixel electrode,
Wherein provided on the outside of the display area, so as to sequentially scan the gate lines, respectively, a gate driver applying a gate signal to the gate line,
Wherein provided on the outside of the display area, the data driver for applying data signals to the data lines, respectively, and
A TFT element provided in the pixel region respectively, when turned on by the gate signal of the gate line, the active matrix liquid crystal display device comprising a TFT element for applying a data signal of the data line to the pixel electrode In
The TFT element, the amorphous semiconductor patch disposed on the gate line, composed of a drain electrode and a source electrode disposed on said patch,
The drain electrode has a concave shape including a first and second side surfaces facing each other, a third side surface connecting the first and second side surfaces, and a recessed portion surrounded by the first to third sides. Is a shape,
At least a portion of the source electrode enters a recessed portion of the drain electrode;
The TFT element includes a first TFT element disposed at a first distance from the gate driver and a second TFT element disposed at a second distance longer than the first distance from the gate driver. ,
The width of the source electrode of the second TFT element is wider than the width of the source electrode of the first TFT element so that the second TFT element has a larger gate-source parasitic capacitance than the first TFT element. ,
The width of the first and second sides of the drain electrode of the second TFT element is such that the channel gap L ″ of the second TFT element is the same as the channel gap L ′ of the first TFT element. The width of the third side of the drain electrode of the second TFT element is smaller than the width of the first and second sides of the drain electrode of the first TFT element, and the width of the third side of the drain electrode of the second TFT element is the drain of the first TFT element. Narrower than the width of the third side of the electrode,
The lengths of the first and second sides of the drain electrode of the second TFT element so that the channel width W ″ of the second TFT element is the same as the channel width W ′ of the first TFT element. Is shorter than the length of the first and second sides of the drain electrode of the first TFT element,
The first and second sides of the drain electrode of the second TFT element have the same width D so that the drain electrodes of the first and second TFT elements have the same width D. An active matrix liquid crystal display device which is disposed apart from each other by a distance longer than the first and second sides .
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005192589A JP4856399B2 (en) | 2005-06-30 | 2005-06-30 | TFT element electrode shape of liquid crystal display device |
| KR1020050078211A KR101166830B1 (en) | 2005-06-30 | 2005-08-25 | active matrix liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005192589A JP4856399B2 (en) | 2005-06-30 | 2005-06-30 | TFT element electrode shape of liquid crystal display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007011056A JP2007011056A (en) | 2007-01-18 |
| JP4856399B2 true JP4856399B2 (en) | 2012-01-18 |
Family
ID=37749647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005192589A Expired - Fee Related JP4856399B2 (en) | 2005-06-30 | 2005-06-30 | TFT element electrode shape of liquid crystal display device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP4856399B2 (en) |
| KR (1) | KR101166830B1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090054572A (en) | 2007-11-27 | 2009-06-01 | 삼성전자주식회사 | Display device |
| CN101750826B (en) * | 2009-12-28 | 2011-09-14 | 深超光电（深圳）有限公司 | Pixel structure |
| KR102097024B1 (en) | 2013-01-04 | 2020-04-06 | 삼성디스플레이 주식회사 | Thin film transistor array panel |
| KR102128969B1 (en) | 2014-02-17 | 2020-07-02 | 삼성디스플레이 주식회사 | Liquid crystal display and method of manufacturing the same |
| TWI545381B (en) * | 2014-05-21 | 2016-08-11 | 群創光電股份有限公司 | Display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05232512A (en) * | 1992-02-25 | 1993-09-10 | Sanyo Electric Co Ltd | Liquid crystal display device |
| JP2001075127A (en) * | 1999-09-03 | 2001-03-23 | Matsushita Electric Ind Co Ltd | Active matrix type liquid crystal display element and its manufacturing method |
| JP2002072250A (en) * | 2000-04-24 | 2002-03-12 | Matsushita Electric Ind Co Ltd | Display device and driving method thereof |
| KR20020042898A (en) * | 2000-12-01 | 2002-06-08 | 구본준, 론 위라하디락사 | Liquid crystal display device and method of manufacturing thereof |
| TWI287132B (en) * | 2001-11-23 | 2007-09-21 | Chi Mei Optoelectronics Corp | A liquid crystal display having reduced flicker |
-
2005
- 2005-06-30 JP JP2005192589A patent/JP4856399B2/en not_active Expired - Fee Related
- 2005-08-25 KR KR1020050078211A patent/KR101166830B1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| KR20070003497A (en) | 2007-01-05 |
| JP2007011056A (en) | 2007-01-18 |
| KR101166830B1 (en) | 2012-07-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10901442B2 (en) | Active-matrix substrate, display panel and display device including the same | |
| KR101369587B1 (en) | Liquid crystal display device | |
| JP4969568B2 (en) | Display device | |
| US8614658B2 (en) | Liquid crystal display | |
| US20060066553A1 (en) | Active matrix display device with dc voltage compensation based on measurements on a plurality of measurement pixels outside the display area | |
| WO2006098176A1 (en) | Active matrix substrate and display device using the same | |
| EP1972989A3 (en) | Active matrix display substrate having tailored subpixel auxiliary capacitances according to colour | |
| JP2003075871A (en) | Liquid crystal display element | |
| KR20070060757A (en) | Display device and driving apparatus thereof | |
| JP4860233B2 (en) | Flicker prevention adjustment method for liquid crystal display device | |
| JP4592384B2 (en) | Liquid crystal display | |
| JP4856399B2 (en) | TFT element electrode shape of liquid crystal display device | |
| KR20170118997A (en) | Display apparatus | |
| JP2556253B2 (en) | Liquid crystal display | |
| KR101148563B1 (en) | Liquid crystal display device | |
| US10928694B2 (en) | Active matrix substrate and liquid crystal display device | |
| KR20080040953A (en) | Controlling method for preventing flickering of liquid crystal display device | |
| JPH11282014A (en) | Active matrix type liquid crystal display device | |
| KR100447225B1 (en) | Apparatus of Liquid Crystal Display Device | |
| JPH07175453A (en) | Liquid crystal display device | |
| KR20060029101A (en) | Thin film transistor array substrate | |
| KR100789089B1 (en) | Liquid crystal display device | |
| KR100922296B1 (en) | Liquid crystal display device | |
| JPH0829751A (en) | Liquid crystal display device | |
| KR101327870B1 (en) | A liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080618 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110411 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110418 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110719 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111005 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111028 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141104 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4856399 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |