KR100789089B1 - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device having improved image quality by compensating kickback voltage is disclosed.

According to the present invention, the kickback voltage can be compensated by arranging two thin film transistors, two pixel electrodes, and the pixel electrode bars of the pixel in a symmetrical structure. The pixel electrode bars may be arranged in the horizontal direction or the vertical direction. In order to form the storage capacitor, the common electrode may be formed to overlap the pixel electrode and a part of the pixel electrode bar, or a part of the pixel electrode may overlap the gate line.

LCD, Kickback Voltage, Thin Film Transistor, Symmetry, Pixel Electrode Bar

Description

Liquid crystal display device

1 is an equivalent circuit for a unit pixel in a conventional liquid crystal display device.

2 is a diagram illustrating a voltage distortion caused by a kickback voltage.

3 is an equivalent circuit diagram of a unit pixel in the liquid crystal display of the present invention.

FIG. 4 is an equivalent circuit diagram in which unit pixels of the liquid crystal display of FIG. 3 are enlarged to m × n. FIG.

5A and 5B are waveform diagrams illustrating gate voltages for driving the liquid crystal display of FIG. 3.

6A and 6B are a plan view and a cross-sectional view of a liquid crystal display according to a first embodiment of the present invention.

7A and 7B are a plan view and a cross-sectional view of a liquid crystal display according to a second embodiment of the present invention.

8A and 8B are a plan view and a cross-sectional view of a liquid crystal display according to a third embodiment of the present invention.

9A and 9B are a plan view and a cross-sectional view of a liquid crystal display according to a fourth embodiment of the present invention.

Fig. 10 is an equivalent circuit diagram of a liquid crystal display device having m × n unit pixels of the present invention.

12 is a plan view illustrating unit pixels of a liquid crystal display according to a fourth exemplary embodiment of the present invention.

13A and 13B are cross-sectional views taken along lines II ′ and II-II ′ of unit pixels of the LCD of FIG. 12, respectively.

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device for compensating kickback voltage.

A liquid crystal display device is a display device that obtains a desired image by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and controlling the amount of light transmitted through the substrate by controlling the intensity of the electric field.

A plurality of gate lines parallel to each other and a plurality of data lines insulated from and intersecting the gate lines are formed on the substrate of the liquid crystal display, and one pixel is defined by the gate lines and the data lines. A thin film transistor TFT is formed at a portion where the gate line and the data line of each pixel cross each other.

1 shows an equivalent circuit for a unit pixel in a conventional liquid crystal display.

As illustrated in FIG. 1, the gate electrode, the source electrode, and the drain electrode of the thin film transistor 10 are connected to the gate line, the data line, and the pixel electrode P, respectively. A liquid crystal material is formed between the pixel electrode P and the common electrode Com, which is equivalently represented as the liquid crystal capacitor Clc. In addition, the storage capacitor Cst is formed between the pixel electrode P and the common electrode Com, and the parasitic capacitance Cgd is generated between the gate electrode and the drain electrode due to misalignment.

The operation of such a liquid crystal display will be described as follows.

First, as shown in FIG. 2, the thin film transistor 10 is turned on by applying a gate high voltage to a gate electrode connected to a gate line to be displayed, and then a data voltage Vd + representing an image signal is applied to the source electrode. This data voltage is applied to the drain electrode.

Then, the data voltage Vd + is applied to the liquid crystal capacitor Clc and the storage capacitor Cst through the pixel electrode P, respectively, and an electric field is formed by the potential difference between the pixel electrode P and the common electrode Com. do. Since the liquid crystal deteriorates when an electric field in the same direction is continuously applied to the liquid crystal material, the liquid crystal display drives the image signal to be repeated positively and negatively with respect to the common voltage Vcom to prevent deterioration of the liquid crystal.

On the other hand, when the thin film transistor 10 is turned on, the voltage applied to the liquid crystal capacitor Clc and the storage capacitor Cst should be maintained even after the thin film transistor 10 is turned off, but between the gate electrode and the drain electrode. Due to the parasitic capacitance Cgd existing at, distortion occurs in the voltage applied to the pixel electrode P. FIG. The distorted voltage is referred to as kick-back (ΔV), and the kickback voltage (ΔV) is represented by Equation 1 below.

Here, ΔVg means a change amount of the gate voltage, that is, a difference value Vgon-Vgoff between the gate high voltage and the gate low voltage.

This voltage distortion always acts in the direction of lowering the voltage of the pixel electrode P regardless of the polarity of the data voltage Vd.

As shown by a dotted line in FIG. 2, in an ideal liquid crystal display device, the data voltage Vd is applied to the pixel electrode P when the gate high voltage Vgon is applied, so that the data is turned off even when the gate voltage Vg is turned off. The voltage Vd is maintained. However, in the actual liquid crystal display device, as shown by the solid line of FIG. 2, in the part where the gate voltage Vg is changed from on to off, the voltage Vp of the pixel electrode is caused by the kickback voltage ΔV due to the parasitic capacitance Cgd. As much as descend.

Therefore, the maximum data voltage applied when driving each cell of the liquid crystal requires a voltage higher than the operating range of the liquid crystal cell. In order to apply the liquid crystal voltage having the same magnitude as that of the liquid crystal voltage applied in the odd frame during the inversion driving, even in the even frame The common voltage Vcom should be applied to the common electrode in consideration of the kickback effect due to the parasitic capacitance Cgd of the transistor. As such, the kickback voltage may be compensated to a certain degree by adjusting the common voltage.

However, in the conventional LCD, since it is difficult to optimize the design so that the parasitic capacitance Cgd of each cell remains the same, the kickback voltage ΔV of each cell is different. As described above, since different kickback voltages are generated for each cell over the entire liquid crystal panel, even when the common voltage is constantly applied, the common voltage is not maintained at the center value of the pixel voltage, and thus the voltage of the voltage charged in the pixel on a frame basis. The value is changed and flicker occurs accordingly. This phenomenon becomes even more problematic as the screen of the liquid crystal display becomes larger and the gate lines become longer.

In addition, the liquid crystal display of the related art may generate an afterimage or a stain due to the kickback voltage.

An object of the present invention is to provide a liquid crystal display device having a novel electrode structure that compensates for kickback voltage.

Another object of the present invention to provide a liquid crystal display device having a symmetric electrode structure, which can improve the image quality.

Another object of the present invention is to provide a liquid crystal display device which can improve luminance by maximizing the aperture ratio.

According to a first embodiment of the present invention for achieving the above object, a liquid crystal display device is composed of a plurality of pixels arranged in a matrix form for displaying an image, each pixel is arranged in a first direction First and second gate lines; First and second data lines arranged in a second direction perpendicular to the second gate line; A first thin film transistor connected to the first gate line and the first data line; A second thin film transistor connected to the second gate line and the second data line; A first pixel electrode connected to the first thin film transistor and having a plurality of pixel electrode bars; And a second pixel electrode connected to the second thin film transistor and alternately arranged with the pixel electrode bar of the first pixel electrode.

According to a second embodiment of the present invention, a liquid crystal display device is composed of a plurality of pixels arranged in a matrix form for displaying an image, each of the pixels, the first and second gate lines arranged in a first direction ; First and second data lines arranged in a second direction perpendicular to the second gate line and bent at a predetermined slope; A first thin film transistor connected to the first gate line and the first data line; A second thin film transistor connected to the second gate line and the second data line; A first pixel electrode connected to the first thin film transistor and having a plurality of pixel electrode bars; And a second pixel electrode connected to the second thin film transistor and arranged alternately with the pixel electrode bar of the first pixel electrode, wherein the outermost pixel electrode bar of the first pixel electrode and the outermost pixel electrode of the second pixel electrode are arranged. A bar overlaps each of the first and second data lines.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3 shows an equivalent circuit diagram of a unit pixel in the liquid crystal display of the present invention.

As shown in FIG. 3, the first and second gate lines GL1 and GL2 are arranged in parallel to be spaced apart from each other in a first direction (eg, in a horizontal direction). The first and second data lines DL1 and DL2 are arranged in parallel to be spaced apart from each other by a predetermined interval in the second direction (eg, the vertical direction).

A unit pixel is defined by the first and second gate lines GL1 and GL2 and the first and second data lines DL1 and DL2.

The unit pixels are driven by two thin film transistors 20 and 30 provided in pairs. In the first thin film transistor 20, a gate electrode is connected to the first gate line GL1, a source electrode is connected to the first data line DL1, and a drain electrode is connected to the first pixel electrode 22. In the second thin film transistor 30, a gate electrode is connected to the second gate line GL2, a source electrode is connected to the second data line DL2, and a drain electrode is connected to the second pixel electrode 32. The first and second pixel electrodes 22 and 32 are formed on the same plane.

In this case, the first and second thin film transistors 20 and 30 and the first and second pixel electrodes 22 and 32 are arranged symmetrically with each other. The parasitic capacitance, the storage capacitance, and the liquid crystal capacitance also have the same value due to the symmetrically arranged first and second thin film transistors 20 and 30 and the first and second pixel electrodes 22 and 32 ( Cgd1 = Cgd2, Cst1 = Cst2, Clc1 = Clc2).

In order to drive the unit pixel configured as described above, the first gate line GL1 and the second gate line GL2 must be simultaneously activated.

To this end, as illustrated in FIG. 5A, the first gate voltage Vg1 applied to the first gate line GL1 and the second gate voltage Vg2 applied to the second gate line GL2 are 2 per frame, respectively. High level signals. The high level signal after the first gate voltage Vg1 and the high level signal before the second gate voltage Vg2 overlap a predetermined period. Preferably, the rear high level signal of the first gate voltage Vg1 and the front high level signal of the second gate voltage Vg2 have the same width.

As shown in FIG. 5B, the first gate voltage Vg1 applied to the first gate line GL1 and the second gate voltage Vg2 applied to the second gate line GL2 are each one high per frame. The level signal is generated. In this case, the second gate voltage Vg2 is generated to overlap a portion of the high level signal section of the first gate voltage Vg1 with a predetermined section. For example, the front high level signal section of the second gate voltage Vg2 may overlap the high level signal section of the second gate voltage Vg1.

Therefore, the first and second thin film transistors 20 and 30 are turned on at the same time by the first gate voltage Vg1 and the second gate voltage Vg2. The first data voltage input to the first data line DL1 is applied to the first pixel electrode 22 via the first thin film transistor 20. The second data voltage input to the second data line DL2 is applied to the second pixel electrode 32 via the second thin film transistor 30.

Therefore, an electric field is generated by a potential difference between the first data voltage applied to the first pixel electrode 22 and the second data voltage applied to the second pixel electrode 32, and the liquid crystal molecules are displaced by the electric field. The desired image can be obtained.

In a conventional general liquid crystal display, an image is displayed by a potential difference between a data voltage and a common voltage in a unit pixel, whereas in the present invention, the first pixel electrode 22 and the second pixel electrode 32 provided per unit pixel are provided. The first and second data voltages are applied, and an image is displayed by the difference value between these data voltages.

Meanwhile, the first data voltage input to the first data line DL1 is formed between the gate electrode and the drain electrode of the first thin film transistor 20 at the point where the first gate voltage Vg1 is changed from the high level to the low level. The voltage is dropped by the first kickback voltage ΔV1 due to the first parasitic capacitance Cgd1 to become the first pixel voltage Vp1. Similarly, the second data voltage input to the second data line DL2 is formed between the gate electrode and the drain electrode of the second thin film transistor 20 at the point where the second gate voltage Vg2 is changed from the high level to the low level. The second kickback voltage ΔV2 is decreased by the second parasitic capacitance Cgd2 to become the second pixel voltage Vp2.

In this case, the first and second kickback voltages ΔV1 and ΔV2 are represented by Equations 2 and 3 below.

As described above, since the first and second thin film transistors 20 and 30 and the first and second pixel electrodes 22 and 32 are arranged symmetrically with each other, the parasitic capacitance, the auxiliary capacitance, and the liquid crystal capacitance are increased. Since the first and second gate voltages have the same value (Cgd1 = Cgd2, Cst1 = Cst2, Clc1 = Clc2) and the amount of change of the first and second gate voltages is the same (ΔVg1 = ΔVg2), the first and second kickback voltages have the same value. (ΔV1 = ΔV2).

Therefore, since the liquid crystal voltage Vlc substantially applied to the liquid crystal is determined by the difference ΔV1-ΔV2 between the first and second kickback voltages, the liquid crystal voltage Vlc has a zero value. Therefore, since the kickback voltage is compensated, flicker, afterimage or spots are not generated, and the image quality can be improved.

FIG. 4 is an equivalent circuit diagram in which unit pixels of the liquid crystal display of FIG. 3 are enlarged to m × n. FIG.

As illustrated in FIG. 4, gate electrodes of the thin film transistors 20 and 30 provided in the adjacent pixels P1 and P2 are connected to one gate line GL2. Similarly, a source electrode of each of the thin film transistors 20 and 30 provided in the adjacent pixels P1 and P3 is connected to one data line DL2.

Accordingly, each of the m × n unit pixels has adjacent first and second gate lines GL1 and GL2 and first and second data lines DL1 and DL2 vertically intersecting the gate lines GL1 and GL2. ) Is arranged and connected to the first thin film transistor 20, the second gate line GL2, and the second data line DL2 connected to the first gate line GL1 and the first data line DL1. The second thin film transistors 30 connected to each other are symmetrically arranged, and the first pixel electrode 22 connected to the first thin film transistor 20 and the second pixel electrode 32 connected to the second thin film transistor 30 are connected. ) Are formed symmetrically arranged with each other.

In this case, the first and second thin film transistors 20 and 30 are turned on by the high level signals simultaneously applied to the adjacent first and second gate lines GL1 and GL2. Accordingly, a first data voltage is applied to the first pixel electrode 22 through the first thin film transistor 20 and second data to the second pixel electrode 32 via the second thin film transistor 30. Voltage is applied. In this case, since the first and second thin film transistors 20 and 30 and the first and second pixel electrodes 22 and 32 are arranged symmetrically with each other, the first and second kickback voltages have the same value ΔV1. Since the first and second kickback voltages ΔV1 and ΔV2 cancel each other, the liquid crystal voltage Vlc applied to the liquid crystal is substantially independent of the first and second kickback voltages ΔV1 and ΔV2. The potential difference between the first and second data voltages is determined. Therefore, the desired image can be obtained accurately regardless of the kickback voltage, and the image quality can be improved.

Hereinafter, the liquid crystal display of the present invention as described above will be described with reference to the practical layout.

6A and 6B show a plan view and a cross-sectional view of a liquid crystal display according to a first embodiment of the present invention.

As shown in FIG. 6A, the plurality of gate lines 24 to 26 are arranged in parallel so as to be spaced apart at regular intervals along the horizontal direction. A plurality of data lines 27 to 29 are arranged in parallel so as to be spaced apart at regular intervals along a vertical direction perpendicular to the gate lines 24 to 26. The unit pixel P is defined by the gate lines 24 to 26 and the data lines 27 to 29.

The unit pixel P includes two thin film transistors 20 and 30 connected to two adjacent gate lines 24 and 25 and two adjacent data lines 27 and 28. For example, the first gate line 24 and the first data line 27 are connected to the first thin film transistor 20, and the second gate line 25 and the second data line are connected to the second thin film transistor 30. 28 may be connected. Alternatively, the first gate line 24 and the second data line 28 may be connected to the first thin film transistor 20, and the second gate line 25 and the first data line may be connected to the second thin film transistor 30. 27) may be connected.

The first pixel electrode 22 is integrally formed with a plurality of pixel electrode bars 22a having one side connected to the first thin film transistor 20 and protruding vertically toward the other side. The second pixel electrode 32 includes a plurality of pixel electrode bars 32a having one side connected to the second thin film transistor 30 and alternately arranged with the pixel electrode bars 22a of the first pixel electrode 22 on the other side. ) Is integrally formed.

Accordingly, since the first thin film transistor 20 and the second thin film transistor 30 are symmetric in a diagonal direction, the first and second pixel electrodes 22 and 22 respectively connected to the first and second thin film transistors 20 and 30, respectively. Each of the pixel electrode bars 22a and 32a provided at 32 may also be arranged symmetrically. As such, the first and second thin film transistors 20 and 30 and the first and second pixel electrodes 22 and 32 and pixel electrode bars 22a and 32a are symmetrically formed to form the first thin film transistor. By canceling the kickback voltage on the side of the (20) side and the kickback voltage on the side of the second thin film transistor 30, substantially no kickback voltage is reflected in the voltage Vlc applied to the liquid crystal, so that image quality improvement can be expected.

The common electrode 34 is the first pixel electrode 22, the outermost pixel electrode bar 22a of the first pixel electrode 22, the second pixel electrode 32, and the second pixel electrode 32. By overlapping the outermost pixel electrode bar 32a with the insulating material therebetween, a predetermined storage capacitor Cst is formed.

6B will be described with reference to FIG. 6B. A plurality of gate lines 24 to 26 spaced apart from each other by a predetermined interval are formed on the substrate 41.

Hereinafter, the description will be limited to unit pixels for convenience of description, but the description may be extended to all unit pixels. Accordingly, the first and second gate lines 24 and 25 are formed on the substrate 41 at predetermined intervals. In addition, the common electrode 34 is formed in the unit pixel on the same plane as the plurality of gate lines 24 and 25.

In the present invention, the gate electrode constituting the thin film transistor is not separately formed, but a method of forming the thin film transistor on the gate line is provided as an example. However, the thin film transistor may be formed by protruding the gate electrode from the gate line into the unit pixel. have. Through the method of directly forming the thin film transistor on the gate line as in the present invention, the aperture ratio can be further improved.

An insulating layer 44 is formed from an insulating material applied on the first and second gate lines 24 and 25. Subsequently, semiconductor layers 45 and 46 formed of an active layer and an ohmic contact layer are formed on the first and second gate lines 24 and 25 including the insulating layer 44. Next, first and second data lines 27 and 28 are formed on the substrate 41 including the semiconductor layers 45 and 46 to be perpendicular to the first and second gate lines 24 and 25. Source electrodes 42a and 43a and drain electrodes 42b and 43b are formed on the semiconductor layers 45 and 46. Accordingly, the first thin film transistor 20 including the first gate line 24, the semiconductor layer 45, the source electrode 42a, and the drain electrode 42b is formed, and the second gate line 25 and the semiconductor layer are formed. A second thin film transistor 30 composed of the 46, the source electrode 43a and the drain electrode 43b is formed.

A protective layer 47 is formed on the substrate 41 including the source electrodes 42a and 43a and the drain electrodes 42b and 43b, and is not shown in FIG. 6B, but is disposed on the drain electrodes 42b and 43b. The formed protection layer 47 is removed to form a contact hole (not shown).

The pixel electrode bars 22a of the first and second pixel electrodes 22 and 32, the pixel electrode bars 22a of the first pixel electrode 22, and the pixel electrode bars of the second pixel electrode 32 are formed on the passivation layer 47. 32a) is formed. In this case, the pixel electrode bars 22a of the first pixel electrode 22 and the pixel electrode bars 32a of the second pixel electrode 32 are alternately arranged. In addition, the first pixel electrode 22 is connected to the drain electrode 42b of the first thin film transistor 20 through the contact hole, and the second pixel electrode 32 is the second thin film transistor 30. Is connected to the drain electrode 43b.

In the above, the storage capacitor Cst is formed by overlapping the common electrode 34 with the pixel electrodes 22 and 32 and the pixel electrode bars 22a and 32a. However, the storage capacitor Cst may be removed even if necessary. May be formed.

As shown in FIGS. 7A and 7B, in the second embodiment of the present invention, a pixel electrode is formed to overlap a predetermined region with some gate lines to form a storage capacitor. The pixel electrodes 48 and 49 of FIGS. 7A and 7B may be designed to have a larger area than the pixel electrodes 22 and 32 of FIGS. 6A and 6B.

Accordingly, the second embodiment of the present invention overlaps the pixel electrodes 48 and 49 with some regions of the gate lines 24 and 25 without the common electrode 34 shown in FIGS. 6A and 6B. The storage capacitor Cst may be formed through an insulating medium between the 24 and 25 and the pixel electrodes 48 and 49. Therefore, the cost is reduced and a simpler pixel can be formed by not using the common electrode, and the aperture ratio can be improved by removing the common electrode in the pixel P. FIG.

Reference numerals 48a and 49a denote a plurality of pixel electrode bars of the first pixel electrode 48 and a plurality of pixel electrode bars of the second pixel electrode 49, respectively.

In the first and second embodiments of the present invention described above, the pixel electrode bars 22a and 48a of the first pixel electrodes 22 and 48 and the pixel electrode bars 32a and 49a of the second pixel electrodes 32 and 49 are described. These were formed alternately in the longitudinal direction.

In addition, the pixel electrode bars of the first pixel electrode and the pixel electrode bars of the second pixel electrode may have a symmetrical structure even if they are alternately arranged in the horizontal direction.

8A and 8B show a plan view and a cross-sectional view of a liquid crystal display according to a third embodiment of the present invention.

8A and 8B are the same except for the arrangement direction of the pixel electrode bars as shown in FIGS. 6A and 6B. That is, as shown in FIGS. 8A and 8B, the unit pixel P is defined by the adjacent first and second gate lines 24 and 25 and the first and second data lines 27 and 28. . The unit pixel P includes two thin film transistors 20 and 30 which are symmetrical to each other. The first thin film transistor 20 is connected to the first gate line 24 and the first data line 27, and the second thin film transistor 30 is connected to the second gate line 25 and the second gate line. 2 is connected to the data line 28.

In addition, a first pixel electrode 22 may be connected to the first thin film transistor 20, and a second pixel electrode 32 may be connected to the second thin film transistor 30. In this case, a plurality of pixel electrode bars 22a are integrally formed in the horizontal direction on the first pixel electrode 22, and pixel electrode bars of the first pixel electrode 22 are formed on the second pixel electrode 32. Pixel electrode bars 32a arranged alternately with 22a are integrally formed.

In addition, the common electrode 34 is formed to overlap the first and second pixel electrodes 22 and 32 and the outermost pixel electrode bars 22q and 32a to form the storage capacitor Cst.

As described above, the parasitic capacitance Cgd is mainly formed by symmetrically forming the first and second thin film transistors 20 and 30 and the pixel electrode bars 22a and 32a of the first and second pixel electrodes 22 and 32. Image quality can be improved by removing kickback voltage caused by.

9A and 9B, in the fourth embodiment of the present invention, the pixel electrode bars 48a and 49a of the first and second pixel electrodes 48 and 49 are symmetric to each other in the horizontal direction. The arrangement is the same as the third embodiment of the present invention described above. However, in the fourth exemplary embodiment of the present invention, unlike the third exemplary embodiment in which the common electrode 34 is used, the first and second pixel electrodes 48 and 49 are enlarged to respectively enlarge the first and second gates. By overlapping portions of the lines 24 and 25, the storage capacitor Cst can be formed without the common electrode. Accordingly, since the common electrode is not used, the cost can be reduced, and the aperture ratio corresponding to the area occupied by the common electrode can be secured to improve the image quality.

In the above description, as illustrated in FIG. 4, two thin film transistors respectively provided to pixels adjacent to one gate line between the adjacent pixels up and down are connected. For example, the second thin film transistor 30 of the first pixel P1 and the first thin film transistor 20 of the second pixel P2 may be connected to the second gate line GL2.

In contrast, as illustrated in FIG. 10, a pixel is defined by a plurality of gate lines GL1 to GLm and data lines DL1 to DLn. At this time, the pixels P1 and P2 adjacent to each other up and down are divided by two gate lines GL'1 and GL2. For example, the first pixel P1 may include the first thin film transistor 20, the second gate line GL′1, and the second data line DL2 connected to the first gate line GL1 and the first data line DL1. It includes a second thin film transistor 30 connected to). The second pixel P2 is connected to the first thin film transistor 20, the second gate line GL′2, and the second data line DL2 connected to the first gate line GL2 and the first data line DL1. And a second thin film transistor 30 connected thereto.

In this case, two gate lines GL'1 and GL2 or GL2 and GL'3 are provided between the first and second pixels P1 and P2 adjacent to each other. Therefore, one gate line GL'1 of the two gate lines GL'1 and GL2 provided between the first and second pixels P1 and P2 is a second thin film of the first pixel P1. The other gate line GL2 may be connected to the transistor 30 and may be connected to the first thin film transistor 20 of the second pixel P2.

In this manner, all the unit pixels shown in FIG. 10 may be configured.

When gate high voltages are simultaneously applied to the first and second gate lines GL1 and GL'1 in order to drive the first pixel P1, the first and the first and second gate lines GL1 and GL'1 connected to the gate lines GL1 and GL'1. 2 As the thin film transistors 20 and 30 are turned on, a first data voltage is applied to the first pixel electrode 22 connected to the first thin film transistor 20 and the second pixel connected to the second thin film transistor 30. The second data voltage is applied to the electrode 32. Thus, an electric field corresponding to the potential difference between the second data voltage and the first data voltage is generated and the light transmittance is adjusted by this electric field to obtain a desired image. In this case, the thin film transistor, the pixel electrode, and the pixel electrode bars are symmetrically arranged, so that the first and second kickback voltages generated by the parasitic capacitance Cgd between the gate electrode and the drain electrode of each of the first and second thin film transistors. This offset can be suppressed to prevent flicker, afterimage, and the like, thereby improving image quality.

However, as shown in FIG. 11, the outermost pixel electrode bars 22a of the first data line 27 and the first pixel electrode 22 and the first data line 27 and the second pixel electrode 32 are shown. The parasitic capacitances Cdp1 and Cdp2 are not the same and the outermost pixel electrode bars of the second data line 28 and the first pixel electrode 22 are different because the distances between the outermost pixel electrode bars 32a of the same are different. The parasitic capacitances Cdp3 and Cdp4 do not become the same as the distance between the 22a and the second data line 28 and the outermost pixel electrode bar 32a of the second pixel electrode 32 is different, thereby making the pixel field It may cause distortion.

It will be appreciated that the above description for convenience of description will not be described.

12 is a plan view illustrating unit pixels of a liquid crystal display according to a fourth exemplary embodiment of the present invention, and FIGS. 13A and 13B are lines II ′ and II− of unit pixels of the liquid crystal display of FIG. 12, respectively. Sectional drawing cut along the II 'line is shown.

12, 13A, and 13B, first and second gate lines 72 and 74 arranged in a horizontal direction are formed on the substrate 54, and the first and second gate lines ( An insulating layer 55 is formed on the substrate 54 including the 72, 74.

First and second thin film transistors 50 and 60 including semiconductor layers 56 and 57, source electrodes 58a and 59a, and drain electrodes 58b and 59b are formed on each gate line 72 and 74. . At the same time, the insulating layer 55 is made of the same material as the source electrodes 58a and 59a and the drain electrodes 58b and 59b and is perpendicular to the first and second gate lines 72 and 74. First and second data lines 82 and 84 arranged in the vertical direction are formed. In this case, the first and second data lines 82 and 84 are formed to be bent with a predetermined slope. Here, the slope is simultaneously overlapped with a part of each of the outermost pixel electrode bars 52a and 62a of the first and second pixel electrodes 52 and 62, which will be described later on the first data line 82, and also the second data. A portion of the outermost pixel electrode bars 52a and 62a of the first and second pixel electrodes 52 and 62 in the line 84 is an inclination for overlapping at the same time. In other words, the pixel electrode bars 52a and 62a of the first and second pixel electrodes 52 and 62 may overlap the first data line 82 or the second data line 84 at the same time. The first and second data lines 82, 84 should be bent with a predetermined slope.

The passivation layer 64 is formed on the substrate 54 including the first and second data lines 82 and 84, wherein each drain electrode of the first and second thin film transistors 50 and 60 is formed. The protective layer 64 formed on the 58b and 59b is removed to form a contact hole.

A transparent material or the like is coated on the protective layer 64 so that the first pixel electrode 52 and the plurality of pixel electrode bars 52a integrally connected thereto and the second pixel electrode 62 and the plurality of pixels integrally connected thereto are provided. Electrode bars 62a are formed respectively. The first and second pixel electrodes 52 and 62 are connected to the drain electrodes 58b and 59b of the first and second thin film transistors 50 and 60 through contact holes, respectively.

The pixel electrode bars 52a of the first pixel electrode 52 and the pixel electrode bars 62a of the second pixel electrode 62 are alternately arranged. In this case, each of the pixel electrode bars 52a and 62a may be bent at the same inclination with the first and second data lines 82 and 84 so that the pixel electrode bars 52a and 62a are arranged in parallel with the first and second data lines 82 and 84. Is formed. In this case, the one outermost pixel electrode bar 52a of the first pixel electrode 52 and the one outermost pixel electrode bar 62a of the second pixel electrode 62 are simultaneously formed on the first data line 82. The second outermost pixel electrode bar 62a overlapping with a portion and the other outermost pixel electrode bar 52a of the first pixel electrode 52 and the other outermost pixel electrode bar 62a of the second pixel electrode 62 simultaneously. It overlaps with part of 84.

In this case, each of the data lines 82 and 84 and the pixel electrode bars 52a and 62a of the pixel electrodes 52 and 62 overlap each other with the protective layer 64 interposed therebetween, thus serving as a storage capacitor Cst. Can be done.

Therefore, the liquid crystal display according to the fourth exemplary embodiment of the present invention overlaps the pixel electrode bars 52a and 62a of the pixel electrodes 52 and 62 with the data lines 82 and 84, thereby separately forming auxiliary capacitances. Since there is no need to form a common electrode for the purpose, the cost can be reduced and the aperture ratio can be improved.

Accordingly, as shown in FIG. 13B, the outermost pixel electrode bar 52a of the first pixel electrode 52 and the outermost pixel electrode bar 62a of the second pixel electrode 62 are formed of the first data line 82, the parasitic capacitance Cdp1 and the second data line 84 between the first data line 82 and the outermost pixel electrode bar 52a of the first pixel electrode 52 may be overlapped with each other. The parasitic capacitance Cdp2 between the outermost pixel electrode bars 62a of the second pixel electrode 62 becomes equal. Therefore, the outermost pixel electrode bar 52a of the first pixel electrode 52 and the outermost pixel electrode bar of the second pixel electrode 62 are formed by the data voltage input to the first data line 82. By 62a) being affected by the same, the image quality can be improved by preventing the pixel field distortion phenomenon.

As described above, according to the present invention, two thin film transistors per pixel and two pixel electrodes connected thereto are symmetrically disposed, thereby compensating kickback voltages and improving image quality.

According to the present invention, the cost can be reduced and the aperture ratio can be improved by not adding a common electrode for forming the storage capacitor.

According to the present invention, pixel field distortion can be prevented by overlapping the pixel electrode bars of each data line and each pixel electrode.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (18)

Made up of a plurality of pixels arranged in a matrix to display an image, Each of the pixels, First and second gate lines arranged in a first direction; First and second data lines arranged in a second direction perpendicular to the second gate line; A first thin film transistor connected to the first gate line and the first data line; A second thin film transistor connected to the second gate line and the second data line; A first pixel electrode connected to the first thin film transistor and having a plurality of pixel electrode bars; And A second pixel electrode connected to the second thin film transistor and alternately arranged with a pixel electrode bar of the first pixel electrode; Liquid crystal display comprising a. The liquid crystal display of claim 1, wherein the pixel electrode bar of the first pixel electrode and the pixel electrode bar of the second pixel electrode are arranged in parallel with the first direction. The liquid crystal display of claim 1, wherein the pixel electrode bar of the first pixel electrode and the pixel electrode bar of the second pixel electrode are arranged in parallel with the second direction. The common electrode of claim 1, wherein the common electrode is arranged to overlap the first pixel electrode and the second pixel electrode to form a storage capacitor. Liquid crystal display device further comprising. The liquid crystal display of claim 1, wherein the first pixel electrode overlaps the first gate line and the second pixel electrode overlaps the second gate line to form a storage capacitor. Made up of a plurality of pixels arranged in a matrix to display an image, Each of the pixels, First and second gate lines arranged in a first direction; First and second data lines arranged in a second direction perpendicular to the second gate line and bent at a predetermined slope; A first thin film transistor connected to the first gate line and the first data line; A second thin film transistor connected to the second gate line and the second data line; A first pixel electrode connected to the first thin film transistor and having a plurality of pixel electrode bars; And A second pixel electrode connected to the second thin film transistor and arranged alternately with a pixel electrode bar of the first pixel electrode; Including, And the outermost pixel electrode bar of the first pixel electrode and the outermost pixel electrode bar of the second pixel electrode overlap each of the first and second data lines. 7. The liquid crystal display of claim 6, wherein each of the pixel electrode bars of the first and second pixel electrodes is bent at the same slope as the first and second data lines. The parasitic capacitance between the first data line and the outermost pixel electrode bar of the first pixel electrode and the parasitic capacitance between the first data line and the outermost pixel electrode bar of the second pixel electrode. Liquid crystal display device characterized in that the same. The parasitic capacitance between the second data line and the other outermost pixel electrode bar of the first pixel electrode and the parasitic capacitance between the second data line and the other outermost pixel electrode bar of the second pixel electrode are the same. Liquid crystal display device characterized in that. 10. The liquid crystal display device according to claim 8 or 9, wherein the parasitic capacitance is used as an auxiliary capacitance for storing an auxiliary data voltage. 7. The liquid crystal display device according to claim 6, wherein the pixel electrode bar of the first pixel electrode and the pixel electrode bar of the second pixel electrode are arranged in parallel with the second direction. 7. The liquid crystal display of claim 6, wherein the first and second gate lines are simultaneously activated by first and second gate voltages. The method of claim 12, wherein each of the first and second gate voltages has two high level signals, and a rear end high level signal of the first gate voltage and a front end high level signal of the second gate voltage overlap a predetermined period. Liquid crystal display device characterized in that. The method of claim 12, wherein the first and second gate voltages each have one high level signal, and the high level signal of the first gate voltage and the high level signal of the second gate voltage overlap each other for a predetermined period. A liquid crystal display device. 7. The liquid crystal display device according to claim 6, wherein a single gate line is provided between the pixels adjacent to each other vertically. The liquid crystal display of claim 15, wherein when the single gate line is provided, different gate voltages are applied to the first and second gate lines in the pixel. 7. The liquid crystal display device according to claim 6, wherein two gate lines are provided between the pixels adjacent to each other vertically. 18. The liquid crystal display device according to claim 17, wherein when the two gate lines are provided, the same gate voltages are applied to the first and second gate lines in the pixel.

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