JPH118386A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress sufficiently short channel effect with a low impurity concn. of the channel region, using not an SOI but a bulk substrate, resulting in the realization of a high performance MOS transistor having a high drive force. SOLUTION: This device comprises a p-well region 2 formed on an Si substrate 1, n-type source-drain region 7 formed apart on the surface of the p-well 2, and gate electrode 6 formed via a gate insulation film 5 on a channel region between the source-drain regions 7. In the substrate beneath the gate electrode an insulation layer 11 which is thinner in the channel length direction than so that the channel region may be separated between the source and the drain side the channel length is disposed, without contacting the substrate surface and the lower end of this layer 11 protrudes from the bottom of a p-well region 3 and reaches a base substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly to a semiconductor device having a MOS field-effect transistor formed on a bulk semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, a MOS type field effect transistor (hereinafter referred to as M
(Abbreviated as OS transistor) is most frequently used. FIGS. 22A to 22C show an example of a manufacturing process of a conventional MOS transistor.

First, as shown in FIG. 1A, B ions are applied to a p-type silicon substrate 1 at 100 keV and 2.0 × 10 4
Implantation is performed at ¹³ cm ^-2 , and thereafter, a heat process is performed at 1190 ° C. for 150 minutes to form a p-well region 2. Subsequently, an element isolation oxide film 3 is formed by the LOCOS method.

Then, as shown in FIG. 22B, in order to obtain a desired threshold voltage in p-well region 2, B
The concentration of the channel surface is adjusted by implanting ions 4 at 15 keV and 1.0 × 10 ¹³ cm ⁻² . Then, the surface of the substrate 1 is oxidized in a 10% HCl atmosphere at 800 ° C. to form a silicon oxide film (gate insulating film) 5 having a thickness of 7 nm.

Next, as shown in FIG. 22C, a 200 nm-thick film is formed on the silicon oxide film 5 by LPCVD.
Is deposited, and the polycrystalline silicon film is selectively etched by RIE to form a gate electrode 6. Subsequently, As ions were added at 50 keV and 5.0 × 10 ¹⁵
The source / drain region 7 made of an n-type layer is formed by implanting at cm ⁻² and passing through a thermal process.

Although not shown hereafter, a silicon oxide film is deposited by an CVD method as an interlayer insulating film, and a contact portion is opened by an RIE method. Then, an aluminum film containing silicon is deposited by a sputtering method, and a wiring is formed by patterning, whereby a MOS transistor is completed.

In this type of MOS transistor, the short channel effect has been suppressed by increasing the impurity concentration in the channel region. for that reason,
In the case of a fine element, the impurity concentration in the channel region must be set higher, and as a result, (1) a decrease in driving force,
This causes problems such as (2) an increase in the threshold voltage, and (3) an increase in the change in the threshold voltage due to the charge sharing effect.

In a fine device, there is an SOI device as one device for making it possible to set the impurity concentration of the channel region to be low. However, in this method, it is difficult to obtain the potential of the substrate. It was difficult to form an element utilizing the effect. Also, SOI
In order to make it possible to sufficiently suppress the short channel effect at a sufficiently low impurity concentration in the device, it is necessary to set the thickness of the silicon layer to be extremely thin, which increases the resistance of the source and drain. There was a problem.

In order to avoid an increase in resistance, there is a method of increasing the thickness by raising the source / drain region by a method such as elevating. In this method, the source / drain region is formed between the source / drain region and the gate electrode. Due to the increased capacity,
There is a problem that the operation speed in the AC operation of the element is reduced. In the SOI element, the source
Immediately below the drain region is silicon oxide and not silicon, so that the subsequent thermal process cannot recover the damage suffered by the silicon layer during the impurity implantation for forming the source / drain region, and the source / drain region and the channel There is also a problem that a leak current tends to flow at a junction with the portion.

As a result, a substrate bias can be obtained, the resistance of the source and the drain is low, the capacitance formed between the source and the drain and the gate is small, and the threshold voltage is extremely high. And the difference in threshold voltage is small compared to long channel devices,
In addition, it is difficult to form a fine element having a small leakage current and a high driving force.

Further, in the MOS transistor having the conventional structure, the well potential is set to the same potential as a whole in at least one element. Therefore, for example, when the substrate bias effect is used, the bias is applied only near the drain while the bias is applied near the source at the same time. This causes an increase in the load due to that portion, and lowers the operation speed in the AC operation. And other inconveniences.

[0012]

As described above, the conventional M
In an OS transistor, when an SOI structure is employed in order to suppress a short channel effect without increasing the impurity concentration of a channel region, resistance of a source and a drain is increased, and capacitance between the source and the drain and the gate is reduced. And the driving force is reduced. In addition, since the well potential is set to the same potential as a whole in at least one element, there is a problem that the substrate bias effect cannot be effectively used.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to use a bulk substrate instead of an SOI and to sufficiently reduce the short channel effect even if the impurity concentration of the channel region is reduced. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can suppress the occurrence of a high-performance fine element having a high driving force.

Another object of the present invention is to provide a high-performance semiconductor device capable of controlling the potential of a well to different values at a plurality of locations and effectively utilizing a substrate bias effect, and a high-performance semiconductor device. It is to provide a manufacturing method.

[0015]

[Means for Solving the Problems]

(Structure) The present invention employs the following structure to solve the above problems. That is, the present invention relates to a semiconductor device in which a gate electrode is formed on a surface of a semiconductor substrate via a gate insulating film, and a source / drain region is formed on a substrate surface portion with a channel region below the gate electrode interposed therebetween. In the substrate under the gate electrode, an insulating layer having a thickness in the channel length direction smaller than the channel length is provided without contacting the substrate surface so as to separate the channel region on the source side and the drain side. Features.

According to the present invention, there is provided a method of manufacturing a semiconductor device having a gate electrode on a surface of a semiconductor substrate with a gate insulating film interposed therebetween, and having source / drain regions on the substrate surface with a channel region below the gate electrode interposed therebetween. Forming an insulating layer near the surface of the substrate, the insulating layer being thinner than a channel region of a MOS field effect transistor to be formed, in a depth direction of the substrate without contacting the substrate surface; Forming a gate electrode and a source / drain region such that a channel region is separated into a source side and a drain side by a layer.

Here, preferred embodiments of the present invention include the following. (1) The insulating layer shall be disposed in a plane parallel to the substrate depth direction and the channel width direction. (2) One or more insulating layers.

(3) The source / drain region is formed on the surface of a well formed in the substrate, and the lower end of the insulating layer protrudes from the bottom of the well to reach the underlying substrate. (4) An electrode connected to the source side of the well and an electrode connected to the drain side of the well are provided separately from the source / drain regions.

(5) A part of the substrate surface sandwiching the gate electrode is etched to a position deeper than the substrate surface below the gate electrode, and the source / drain regions are formed in the etched portion. (6) A part of the substrate surface sandwiching the gate electrode is etched to a position deeper than the substrate surface below the gate electrode, and a semiconductor layer forming a source / drain region is embedded in the etched portion.

(7) As a step of forming an insulating layer near the surface of the substrate, a part of the substrate is selectively etched to form a step on the surface of the substrate, and then the insulating layer is formed on the surface of the substrate including the step. Forming, then etching back the insulating layer to the side of the step, depositing or epitaxially growing a semiconductor to fill the step, and then planarizing the surface of the semiconductor layer.

(8) As a step of forming an insulating layer near the surface of the substrate, the thickness of the substrate in the channel length direction is smaller than the channel length, and a groove extending in the depth direction of the substrate is formed along the channel width direction. After the formation, an insulating layer is buried in the trench, and then a semiconductor layer serving as a channel region of the MOS field-effect transistor is formed on the substrate surface and the insulating layer. (9) After forming a first mask having a stripe opening on a substrate to form a groove, a second mask is formed in a self-aligned manner on the opening side of the mask, and then the first and second masks are formed. Selective etching of the substrate using the second mask.

(Operation) According to the present invention, since the insulating layer is provided immediately below the channel region, punch-through is suppressed by the insulating layer. Therefore, it is possible to set the impurity concentration of the channel region to be low in spite of using the bulk substrate, and it is possible to suppress the threshold voltage from becoming extremely deep and the driving force from being lowered. Further, unlike the SOI element, since it is not necessary to form the source and the drain thinly or to be formed above the channel surface, without increasing the capacitance formed between the source and the drain and the gate, It is possible to reduce the resistance of the source and the drain.

Further, in the present invention, since the lower portions of the source and drain regions are formed of silicon instead of silicon oxide, the damage caused at the time of impurity implantation is recovered in a subsequent heat step, so that the source and drain regions are not damaged. Junction leakage current generated at the junction with the channel is suppressed. Further, since different potentials can be applied to the region near the source and the region near the drain in the well, the substrate bias effect can be effectively used.

Also, in the present invention, Japanese Patent Laid-Open No.
No. 6,455, the MOSFET and its manufacturing method use a bulk substrate instead of an SOI substrate, and the crystal growth when the insulating layer is buried in the semiconductor substrate is always performed only in one direction from the substrate side. Therefore, favorable crystal growth can be performed. Such good crystallinity is an indispensable requirement for a fine element.

As a result, it is possible to realize a high-performance MOS field-effect transistor capable of increasing the driving force while suppressing punch-through and reducing the resistance of the source and the drain.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. (First Embodiment) FIG. 1 is a sectional view showing an element structure of a MOS transistor according to a first embodiment of the present invention.

An element isolation oxide film 3 is formed on a p-type (or n-type) silicon substrate 1 so as to surround an element region, and a p-well region 2 is formed in the element region. p well region 2
Silicon oxide film (gate insulating film) 5
, A gate electrode 6 is formed, and an n-type region (source / drain region) 7 is formed on the surface of the p-well on both sides of the gate electrode 6 with a channel therebetween.

A silicon oxide film is deposited thereon as an interlayer insulating film 8 by, for example, a CVD method, and a contact portion 9 is opened in the insulating film 8. The wiring 10 is formed by depositing, for example, an aluminum film containing 1% of silicon by sputtering and patterning. Although not shown in the figure,
For example, after sintering in a forming gas atmosphere at 450 ° C., a silicon oxide film is then
0 nm is formed to form a passivation film.

The basic configuration up to this point is the same as that of the conventional device, but in this embodiment, in addition, an insulating layer 11 is buried under the channel. This insulating layer 11
Are thinner in the channel length direction than the channel length, and are disposed along the substrate depth direction and the channel width direction. The upper end of the insulating layer 11 is located very close to the substrate surface without contacting the substrate surface, and the lower end penetrates the p-well region 2 and reaches the substrate 1 side.

As described above, according to the present embodiment, the insulating layer 11 is provided immediately below the channel region below the gate electrode so as to separate the channel region. Can be suppressed. Accordingly, it is possible to suppress the punch-through while keeping the impurity concentration of the channel region low while using the bulk substrate, and it is possible to suppress the short channel effect without losing a high driving force.

Further, since the impurity concentration of the channel region can be set low, it is possible to prevent the threshold voltage from becoming extremely deep. Further, since the source and drain regions can be formed to have a large thickness without being lifted above the channel surface, A
The resistance of the source and the drain can be reduced without lowering the operation speed during the C operation.

The bottom of the source and drain regions is S
Compared with the OI element, since silicon is formed in a deep region, damage caused by impurity implantation at the time of forming a source and a drain can be recovered in a subsequent heat process.
It is possible to suppress a leak current at a junction between the source and the drain and the channel. Further, since the p-well region 2 is substantially separated by the insulating layer 11, a substrate bias can be separately applied to the vicinity of the source and the vicinity of the drain.

As described above, in the present embodiment, in addition to the conventional structure, by adding a configuration in which the insulating layer 11 is formed immediately below the channel region, the driving force is increased while suppressing the punch-through, and the source and drain are reduced. It is possible to realize an unprecedented high-performance MOS transistor with reduced resistance, and its usefulness is extremely large.

Next, a method of manufacturing the MOS transistor according to the present embodiment will be described with reference to FIG. First, FIG.
As shown in (a), a part of the p-type silicon substrate 1 is
Etching is performed by an anisotropic etching method such as E method to form a step on the substrate surface. At this time, the height of the step is higher than the depth of a p-well region to be formed later.
Further, the length of the step portion in the front-back direction on the paper surface is M
It is longer than the width of the channel region of the OS transistor. Subsequently, for example, a thickness of 10 n
An m-th silicon oxide film 11 'is formed.

Next, as shown in FIG.
By etching back the silicon oxide film 11 'by a method or the like, the silicon oxide film 11' other than the step portion is removed. Thereby, the insulating layer 11 is formed only at the step portion,
The insulating layer 11 is provided in the substrate depth direction.

Next, as shown in FIG. 2C, a silicon layer 1 'is deposited by, for example, the LPCVD method or the like, and the surface is flattened. Here, after depositing the silicon layer 1 ′, the silicon may be recrystallized by using a method such as a thermal process, and thereafter, flattening may be performed.
Further, the silicon layer may be grown using an epitaxial growth method instead of the LPCVD method.

Next, as shown in FIG. 3D, for example, B ions are implanted at 100 keV and 2.0 × 10 ¹³ cm ^-3 , and then a heat step is performed at 1190 ° C. for 150 minutes, for example. A p-well region 2 is formed. Subsequently, the element isolation oxide film 3 is formed by, for example, the LOCOS method.

Then, as shown in FIG. 3E, for example, B ions 4 are implanted into the p-well region 2 at 15 keV and 1.0 × 10 ¹³ cm ^-2 to obtain a desired threshold voltage. By doing so, the concentration on the channel surface is adjusted. Then, for example, a silicon oxide film (gate insulating film) 5 having a thickness of 4 nm is formed by oxidizing the surface of silicon in a 10% HCl atmosphere at 800 ° C.

Next, as shown in FIG. 3F, a thickness of 200 nm is formed on the silicon oxide film 5 by, for example, the LPCVD method.
Then, a gate electrode 6 is formed by depositing a polycrystalline silicon film having a thickness of nm and selectively etching a part of the polycrystalline silicon film by RIE. Subsequently, using the gate electrode 6 as a mask, for example, As ions are implanted at 50 keV and 5.0 × 10 ¹⁵ cm ⁻² , and a thermal process is performed to form an n-type layer (source / drain region) 7.

Thereafter, in the same manner as in the manufacture of the conventional MOS transistor, an interlayer insulating film, a contact hole, a wiring forming step, and the like are performed.
Is completed.

In this embodiment, an n-channel MOS
Although only the method of manufacturing the transistor is shown, if the conductivity type of the impurity is reversed, the p-channel MOS transistor is configured in exactly the same manner, and the same effect as in the present embodiment can be obtained. In addition, if a method such as a photo-etching method is used to selectively introduce impurities into only a part of the substrate, the complementary type M
The configuration of the OS transistor can be similarly performed, and the same effect as that of the present embodiment can be obtained. Further, in addition to forming the MOS transistor alone, the present invention is also applicable to the case where the MOS transistor is formed as a part of a semiconductor device including another active element such as a bipolar transistor or a passive element such as a resistor or a capacitor. Needless to say, the same effects as in the embodiment can be obtained.

In this embodiment, As is used as an impurity for forming an n-type layer, and B is used as an impurity for forming a p-type layer. Other group V impurities may be used as impurities,
Other Group III impurities may be used as impurities for forming the p-type layer. Furthermore, in the present embodiment, the introduction of the impurity is performed using the method of ion implantation, but the introduction of the impurity may be performed using a method other than ion implantation, such as solid-phase diffusion or gas-phase diffusion, For example, a method of depositing a semiconductor containing impurities may be used.

In this embodiment, only an element having a single drain structure is shown. However, even if an element having a structure other than the single drain structure such as an LDD structure is constructed,
The same effects as in the present embodiment can be obtained. Further, the same applies to an element having a pocket structure or the like.

Although silicidation is not mentioned in the present embodiment, the same effect as in the present embodiment can be obtained even if silicidation is performed. Further, in this embodiment, polycrystalline silicon is used as a gate electrode material, but a gate electrode may be formed using, for example, a metal, a metal silicide, or a laminated structure of these.

In this embodiment, an oxide film formed by thermal oxidation is used as the gate insulating film, but another insulating film such as a nitride film, a nitrided oxide film, or a laminated film may be used. Further, a high dielectric film may be used as a gate insulating film.
Further, even when an element using a ferroelectric film as the gate insulating film is formed, the same effect as in the present embodiment can be obtained.

In this embodiment, the insulating layer below the channel is formed by a method called oxide film formation by thermal oxidation. However, the same effect can be obtained by forming this insulating layer by a method other than thermal oxidation, such as deposition. Is obtained. Of course, the same applies to the case where the insulating layer is made of a material other than silicon oxide, such as silicon nitride.

In this embodiment, the element isolation is L
Although the OCOS method was used, the same effect as in the present embodiment can be obtained even if the element isolation is performed using another method such as a trench element isolation method.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a manufacturing step of the MOS transistor according to the embodiment.

Following the step shown in FIG. 2B of the first embodiment, as shown in FIG. 4A, a silicon layer 1 'is grown by, for example, an epitaxial growth method, and the surface is flattened. . Here, the upper end of the insulating layer 11 is made flush with the surface of the silicon layer 1 '.

Next, as shown in FIG.
A silicon layer 1 ″ is deposited by a VD method or the like, and silicon is recrystallized using a method such as a thermal process. Then, the surface is flattened.

Thereafter, FIG. 3D of the first embodiment will be described.
The description is omitted because it is the same as the subsequent steps. (Third Embodiment) FIG. 5 is a sectional view showing a manufacturing process of a MOS transistor according to a third embodiment of the present invention.

Following the step shown in FIG. 3D of the first embodiment, as shown in FIG. 5A, anisotropic etching such as RIE is performed to form a p-well region of the substrate 1. 2 is partially etched to expose a part of the insulating layer 11.

Next, as shown in FIG. 5B, a silicon layer 1 ″ ″ is deposited by, for example, the LPCVD method. Then, in order to obtain a desired threshold voltage, for example, B ions 4 are applied at 15 keV and 1.0 × 10 ^{13 in} the p-well region 2.
The concentration at the channel surface is adjusted by implantation at cm ⁻² .

Next, as shown in FIG. 5C, for example, polycrystalline silicon 13 containing P is deposited by the LPCVD method, and thereafter, the silicon surface is flattened. Here, instead of the LPCVD method, the P-containing silicon 13 may be grown by an epitaxial growth method. Then, for example, a silicon oxide film (gate insulating film) 5 having a thickness of 4 nm is formed by oxidizing the surface of silicon in a 10% HCl atmosphere at 800 ° C.

Next, as shown in FIG. 5D, a thickness of 200 nm is formed on the silicon oxide film 5 by, for example, LPCVD.
Then, a gate electrode 6 is formed by depositing a polycrystalline silicon film having a thickness of nm and selectively etching a part of the polycrystalline silicon film by RIE.

Thereafter, in the same manner as in the manufacture of a conventional MOS transistor, a MOS transistor is formed through the steps of forming an interlayer insulating film, forming a contact hole, and forming a wiring.

In this embodiment, P-containing silicon is used as the semiconductor region forming the source / drain regions. However, even if silicon containing another group V impurity is used, the same effect as in this embodiment can be obtained. can get. Further, in this embodiment, recrystallization is not performed after silicon deposition, but recrystallization may be performed after silicon deposition. Further, the present embodiment is a method performed following the surface flattening step of the first embodiment. However, following the surface flattening step of the second embodiment, M
It goes without saying that the same effects as those of the present embodiment can be obtained even if the OS transistor is formed.

(Fourth Embodiment) FIGS. 6 and 7 are sectional views showing the steps of manufacturing a MOS transistor according to a fourth embodiment of the present invention.

Following the step shown in FIG. 3D of the first embodiment, as shown in FIG. 6A, anisotropic etching such as RIE is performed, thereby forming the p-well of the substrate 1. A part of the region 2 is etched to expose a part of the insulating layer 11.

Next, as shown in FIG. 6B, silicon 1 ″ is deposited so as to cover the insulating layer 11 by, for example, the LPCVD method or the like. Then, as shown in FIG. Silicon nitride 16 is deposited by a method or the like, and its surface is planarized.

Next, as shown in FIG. 7D, silicon and silicon oxide are etched by RIE or the like using the silicon nitride 16 as a mask. Next, as shown in FIG. 7E, a silicon layer 1 ″ ′ is deposited by an LPCVD method or the like, and its surface is planarized. Subsequently, the silicon layer 1 ″ ′ is etched back by RIE or the like so that the silicon layer 1 ″ ′ slightly remains above the upper end of the insulating layer 11. Then, for example, a silicon oxide film (gate insulating film) 5 having a thickness of 4 nm is formed by oxidizing the surface of silicon in a 10% HCl atmosphere at 800 ° C.

Next, as shown in FIG.
The gate electrode 6 is formed by self-alignment by depositing polycrystalline silicon by a VD method or the like and flattening the surface. Thereafter, the silicon nitride 16 is removed.

Next, as shown in FIG. 7 (g), using the gate electrode 6 as a mask, for example,
Implantation is performed at 5.0 × 10 ¹⁵ cm ⁻² , and a thermal process is performed to form an n-type layer (source / drain region) 7.

Thereafter, in the same manner as in the manufacture of a conventional MOS transistor, a MOS transistor is formed through the steps of forming an interlayer insulating film, forming a contact hole, and forming a wiring.

(Fifth Embodiment) FIGS. 8 and 9 are cross-sectional views showing steps of manufacturing a MOS transistor according to a fifth embodiment of the present invention.

Following the step shown in FIG. 3D of the first embodiment, as shown in FIG. 8A, the silicon substrate 1 is subjected to anisotropic etching such as RIE.
Is etched to expose a part of the insulating layer 11.

Next, as shown in FIG.
A silicon layer 1 ″ is deposited so as to cover the insulating layer 11 by a VD method or the like. Then, as shown in FIG.
Silicon nitride 14 is deposited by an LPCVD method or the like, and its surface is planarized.

Next, as shown in FIG. 8D, silicon and silicon oxide are etched by RIE or the like using the silicon nitride 14 as a mask. Next, as shown in FIG. 9E, after the silicon oxide 15 is deposited and the surface is flattened, the silicon nitride 14 is removed.

Next, as shown in FIG.
Polycrystalline silicon 13 containing P is deposited by a VD method or the like, and the surface is flattened. Here, instead of the LPCVD method, the P-containing silicon 13 may be grown by an epitaxial growth method. Then, by RIE method etc.
The silicon is etched back so as to be almost the same height as the upper end of the insulating layer 11.

Next, as shown in FIG. 9G, silicon nitride 16 is deposited by LPCVD or the like, and the surface is flattened. Subsequently, after removing the silicon oxide 15, a silicon layer 17 is deposited by, for example, the LPCVD method or the like, and the surface is flattened. Then, the insulating layer 1 is formed by RIE or the like.
Etch-back is performed so that the silicon layer 17 remains slightly above the upper end of 1.

Next, as shown in FIG. 9H, a silicon oxide film (gate insulating film) 5 having a thickness of 4 nm is formed by oxidizing the surface of the silicon in a 10% HCl atmosphere at 800 ° C., for example. Thereafter, the gate electrode 6 is formed in a self-aligned manner by depositing polycrystalline silicon by LPCVD or the like and flattening the surface. Thereafter, the silicon nitride 16 is removed.

Thereafter, in the same manner as in the manufacture of a conventional MOS transistor, a MOS transistor is formed through the steps of forming an interlayer insulating film, forming a contact hole, and forming a wiring.

(Sixth Embodiment) FIG. 10 and FIG.
FIG. 15 is a cross-sectional view illustrating a manufacturing step of a MOS transistor according to a sixth embodiment of the present invention. This embodiment is different from the first embodiment in that the number of insulating layers is two.

First, as shown in FIG. 10A, a part of the p-type silicon substrate 1 is etched by an anisotropic etching method such as RIE to form a projection 1a on the substrate surface. At this time, the height of the projection 1a is higher than the depth of a p-well region to be formed later. Further, the length of the protrusion 1a in the front-back direction of the drawing is longer than the width of the channel region of the MOS transistor to be formed. Subsequently, a silicon oxide film 11 'having a thickness of 10 nm is formed by, for example, a method such as thermal oxidation.

Next, as shown in FIG.
By etching back the silicon oxide film 11 'by the E method or the like, the silicon oxide film 11' other than the side wall of the protrusion is removed. Thereby, the insulating layers 11 are respectively formed on both sides of the protrusion, and the two insulating layers 11 are arranged in the substrate depth direction.

Next, as shown in FIG.
A silicon layer 1 'is deposited by a CVD method or the like, and the surface is flattened. Next, as shown in FIG. 11D, for example, B ions are implanted at 100 keV and 2.0 × 10 ¹³ cm ⁻² , and then a heat step is performed at 1190 ° C. and 150 minutes, for example, to form a p-well region. Form 2 Subsequently, the element isolation oxide film 3 is formed by, for example, the LOCOS method.

Then, as shown in FIG. 11E, in order to obtain a desired threshold voltage in the p-well region 2, for example, B ions 4 are applied at 15 keV and 1.0 × 10 ¹³ cm ⁻² . The injection adjusts the concentration on the channel surface.
Then, for example, a silicon oxide film (gate insulating film) 5 having a thickness of 4 nm is formed by oxidizing the surface of silicon in a 10% HCl atmosphere at 800 ° C.

Next, as shown in FIG. 11F, a silicon oxide film 5 having a thickness of 20
A 0 nm polycrystalline silicon film is deposited, and a part of the polycrystalline silicon film is selectively etched by RIE to form a gate electrode 6. Subsequently, using the gate electrode 6 as a mask,
For example, As ions are supplied at 50 keV and 5.0 × 10 ₁₅ cm ^−2.
, And through a thermal process, the n-type layer (source
A drain region 7 is formed.

Thereafter, as in the conventional manufacturing of the MOS transistor, the MOS transistor is completed through the steps of forming an interlayer insulating film, forming a contact hole, and forming a wiring.

As described above, also in the present embodiment, since the two insulating layers 11 provided immediately below the channel region effectively suppress punch-through, the same effect as in the first embodiment can be obtained. . Further, various modifications are possible as described in the first embodiment. Further, in this embodiment, the deposited silicon is not recrystallized, but the deposited silicon may be recrystallized in the same manner as in the second embodiment.

In this embodiment, FIG.
In the process shown in (2), silicon outside the region sandwiched by the insulating layers is etched later, but the same effect as that of the present embodiment can be obtained even if the region sandwiched by the insulating layers is etched later and the same process is performed thereafter. can get. Further, in the present embodiment, the insulating layer is formed at two places below the channel region. However, even if the insulating layer is formed at three or more places by changing the region where silicon is etched, the same as in the present embodiment. The effect is obtained.

(Seventh Embodiment) FIG. 12 is a sectional view showing a process for manufacturing a MOS transistor according to a seventh embodiment of the present invention.

Following the step shown in FIG. 11D of the sixth embodiment, as shown in FIG.
A part of the p-well region 2 of the substrate 1 is etched by performing anisotropic etching such as a method, and then a silicon layer 1 ″ is deposited. Then, a desired threshold voltage is formed in the p-well region 2. For example, to obtain B ion 4 15k
The concentration on the surface of the channel is adjusted by injecting eV at 1.0 × 10 ¹³ cm ⁻² .

Next, as shown in FIG. 12B, polycrystalline silicon 13 containing P is deposited by the LPCVD method, and thereafter, the silicon surface is flattened. Where L
Instead of the PCVD method, the P-containing silicon 13 may be grown by an epitaxial growth method. Then, for example, a silicon oxide film (gate insulating film) 5 having a thickness of 4 nm is formed by oxidizing the surface of silicon in a 10% HCl atmosphere at 800 ° C.

Then, as shown in FIG. 12C, a silicon oxide film 5 having a thickness of 20
A 0 nm polycrystalline silicon film is deposited, and a part of the polycrystalline silicon film is selectively etched by RIE to form a gate electrode 6.

Thereafter, in the same manner as in the manufacture of a conventional MOS transistor, a MOS transistor is formed through the steps of forming an interlayer insulating film, forming a contact hole, and forming a wiring.

In this embodiment, P-containing silicon is used for forming the source / drain.
The same effect as in the present embodiment can be obtained even when silicon containing group-group impurities is used. In this embodiment, recrystallization is not performed after silicon deposition. However, even if recrystallization is performed after silicon deposition, the same effect as in the present embodiment can be obtained. Further, the present embodiment is a method performed following the surface flattening step of the sixth embodiment.
Even if a field-effect transistor is formed through a process similar to that of the present embodiment following the surface flattening process after the recrystallization of silicon as in the second embodiment, the same effect as that of the present embodiment can be obtained. Needless to say, this is obtained.

(Eighth Embodiment) FIG. 13 and FIG.
FIG. 15 is a cross-sectional view showing a manufacturing step of the MOS transistor according to the eighth embodiment of the present invention.

Following the step shown in FIG. 11D of the sixth embodiment, as shown in FIG.
By performing anisotropic etching such as a method, a part of the p-well region 2 of the silicon substrate 1 is etched to form the insulating layer 1.
Expose 1

Then, as shown in FIGS. 13 (b), (c) and (d) and FIGS. 14 (e), (f) and (g), the MOS transistors are obtained through the same steps as in FIGS. A transistor is created.

(Ninth Embodiment) FIG. 15 and FIG.
FIG. 21 is a cross-sectional view illustrating a manufacturing step of a MOS transistor according to a ninth embodiment of the present invention.

Following the step shown in FIG. 11D of the sixth embodiment, as shown in FIG.
By performing anisotropic etching such as a method, a part of the p-well region 2 of the silicon substrate 1 is etched to form the insulating layer 1.
Expose 1

As shown in FIGS. 15 (b), (c), (d) and FIGS. 16 (e), (f), (g), (h), FIG.
Through the same steps as those shown in FIG. 9 and FIG. 9, a MOS transistor is formed.

(Tenth Embodiment) FIG. 17 is a sectional view showing an element structure of a MOS transistor according to a tenth embodiment of the present invention.

Although the basic structure is the same as that of FIG. 1, in this embodiment, in addition to this, the source
A p-type layer 27 separated from the drain region 7 by the element isolation oxide film 3 is formed, and an electrode 30 connected to the p-type layer 27 is provided. That is, the p-well region 2 is formed larger than the original transistor formation region, and the surface of the transistor portion and the outside thereof are separated by the element isolation oxide film 3. On each of the source side and the drain side, an electrode 30 for applying a substrate potential is connected to the p-type layer 27 outside the transistor section.

With such a structure, not only the same effects as in the first embodiment can be obtained, but also the potential can be independently applied to the source-side and drain-side wells. The effect can be used effectively. For example, it is possible to apply a bias only near the drain.

Next, a method for manufacturing the MOS transistor of the present embodiment will be described with reference to FIG. First, FIG.
As shown in FIG. 2A, FIGS.
Similarly to the step (c), an insulating layer 11 is formed near the surface of the p-type silicon substrate 1 in the depth direction of the substrate.

Next, as shown in FIG. 18 (b), for example, B ions are implanted at 100 keV and 2.0 × 10 ¹³ cm ^-2 , and thereafter, a p-type heat treatment is performed at, for example, 1190 ° C. for 150 minutes. A well region 2 is formed. Subsequently, the element isolation oxide film 3 is formed by, for example, the LOCOS method.
Here, the isolation oxide film 3 is formed on the p-well region 2 in a region excluding the transistor formation region and the p-type layer formation region outside the transistor portion.

Next, as shown in FIG. 18C, for example, B ions 4 are implanted into the p-well region 2 at 15 keV and 1.0 × 10 ¹³ cm ^-2 to obtain a desired threshold voltage. By doing so, the concentration on the channel surface is adjusted. Then, for example, a silicon oxide film (gate insulating film) 5 having a thickness of 4 nm is formed by oxidizing the surface of silicon in a 10% HCl atmosphere at 800 ° C.

Next, as shown in FIG. 18D, a 200 nm-thick film was formed on the silicon oxide film 5 by LPCVD.
Is deposited, and the polycrystalline silicon film is selectively etched by RIE to form a gate electrode 6. Thereafter, for example, As ions are supplied at 50 keV,
Implantation is performed at 0 × 10 ¹⁵ cm ⁻² , and then, for example, BF ₂ ions are implanted at 30 keV and 5.0 × 10 ¹⁵ cm ⁻² , and a heat process is performed. Then, a contact portion 27 of the substrate as a p-type layer is formed.

Thereafter, a 500 nm-thick silicon oxide film is deposited as the interlayer insulating film 8 by the CVD method, and the contact portion is opened by the RIE method. Then, an aluminum film containing 1% of silicon is deposited by a sputtering method, and the wiring 10 is formed by patterning, whereby the structure shown in FIG. 17 is obtained.

In the present embodiment, various modifications as described in the first embodiment are possible. Also,
Although the deposited silicon is not recrystallized in the present embodiment, the same effect as in the present embodiment can be obtained even if the deposited silicon is recrystallized in the same manner as in the second embodiment.

In this embodiment, FIG.
In the process shown in (1), only one region to be filled with the insulating layer later is formed, but the same effect as in the present embodiment can be obtained even if two or more regions are formed. Further, in this embodiment, silicon oxide is used as the insulating layer below the channel, but the element may be formed using another insulating material. Further, in the present embodiment, the electrodes for applying the substrate potential are provided at two places. However, the positions at which the substrate electrodes are taken are not limited to two places, and the electrodes may be taken from only one place or three or more places. Of course, the same effect as in the present embodiment can be obtained.

(Eleventh Embodiment) FIG. 19 is a sectional view showing a manufacturing process of a MOS transistor according to an eleventh embodiment of the present invention.

First, as shown in FIG. 19A, a part of the p-type silicon substrate 1 is selectively etched by anisotropic etching such as RIE to form a groove having a narrow opening and extending in the substrate depth direction. 1b is formed. At this time, the length of the groove 1b in the front-back direction of the drawing is longer than the width of the channel region of the MOS transistor to be formed.

Next, as shown in FIG.
After the silicon oxide 11 'is deposited by a method such as the CVD method to fill the trench, the surface is flattened. Thereby, a structure in which the insulating layer 11 is embedded only in the groove 1b is obtained.

Next, as shown in FIG. 19C, for example, B ions are implanted at 100 keV and 2.0 × 10 ¹³ cm ⁻² , and then a heat step is performed at 1190 ° C. for 150 minutes, for example. A p-well region 2 is formed. continue,
For example, the element isolation oxide film 3 is formed by the LOCOS method.

Thereafter, FIG. 5A of the third embodiment will be described.
(D) etching of the substrate, deposition of silicon by LPCVD, concentration adjustment of the channel surface by implantation of B ions, deposition of P-containing silicon by LPCVD, Flattening,
Formation of silicon oxide film by oxidation of silicon surface, L
A MOS transistor is formed by performing processes such as deposition of a polycrystalline silicon film by the PCVD method and formation of a gate electrode by patterning the polycrystalline silicon film by the RIE method.

It is to be noted that, following the step shown in FIG. 19C in this embodiment, a transistor can be manufactured in the same manner as the steps shown in FIGS. 6 and 7 of the fourth embodiment. Further, following the step shown in FIG. 19C of this embodiment, a transistor can be manufactured in the same manner as the steps shown in FIGS. 8 and 9 of the fifth embodiment. Further, modifications similar to those described in the first embodiment are possible.

(Twelfth Embodiment) FIGS. 20 and 21
FIG. 29 is a cross-sectional view showing a manufacturing step of the MOS transistor according to the twelfth embodiment of the present invention.

First, as shown in FIG. 20A, for example, B ions are applied to the p-type silicon substrate 1 at 100 keV and 2.0 keV.
× 10 ¹³ cm ^-2 and then, for example, 1190 ° C,
The p-well region 2 is formed through a heating step for 150 minutes. Subsequently, the element isolation oxide film 3 is formed by, for example, the LOCOS method.

Next, as shown in FIG. 20B, a silicon nitride 16 is deposited by, for example, the LPCVD method or the like, and R
By performing anisotropic etching such as the IE method, a part of the opening is removed to form an opening. Then, silicon oxide is deposited by a method such as the LPCVD method, and is subjected to anisotropic etching such as the RIE method so that the silicon oxide sidewall 20 is formed.
To form

Next, as shown in FIG. 20C, the silicon nitride 16 and the silicon oxide
By performing anisotropic etching such as the IE method, the substrate 1
A groove is formed in the groove. Then, silicon oxide 11 'is deposited by a method such as the LPCVD method. And RIE
By performing anisotropic etching such as a method, a structure in which the insulating layer 11 is embedded only in the groove can be obtained.

Next, as shown in FIG. 21D, silicon 17 is deposited by a method such as the LPCVD method.
After the surface is flattened, the silicon layer 17 is etched back by a method such as the RIE method. And, for example, 800
A silicon oxide film (gate insulating film) 5 having a thickness of 4 nm is formed by oxidizing the surface of silicon in a 10% HCl atmosphere at a temperature of 10 ° C.

Next, as shown in FIG. 21E, the gate electrode 6 is formed in a self-aligned manner by depositing polycrystalline silicon by, for example, the LPCVD method and flattening the surface. After that, the silicon nitride 16 is removed.

Next, as shown in FIG. 21F, for example, As ions are applied at 50 keV and 50 keV using the gate electrode 6 as a mask.
Implantation is performed at 5.0 × 10 ¹⁵ cm ⁻² , and a thermal process is performed to form an n-type layer (source / drain region) 7.

Thereafter, in the same manner as in the manufacture of a conventional MOS transistor, a MOS transistor is formed through the steps of forming an interlayer insulating film, forming a contact hole, and forming a wiring.

In the present embodiment, various modifications as described in the first embodiment are possible. Also,
In the present embodiment, recrystallization is not performed after silicon deposition. However, even if recrystallization is performed after silicon deposition, the same effect as in the present embodiment can be obtained. Further, in the present embodiment, silicon oxide is used as an insulator under the channel, but it goes without saying that the same effect as in the present embodiment can be obtained even if an element is formed using another insulator.

[0119]

As described in detail above, according to the present invention, an insulating layer is provided immediately below a channel region, and punch-through is suppressed by this insulating layer. Even if the impurity concentration of the channel region is reduced, the short channel effect can be sufficiently suppressed. As a result, a high-performance fine element having a high driving force can be realized.

Further, the potential of the well can be controlled to different values at a plurality of locations, and the substrate bias effect can be effectively used. As a result, a high-performance MOS field-effect transistor can be realized, and its usefulness is enormous.

[Brief description of the drawings]

FIG. 1 is an exemplary sectional view showing the element structure of a MOS transistor according to a first embodiment;

FIG. 2 is a sectional view showing the manufacturing process of the MOS transistor according to the first embodiment.

FIG. 3 is a sectional view showing the manufacturing process of the MOS transistor according to the first embodiment.

FIG. 4 is a sectional view showing a step of manufacturing the MOS transistor according to the second embodiment.

FIG. 5 is a sectional view showing a manufacturing process of the MOS transistor according to the third embodiment.

FIG. 6 is a sectional view showing a manufacturing process of a MOS transistor according to a fourth embodiment.

FIG. 7 is a sectional view showing a manufacturing process of the MOS transistor according to the fourth embodiment.

FIG. 8 is a sectional view showing a manufacturing process of the MOS transistor according to the fifth embodiment.

FIG. 9 is a sectional view showing a manufacturing step of the MOS transistor according to the fifth embodiment;

FIG. 10 is a sectional view showing a manufacturing step of the MOS transistor according to the sixth embodiment;

FIG. 11 is a sectional view showing a manufacturing step of the MOS transistor according to the sixth embodiment.

FIG. 12 is a sectional view showing a manufacturing step of the MOS transistor according to the seventh embodiment;

FIG. 13 is a sectional view showing a manufacturing step of the MOS transistor according to the eighth embodiment;

FIG. 14 is a sectional view showing a manufacturing step of the MOS transistor according to the eighth embodiment;

FIG. 15 is a sectional view showing the manufacturing process of the MOS transistor according to the ninth embodiment;

FIG. 16 is a sectional view showing the manufacturing process of the MOS transistor according to the ninth embodiment;

FIG. 17 is a sectional view showing an element structure of a MOS transistor according to a tenth embodiment.

FIG. 18 is a sectional view showing the manufacturing process of the MOS transistor according to the tenth embodiment.

FIG. 19 is a sectional view showing the manufacturing process of the MOS transistor according to the eleventh embodiment.

FIG. 20 is a sectional view showing the manufacturing process of the MOS transistor according to the twelfth embodiment;

FIG. 21 is a sectional view showing a manufacturing step of the MOS transistor according to the twelfth embodiment;

FIG. 22 is a sectional view showing a manufacturing process of a conventional MOS transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... p-well region 3 ... element isolation oxide film 4 ... B ion 5 ... silicon oxide film (gate insulating film) 6 ... gate electrode 7 ... n-type layer (source / drain region) 10 ... wiring electrode DESCRIPTION OF SYMBOLS 11 ... Insulating layer 13 ... Polycrystalline silicon 14, 16 ... Silicon nitride 15 ... Silicon oxide film 17 ... Silicon layer 20 ... Silicon oxide side wall 27 ... P-type layer (substrate contact part) 30 ... Substrate electrode

Claims (9)

[Claims] 1. A semiconductor device comprising: a gate electrode formed on a surface of a semiconductor substrate via a gate insulating film; and a source / drain region formed on a surface of the substrate with a channel region below the gate electrode interposed therebetween. In the substrate under the gate electrode, an insulating layer having a thickness in the channel length direction smaller than the channel length is provided without contacting the substrate surface so as to separate the channel region on the source side and the drain side. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein said insulating layer is provided in a plane parallel to a substrate depth direction and a channel width direction. 3. The semiconductor device according to claim 1, wherein the source / drain region is formed on a surface of a well formed in the substrate, and a lower end of the insulating layer protrudes from a bottom of the well to reach a base substrate. The semiconductor device according to claim 1. 4. An electrode connected to the source side of the well and an electrode connected to the drain side of the well are provided separately from the source / drain regions. Semiconductor device. 5. The semiconductor device according to claim 1, wherein a part of the substrate surface sandwiching the gate electrode is etched to a position deeper than a substrate surface below the gate electrode, and the source / drain region is formed in the etched portion. The semiconductor device according to claim 1. 6. A method of manufacturing a semiconductor device having a gate electrode on a surface of a semiconductor substrate with a gate insulating film interposed therebetween, and having a source / drain region on a substrate surface with a channel region below the gate electrode interposed therebetween. Forming an insulating layer, which is thinner than the length of the channel region of the MOS field effect transistor to be formed, in the depth direction of the substrate near the surface of the substrate without contacting the substrate surface; Forming a gate electrode and a source / drain region so that the region is separated into a source side and a drain side. 7. A step of forming an insulating layer near the surface of the substrate, forming a step on the surface of the substrate by selectively etching a part of the substrate, and insulating the surface of the substrate including the step. Forming a layer, then etching back the insulating layer on the side of the step, depositing or epitaxially growing a semiconductor layer so as to fill the step, and then planarizing the surface of the semiconductor layer. The method of manufacturing a semiconductor device according to claim 6. 8. A step of forming an insulating layer near a surface portion of the substrate, wherein a thickness of the substrate in a channel length direction is smaller than the channel length, and a groove extending in a depth direction of the substrate is formed along the channel width direction. After that, an insulating layer is buried in the groove, and then the MO layer is formed on the substrate surface and the insulating layer.
7. The method according to claim 6, wherein a semiconductor layer serving as a channel region of the S-type field effect transistor is formed. 9. After forming a first mask having a stripe opening on the substrate to form the groove, a second mask is formed in a self-aligned manner on the opening side of the mask. 9. The method according to claim 8, wherein the substrate is selectively etched using the first and second masks.