JPH1175161A - Synchronization method and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To synchronize a video signal with an audio sampling period with high accuracy. SOLUTION: An analog phase comparator 44 compares a phase of a signal of a reference frequency with a phase of a signal from an unequal interval frequency divider 43 and a phase error signal is fed to a voltage controlled oscillator VCO 46 via an LPF 45. The VCO 46 generates a prescribed frequency (e.g. 24.576 MHz) corresponding to a signal from the LPF 45 and the signal is fed to a high accuracy frame counter 48, where the frequency is divided into 1/820020 at one cycle per 5 frames and into 1/820019 at four cycles per 5 frames, and the frequency-divided signals are fed to a digital phase comparator 41. The digital phase comparator 41 detects phase error data with a reference frame signal and the data are fed to a digital loop filter 42.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization method and apparatus, for example, to a synchronization method and apparatus suitable for synchronizing a video signal and an audio signal.

[0002]

2. Description of the Related Art Existing sampling frequencies (48 KHz, 44.1 KHz, 32 KH) in audio equipment are used.
z) is NTSC (National Television System Commit)
tee) The video signal has a frequency relationship in which complete synchronization in one frame is not possible. In a so-called video device that records and reproduces both an audio signal and a video signal,
Asynchronous audio signals or video signals often cause inconvenience at the time of editing. Therefore, a method of obtaining synchronization in a cycle of one frame or more is often adopted.

FIG. 5 is a schematic diagram of NTSC (National Television S).
ystem Committee) Video signal and 48 kHz (KHz)
Alternatively, a configuration example of a conventional PLL circuit for synchronizing a 32 KHz audio signal is shown.

A frame PLL (phase-locked loop) 1
Is composed of a phase comparator and a frequency divider (1 / Na) 2, and includes an LPF 3 and a VCO (Voltage Controlled Oscill
ator) 4 together with a PLL circuit. VCO4
(13.5 MHz) is divided by the frequency divider 2
, And also to the frequency divider (1 / Nb) 5. The signal supplied to the frequency divider 5 is divided to 24K
Hz signal is output. The output from the frequency divider 5 is PL
L6. The PLL 6 has a frequency divider (1/1).
Nc) 9 is also supplied.

The PLL 6 converts the phase error signal corresponding to the phase error between the signal from the frequency divider 9 and the signal from the frequency divider 5 into LP
It supplies to VCO8 via F7. VCO8 is LPF
7 outputs a signal having a frequency corresponding to the phase error signal supplied through the switch 7. This signal is supplied to the frequency divider 9 and also to the frequency divider (1 / Nd) 10, and the frequency-divided signal is output as a sampling clock.

As described above, a PLL is configured at an arbitrary frequency (13.5 MHz in this example) for video synchronization. Then, the output signal of the first-stage PLL is set to 48K.
Frequency or a frequency that is a multiple of 32 kHz,
A second-stage PLL is configured. In this example, synchronization is performed every two frames.

For example, at 48 KHz, the number of audio samples per frame is 2 frames per frame.
Assuming 9.97 Hz, (1.001 / 30) × 48
(KHz) = 1601.6, resulting in a fraction of 0.6. This is ((1600 × 1 + 1602 × 4) / 5)
= 1601.6, and can be reproduced in 5 frame cycles.

At 32 kHz, (1.001 / 3
0) × 32 KHz = 1067.73, resulting in a fraction of 0.73. This is ((1066 × 2 + 1068 ×
13) / 15) = 1067.73, which can be reproduced in 15 frame cycles.

Also, PAL (phase alternation by lin)
In the case of the television picture of the e) system, if the sampling frequency of the audio is 48 KHz, about 1920 audio data is recorded in one frame. The quantity of the recorded audio data becomes a variable of the variable phase in the PLL.

FIG. 6 shows another example of the PLL circuit. Sampling period operation feedback frame counter 21
Operates based on the input sampling number for each frame, and counts up the signal supplied from the frequency divider 27. This count value is supplied to the digital phase comparator 23 as frame phase information, compared with the phase of the reference frame signal, and a signal corresponding to the phase difference is supplied to the analog phase comparator 24. In the analog phase comparator 24, the phase of the reference frequency signal is compared with the phase of the signal supplied from the digital phase comparator 23, a signal corresponding to the phase difference is supplied to the analog LPF 25, and after the high frequency component is removed, It is supplied to the VCO 26. The VCO 26 supplies a signal having a frequency corresponding to the signal supplied via the analog LPF 25 to the frequency divider 27. In the frequency divider 27, the signal supplied from the VCO 26 is frequency-divided and supplied to the sampling period operation feedback frame counter 21.

[0011]

As described above, the distribution of feedback frames is performed in units of integers and synchronization is performed. When an audio signal of 48 KHz is synchronized with a reference frame, 0.0x (x is When synchronizing an audio signal of 32 KHz (an integer from 0 to 9) percent (%), 0. x% accuracy errors dominant, 5,7
Alternatively, an error offset by two samplings occurs every eight frames, which affects the stability of the PLL.

Further, as shown in FIG. 6, in the case of a configuration in which digital phase information is obtained, the recorded sampling unit has an accuracy of ± about 0.05% with respect to the frame. , This sampling unit is the limit. For this reason, as shown in FIG. 7, when the entire variable (feedback) frame of the PLL is increased in accuracy in order to increase the accuracy, the multiplier 31 for increasing the accuracy for the PLL and the frame in units of increased accuracy are used. There is a problem that the counter 32 is required, which leads to an increase in circuit scale.

The present invention has been made in view of such circumstances, and aims to synchronize a video signal and an audio signal with high accuracy by using a simple circuit.

[0014]

According to a first aspect of the present invention, there is provided a synchronization method for generating a signal having a frequency which is a predetermined number of times higher than a sampling frequency of an audio signal, and generating an audio signal in a frame period of a video signal based on the signal. A first method of allocating a fraction of a signal to a sampling frequency to a predetermined number of pseudo frames, and allocating a fraction to a predetermined number of frames based on the sampling number of each frame.

According to a second aspect of the present invention, a signal having a frequency which is a predetermined number times the sampling frequency of the audio signal is generated, and a fraction of the sampling frequency of the audio signal in a frame cycle of the video signal is generated based on the signal. A first method of assigning to a predetermined number of pseudo frames;
A second method of dividing fractions into a predetermined number of frames based on the number of samplings for each frame, and switching between a locked mode in which audio sampling and video frames are synchronized and an unlocked mode in which audio sampling and video frames are not synchronized. It is characterized by using.

According to a third aspect of the present invention, there is provided a synchronizing device for generating a signal having a frequency several times the sampling frequency of an audio signal, and sampling the audio signal at a frame period of a video signal based on the signal. Allocating means for allocating a fraction for a frequency to a predetermined number of pseudo frames.

According to a fourth aspect of the present invention, the synchronization method operates at a predetermined sampling period in accordance with the number of samplings per frame, counts up the number of samplings per frame, outputs phase information, and outputs the phase information. The phase information within the lock range of the phase information is converted into phase information having a precision several times the sampling period, and the phase information outside the lock range is limited.

According to a fifth aspect of the present invention, there is provided a synchronizer which operates at a predetermined sampling period in accordance with the number of samplings per frame, counts up the number of samplings per frame, and outputs phase information; Conversion means for converting the phase information within the lock range of the phase information output from the count means into phase information having a precision several times the sampling period, and limit means for limiting the phase information outside the lock range. It is characterized by having.

According to the first aspect of the present invention, a signal having a frequency several times the sampling frequency of the audio signal is generated, and a fraction of the sampling frequency of the audio signal in a frame period of the video signal is generated based on the signal. Is allocated to a predetermined number of pseudo frames.

According to a second aspect of the present invention, a signal having a frequency several times the sampling frequency of the audio signal is generated, and based on the signal, a signal having a frequency corresponding to the sampling frequency of the audio signal in the frame period of the video signal is generated. Audio sampling and video frames are synchronized between a first method for distributing fractions to a predetermined number of pseudo frames and a second method for distributing fractions to a predetermined number of frames based on the sampling number for each frame. Switch between locked mode and unlocked unlocked mode.

According to a third aspect of the present invention, the synchronizing device generates a signal having a frequency which is a predetermined multiple of the sampling frequency of the audio signal, and the distributing device generates a signal based on the signal at a frame period of the video signal. Is divided into a predetermined number of pseudo frames with respect to the sampling frequency of the audio signal.

According to a fourth aspect of the present invention, the synchronization method operates at a predetermined sampling period according to the number of samplings per frame, counts up the number of samplings per frame, outputs phase information, and outputs the phase information. The phase information within the lock range of the obtained phase information is converted into phase information having a precision several times the sampling period, and the phase information outside the lock range is limited.

[0023] In the synchronizer according to the fifth aspect, the counting means includes:
It operates at a predetermined sampling period, counts up the number of samplings per frame, outputs phase information, and converts the phase information within the lock range of the phase information output from the counting unit into the sampling period. Is converted into phase information having a precision several times higher than the above, and the limit means limits the phase information outside the lock range.

[0024]

FIG. 1 is a block diagram showing a configuration example of an embodiment of a PLL (phase-locked loop) circuit to which a synchronizer of the present invention is applied. The basic configuration of the PLL circuit is based on Japanese Patent Application Laid-Open No. Hei 5-90958 filed by the present applicant. The digital phase comparator 41 compares the phase of a reference frame signal with the phase of an output signal from a high-precision frame counter 48 (distribution means) described later, and outputs a phase error signal corresponding to the phase error.
The digital loop filter 42 is configured by a low-pass filter or the like, and removes a high frequency component of the output signal from the digital phase comparator 41.

The unequally-divided frequency divider 43 divides the frequency of the signal from the digital loop filter 42, and
4. The analog phase comparator 44 compares the phase of the reference frequency signal with the phase of the signal from the unequally-spaced frequency divider 43, and converts the phase error signal into an LPF (low pass fi
lter) 45. LPF45
Allows only low frequency components of the signal from the analog phase comparator 44 to pass, and outputs a VCO (Voltage Controlled Oscillat
or) 46 (generation means).

The VCO 46 outputs a signal 512 times the sampling frequency (when the audio sampling frequency is 48 KHz) or 768 times (the audio sampling frequency) according to the voltage level of the phase error signal supplied via the LPF 45. Is 32 KHz) and is supplied to the high-precision frame counter 48 and also to the frequency divider (1 / n) 17. The high-precision frame counter 48 converts the signal from the VCO 46 into 1/8200
The frequency is divided by 20 and supplied to the digital phase comparator 41. In addition, the frequency is divided into 1/820019 by four cycles in five frames and supplied to the digital phase comparator 41.

The signal supplied to the frequency divider 47 is 1/512 (when the sampling frequency is 48 KHz) or 1/768 according to the audio sampling frequency.
(When the sampling frequency is 32 KHz) and output as a sampling clock signal.

Next, the operation will be described. First, the case where the audio sampling frequency is 48 KHz will be described. In the digital phase comparator 41, the input reference frame signal of 29.97 Hz,
The phases of pulse signals supplied from a high-precision frame counter 48 described later are compared. Then, the phase error data corresponding to the phase difference is supplied to the digital loop filter 42, and after the high frequency component is removed, the unequally-divided frequency divider 4
3 is supplied.

In the unequal interval frequency divider 43, the phase error data supplied from the digital loop filter 42 is frequency-divided and supplied to the analog phase comparator 44. In the analog phase comparator 44, the phase of the signal of the reference frequency is compared with the phase of the signal supplied from the unequal frequency divider 43, and the signal corresponding to the phase difference is supplied to the LPF 45.
In the LPF 45, the high frequency component of the signal supplied from the analog phase comparator 44 is removed, and only the low frequency component passes and is supplied to the VCO 46.

In the VCO 46, a frequency (24.576M) corresponding to the voltage of the signal supplied from the LPF 45 is used.
A signal of Hz (= 48 KHz × 512) is generated and supplied to the high-precision frame counter 48 and the frequency divider 47. The signal supplied to the high precision frame counter 48 is
The frequency is divided into 1/820020 in one cycle in 5 frames, and 1/820019 in 4 cycles in 5 frames.
Divided by The frequency-divided signal is supplied to the digital phase comparator 41, where the phase is compared with the reference frame signal as described above, and a signal corresponding to the phase difference is output.
Further, the signal supplied to the frequency divider 47 is frequency-divided by 1/512 and output as a sampling clock.

When the phase of the reference frame (reference frame) matches the phase of the feedback frame (variable frame) for each frame, the frequency division ratio of the feedback frame counter 48 is constant, but the NTSC (National Television System) is used.
In the (m Committee) -TV (Television) system, since it is impossible to synchronize with 48 KHz or 32 KHz audio sampling in one frame unit, the fraction is divided into several frames and absorbed.

For example, assuming that a fraction is allocated to each frame in five frame cycles, the fraction with respect to the sampling frequency in the frame cycle is as described above.
0.6 or 0.73. The output frequency of the PLL is
When the sampling frequency is 48 KHz, when the sampling frequency is 512 times, and when the sampling frequency is 32 KHz, it is 768 times, the fraction can be converged in 5 frame cycles as follows.

That is, when the sampling frequency is 48 KHz, the number of samples is (1601+
308/512) + (1601 + 307/512) × 4
Becomes Therefore, the count number of the high-precision frame counter 48 is 512 times the number of samples, and becomes 80020 + 820019 × 4 per 5 frames.

When the sampling frequency is 32 KHz, the number of samples is (1068+
564/768) + (1068 + 563/768) × 4
Becomes Therefore, the count number of the high-precision frame counter 48 becomes 820788 + 820787 × 4 per five frames by multiplying the sample number by 768.

The offset amount of each pseudo frame composed of the above-mentioned count number is an accuracy (± 80 dB or less) of ± 0.00000x (x is an integer of 0 to 9) percent (%) or less.
Becomes

As described above, 24.576 MHz (= 4
8 KHz × 512 = 32 KHz × 768) or a multiple of this as the oscillation frequency of the PLL, a variable feedback frame with only one VCO cycle displacement in 5 frame cycles can be realized, and the feedback frame has little variation. Thus, a stable PLL clock can be supplied.

FIG. 2 shows a PL to which the synchronizer of the present invention is applied.
FIG. 13 is a block diagram illustrating a configuration example of another embodiment of an L circuit. Sampling period operation feedback frame counter (hereinafter abbreviated as feedback frame counter as appropriate) 21
(Counting means) is a sampling number (A
F size) (1600 or 1602) is equivalent to 48 pulses of the frequency-divided signal supplied from the frequency divider 27, which will be described later.
It counts up with a KHz clock and supplies it to a high resolution phase signal generator (high resolution phase SG) 51 (conversion means, limit means).

The high-resolution phase signal generator 51 counts up only phase information within a predetermined range of the signal from the feedback frame counter 21 with a 512-times clock (24.576 MHz) supplied from the VCO 26, It is designed to increase the accuracy of information.

The digital phase comparator 23 compares the phase of the reference frame signal with the phase of the signal from the high-resolution phase signal generator 51, and outputs a signal corresponding to the phase difference to the analog phase comparator 2.
4. The analog phase comparator 24 compares the phase of the reference frequency signal with the phase of the signal from the digital phase comparator 23, and supplies a signal corresponding to the phase difference to the analog LPF 25. The analog LPF 25 removes high frequency components of the signal from the analog phase comparator 24 and passes only low frequency components.

VCO (Voltage Controlled Oscillator)
26 outputs a signal having a frequency corresponding to the average voltage of the signal from the analog phase comparator 24 supplied via the analog LPF 25. The divider 27 is
The frequency of the signal from the VCO 26 is divided by 1/512,
The data is supplied to the feedback frame counter 21.

Next, the operation will be described. The sampling number (AF size) for each frame is supplied to the feedback frame counter 21. Also, from the frequency divider 27,
The signal divided by 1 / n is supplied to the feedback frame counter 21. The signal from the frequency divider 27 supplied to the feedback frame counter 21 is counted up at a sampling cycle corresponding to the number of samplings for each frame, as shown in FIG. It is supplied to a generator 51. FIGS. 4A and 3B and FIGS.
(C) is an enlarged view of the portion within the lock range.
Thus, in FIG. 3B, for example, 15 gradations, but in FIG. 3C, 7680 (= 15 ×
512) Gray scale.

In the high-resolution phase signal generator 51,
The signal supplied from the feedback frame counter 21 is VC
On the basis of the signal supplied from O26, as shown in FIG. 3C, the signal counted up at a period 512 times the sampling period and having a higher resolution within the lock range is supplied to the digital phase comparator 23. Is done. In the digital phase comparator 23, the phase of the reference frame and the phase of the signal from the high-resolution phase signal generator 51 are compared.
Then, a phase error signal as a comparison result is supplied to the analog phase comparator 24. In the analog phase comparator 24, the signal of the reference frequency and the digital phase comparator 23
Are compared, and the resulting phase error signal is supplied to the analog LPF 25.

In the analog LPF 25, the high frequency component of the signal from the analog phase comparator 24 is removed.
Only low frequency components are passed. In the VCO 26, the analog phase comparator 2
4 generates a signal having a frequency corresponding to the phase error signal supplied from the frequency divider 27 and the high-resolution phase signal generator 5.
1 is supplied. 24.576 supplied to the frequency divider 27
The MHz signal is frequency-divided and converted into a 48 KHz signal, which is then supplied to the feedback frame counter 21.

FIG. 3 shows an operation phase when the PLL is in the locked state. The frame counter for audio signal processing operates with the number of samplings per frame at the time of recording at a frequency corresponding to the sampling period. PL
L operates to lock the phase of this frame and the phase of the reference frame as a reference. The value of the feedback frame counter 21 can be used as it is as phase information. FIG. 6 shows an example of the configuration of the synchronizer when the value of the feedback frame counter 21 is used as it is as the phase information, as described above.

However, when the digital phase comparator 23 extracts the phase information, the accuracy of 0.05% (approximately -65 decibels (dB)) with respect to the frame is limited in sampling frequency units.
-Accuracy is low as a clock used for a DA converter or the like.

In order to improve this accuracy, phase information at a cycle higher than the cycle corresponding to the sampling frequency is required. This improvement in precision can be realized by counting up (512 samples per frame × 512) with a clock 512 times the sampling frequency, if 512 times precision is required.

FIG. 7 shows an example of the configuration of a synchronizer configured to count up with a clock 512 times the sampling frequency. In the case of the configuration example shown in FIG. 7, a 512-times multiplier 31 and a high-bit (16 to 20) feedback frame counter 32 are required in the configuration example shown in FIG.

The resolution of the PLL can be improved with linear phase information only near the lock point (a) shown in FIG. 3C, in contrast to the entire linear phase information shown in FIG. 3B. it can.

In the PLL operation, the falling phase of the feedback frame (point a in FIG. 3B) is the most important phase information. In order to increase the resolution only in this vicinity, a phase preceding by the required lock range (point b in FIG. 3B) and a phase delayed by the lock range (point in FIG. 3B) c) and the phase of the midpoint of the feedback frame (FIG. 3 (B)
Is supplied from the feedback frame counter 21 which operates at the sampling period, and only points b to c are converted into high-resolution phase information, and points c to d and points d to b
The intervening signal is enabled by providing a limited value.

The conversion into high-resolution phase information is performed, for example, by
Set the lock range of ± 15 sampling and set the midpoint value to 0.
By operating the phase information counter with a 512-times clock, -15 × 512 to 0, 0 to 1
It is possible to supply 5 × 512 phase information.

In the example shown in FIG. 2, it is not necessary to increase the number of samplings per frame to 512 times, and it is only necessary to add 14 bits (15 × 2 × 512 (= 1536)
0) phase signal generator 51)
It is possible to configure only. The midpoint phase of the feedback frame is P
Used to keep the LL error Duty at about 50 percent.

As described above, the embodiment shown in FIG. 2 does not require a feedback counter for a required high resolution frame period. Further, since a high-resolution feedback counter is not required, an arithmetic unit for increasing the resolution of sampling data is not required.

When a high-resolution feedback frame counter is used for audio / video synchronous recording / reproduction, etc.,
A high-resolution frame counter can be used as a high-resolution phase information generator without requiring an arithmetic unit for increasing the resolution of sampling data.

In the case of this example, the "STOP" signal at point c and the "RESET" signal at point d in FIG.
Since the signal can be generated based on point b,
Only the phase information of the point b in FIG. 3B described above may be supplied to the high-resolution signal generator 51.

Further, the high-resolution phase signal generator 51 of the embodiment shown in FIG.
L. In this example, since the number of sampling data between frames is known, an arithmetic unit for the sampling data is unnecessary.

For example, in the case of the locked mode, a PLL circuit having a configuration as shown in FIG.
In the unlocked mode, FIG.
Can be used. Thus, the video signal and the audio signal can be synchronized by a method suitable for each mode.

In the above embodiment, the case where the sampling frequency is 48 KHz and 32 KHz has been described, but the sampling frequency is 44.1 KHz.
Or in the case of other frequencies, the audio signal can be synchronized with the TV video signal basically in the same manner as in the case described above.

Further, in the above-described embodiment, the pseudo frame is configured in units of 5 frames, but it is also possible to configure the pseudo frame in units of another number of frames.

Further, in the above-described embodiment, the resolution is increased in the lock range of ± 15 samplings, but may be performed in the lock range of other sampling numbers.

[0060]

According to the first aspect of the present invention, a signal having a frequency several times the sampling frequency is generated,
Based on the signal, the fraction with respect to the sampling frequency of the audio signal in the frame period of the video signal is allocated to a predetermined number of pseudo frames. Audio signals can be synchronized.

According to the second aspect of the present invention, a signal having a frequency several times the sampling frequency is generated, and based on the signal, the fraction of the audio signal in the frame period of the video signal with respect to the sampling frequency is determined. The first method of allocating a predetermined number of pseudo frames and the second method of allocating a fraction to a predetermined number of frames based on the number of samplings for each frame are described by a locked method in which audio sampling and video frames are synchronized. Since the mode is switched between the unlocked mode and the unlocked mode, the video signal and the audio signal can be synchronized by a method suitable for each mode.

According to the third aspect of the present invention, the generation means generates a signal having a frequency which is a predetermined number times the sampling frequency, and the distribution means generates a signal based on the signal in the frame period of the video signal. Since the fraction with respect to the sampling frequency of the audio signal is allocated to a predetermined number of pseudo frames, the video signal and the audio signal can be synchronized with high accuracy using a PLL circuit having a simple configuration.

A synchronization method according to claim 4 and a synchronization method according to claim 5
According to the synchronization device described in the above, according to the number of samplings per frame, operates at a predetermined sampling period, counts up the number of samplings per frame, outputs phase information, out of the output phase information The phase information within the lock range is converted into phase information with a precision several times the sampling period, and the phase information outside the lock range is limited, so that highly accurate phase information can be obtained with a simple configuration. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an embodiment of a PLL circuit to which a synchronization device of the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of another embodiment of a PLL circuit to which the synchronization device of the present invention is applied.

FIG. 3 is a diagram illustrating an operation phase when the PLL circuit is in a locked state.

FIG. 4 is an enlarged view of positions a and P in FIG. 3;

FIG. 5 is a diagram illustrating a configuration example of a conventional PLL circuit.

FIG. 6 is a diagram illustrating another configuration example of the PLL circuit.

FIG. 7 is a diagram illustrating yet another configuration example of the PLL circuit.

[Explanation of symbols]

1 frame PLL, 2 frequency divider (1 / Na), 3
LPF, 4 VCO, 5 divider (1 / Nb),
6 PLL, 7 LPF, 8 VCO 9 divider (1 / Nc), 10 divider (1 / Nd), 21
Feedback frame counter, 23 digital phase comparator,
24 analog phase comparators, 25 analog LPFs,
26 VCO, 27 1 / n frequency divider, 31 multiplier, 32 high-resolution feedback frame counter, 41 digital phase comparator, 42 digital loop filter,
43 unequal interval divider, 44 analog phase comparator,
45 LPF, 46 VCO, 47 1 / n frequency divider, 48 high-precision frame counter

Claims (5)

[Claims] 1. A synchronization method for synchronizing a video signal and an audio signal, comprising: generating a signal having a frequency which is a predetermined number of times higher than a sampling frequency of the audio signal; Wherein the fraction of the audio signal with respect to the sampling frequency is divided into a predetermined number of pseudo frames. 2. A synchronizing method for synchronizing a video signal and an audio signal, comprising: generating a signal having a frequency which is a predetermined number of times higher than a sampling frequency of the audio signal, and generating a frame cycle of the video signal based on the signal. A first method of distributing a fraction of the audio signal at a sampling frequency to a predetermined number of pseudo frames, and a second method of distributing the fraction to a predetermined number of frames based on the sampling number of each frame. A synchronization method characterized by switching between a locked mode in which sampling and a video frame are synchronized and an unlocked mode in which synchronization is not performed. 3. A synchronizing device for synchronizing a video signal and an audio signal, comprising: generating means for generating a signal having a frequency several times a sampling frequency of the audio signal; and generating the video signal based on the signal. Allocating means for allocating a fraction of the sampling frequency of the audio signal in the frame period to a predetermined number of pseudo frames. 4. A synchronizing method for synchronizing a video signal and an audio signal, wherein the synchronizing method operates at a predetermined sampling cycle according to the number of samplings per frame, counts up the number of samplings per frame, and counts up phase information. And converting the phase information within the lock range of the output phase information into phase information having an accuracy of a predetermined multiple of the sampling period, thereby limiting the phase information outside the lock range. And the synchronization method. 5. A synchronizing device for synchronizing a video signal and an audio signal, wherein the synchronizing device operates at a predetermined sampling period in accordance with the number of samplings per frame, counts up the number of samplings per frame, and outputs phase information. A conversion means for converting phase information within a lock range of the phase information output from the count means into phase information having a precision several times the sampling period; and And a limiter for limiting the external phase information.