JPH1174289A - Manufacture of semiconductor device and mask used for the manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device and mask used for the manufacture of semiconductor device

Info

Publication number
JPH1174289A
JPH1174289A JP24959197A JP24959197A JPH1174289A JP H1174289 A JPH1174289 A JP H1174289A JP 24959197 A JP24959197 A JP 24959197A JP 24959197 A JP24959197 A JP 24959197A JP H1174289 A JPH1174289 A JP H1174289A
Authority
JP
Japan
Prior art keywords
elastomer
substrate
mask
semiconductor device
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24959197A
Other languages
Japanese (ja)
Other versions
JP3339808B2 (en
Inventor
Kanta Nokita
寛太 野北
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP24959197A priority Critical patent/JP3339808B2/en
Publication of JPH1174289A publication Critical patent/JPH1174289A/en
Application granted granted Critical
Publication of JP3339808B2 publication Critical patent/JP3339808B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PROBLEM TO BE SOLVED: To manufacture a highly reliable semiconductor device by a method, wherein an elastomer is uniformly applied on a substrate from the aperture part of a mask through a reticulated sheet without the generation of a protuberance or an inclination. SOLUTION: Aperture parts 9 are formed, leaving the prescribed interval on a metal mask 8, and a reticulated sheet 10 where meshes are formed, is adhered to the upper surface of the metal mask 8 using a chemical resisting bonding agent or an emulsion. An elastomer 1 is applied to a substrate 5 in such a manner that the reticulated sheet 10 is placed on the substrate, the elastomer 1 is fed to the upper surface of the reticulated sheet 10, while the elastomer 1 is being pushed forward by a squeegee 11. When the elastomer 1 is applied, since the reticulated sheet 10 is provided on the mask 8, the elastomer 1 is pushed forward on the aperture part 9, and it streams down into a narrow strip form via meshes. As a result, the elastomer 1 can be applied uniformly with a constant thickness.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法及び半導体装置製造用マスクに関する。
The present invention relates to a method for manufacturing a semiconductor device and a mask for manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】例えばμBGAの製造においては、導体
回路パタ−ンを設けたTABテ−プ等のフレキシブルな
基板上に、弾性能のあるエラストマ−を介して半導体チ
ップを搭載し、前記基板と半導体チップの熱膨張差を吸
収する構造としている。
2. Description of the Related Art For example, in the production of a μBGA, a semiconductor chip is mounted on a flexible substrate such as a TAB tape provided with a conductive circuit pattern via an elastomer having elasticity, and the substrate is connected to the substrate. The structure is such that the thermal expansion difference of the semiconductor chip is absorbed.

【0003】エラストマ−は前記熱膨張差を吸収するに
必要な所定厚みに一様に塗布する必要がある。
[0003] The elastomer must be applied uniformly to a predetermined thickness required to absorb the difference in thermal expansion.

【0004】従来のエラストマ−塗布は、所定厚みのエ
ラストマ−とするため当該厚み分のメタルマスクを使用
し、スクリ−ン印刷により行われていた。該塗布は、開
口部を設けたメタルマスクを基板上に置き、流動状のエ
ラストマ−をスキ−ジで前記開口部から前記基板上に練
り込んでいくのであるが、スキ−ジの進行方向側の開口
部端部付近に図5(a)に示すようにエラストマ−1の
盛り上がり2が例えば30〜40μmの高さの突起が発
生する。
[0004] Conventionally, an elastomer is applied by screen printing using a metal mask of the thickness to obtain an elastomer having a predetermined thickness. In this application, a metal mask provided with an opening is placed on a substrate, and a fluid elastomer is kneaded into the substrate from the opening with a squeegee. As shown in FIG. 5 (a), a protrusion 2 of the elastomer 2 having a height of, for example, 30 to 40 .mu.m is generated near the end of the opening.

【0005】[0005]

【この発明が解決しようとする課題】前記エラストマ−
1の盛り上がり2に起因して問題が生じる。その一つ
は、半導体チップ3を搭載するため接着剤4を、図5
(b)に示すように前記エラストマ−1の盛り上がり2
をカバ−するために必要以上塗布せねばならず、その後
のダイアタッチの際に図5(C)のように接着剤4がは
み出し基板5等を汚し、その後のワイヤ−ボンディング
等に支障を及ぼす。
SUMMARY OF THE INVENTION The aforementioned elastomers
A problem arises due to the bulge 2 of 1. One of them is to apply an adhesive 4 for mounting the semiconductor chip 3, as shown in FIG.
(B) As shown in FIG.
Must be applied more than necessary in order to cover the substrate. In the subsequent die attach, as shown in FIG. 5 (C), the adhesive 4 protrudes and contaminates the substrate 5 and the like, which hinders subsequent wire bonding and the like. .

【0006】また、前記エラストマ−1の盛り上がり2
は片側だけに生じ、且つ左右で一般にその盛り上がり高
さに差異があり、図5(d)のように半導体チップ3が
傾き易いことである。これらのことから信頼性のすぐれ
た半導体装置を製造するのが難しくなる。また、前記エ
ラストマ−の厚み不同を補修するには熟練と時間を要
し、生産性を低下させる。
[0006] The swelling 2 of the elastomer-1
Is generated only on one side, and there is generally a difference in the swelling height between the left and right sides, and the semiconductor chip 3 is easily inclined as shown in FIG. For these reasons, it is difficult to manufacture a highly reliable semiconductor device. In addition, repairing the unevenness of the thickness of the elastomer requires skill and time, and lowers productivity.

【0007】さらに、従来のエラストマ−塗布に用いる
マスクは、摩耗し易く使用寿命が短く、例えば300回
程度使用で使用不能になり、コスト高にもなっている。
Further, the conventional mask used for the application of the elastomer is liable to be worn and has a short service life.

【0008】本発明は、エラストマ−を一部に盛り上が
りや傾きを生じることなく基板に所定厚みに一様に塗布
し、信頼性のすぐれた半導体装置を生産性高く得ること
を目的とする。また、使用寿命の永いマスクを得ること
を第2の目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a highly reliable semiconductor device with high productivity by uniformly applying an elastomer to a substrate to a predetermined thickness without causing swelling or inclination. A second object is to obtain a mask having a long service life.

【0009】[0009]

【課題を解決するための手段】前記目的を達成する本発
明の要旨は、導体回路パタ−ンを設けた基板の所望領域
にエラストマ−を塗布し、該エラストマ−を介し半導体
チップを搭載する半導体装置の製造方法において、前記
エラストマ−を編目状シ−トを設けたマスクの開口部か
ら前記網目状シ−トを経て基板に塗布することを特徴と
する半導体装置の製造方法にある。
The gist of the present invention to achieve the above object is to apply an elastomer to a desired region of a substrate provided with a conductor circuit pattern and to mount a semiconductor chip through the elastomer. In the method of manufacturing a device, there is provided a method of manufacturing a semiconductor device, characterized in that the elastomer is applied to a substrate from an opening of a mask provided with a stitch sheet through the mesh sheet.

【0010】他の要旨は導体回路パタ−ンを設けた基板
上に半導体チップを搭載するに先立ってエラストマ−を
塗布するマスクにおいて、網目状シ−トを、開口部を形
成したマスクに設けた半導体装置製造用マスクにある。
Another point is that in a mask for applying an elastomer before mounting a semiconductor chip on a substrate provided with a conductive circuit pattern, a mesh sheet is provided on a mask having openings. In a mask for manufacturing a semiconductor device.

【0011】[0011]

【発明の実施の形態】次に、本発明の実施例について図
1から図4を参照して説明する。図1は基板5の断面を
示すが、該基板5は、例えばフレキシブルな基板で絶縁
フィルム6と銅箔からから形成された導体回路パタ−ン
7が接着されて構成されている。基板5の所定位置に半
導体チップを搭載するためにエラストマ−1を塗布す
る。この塗布は図2に示すマスク8を基板5上に設置し
て行う。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a cross section of the substrate 5. The substrate 5 is, for example, a flexible substrate formed by bonding an insulating film 6 and a conductor circuit pattern 7 formed of a copper foil. Elastomer-1 is applied to mount the semiconductor chip at a predetermined position on the substrate 5. This application is performed by setting the mask 8 shown in FIG.

【0012】マスク8は、例えばメタルマスク製で開口
部9が所定間隔をおいて形成されていて、その上面に網
目が形成された網目状シ−ト10が対薬品性の接着剤あ
るいは乳剤等により接着されている。この接着手段につ
いては接着させるものであれば任意になされる。しか
し、接着剤は開口部9内にはみ出さないようにすること
が望ましい。網目状シ−ト10のメッシュの大きさは特
定しないが細かな網目とし、ポリエステル等の合成樹脂
あるいは金蔵等の細線により製作される。
The mask 8 is made of, for example, a metal mask and has openings 9 formed at predetermined intervals, and a mesh sheet 10 having a mesh formed on the upper surface thereof is made of a chemical-resistant adhesive or emulsion. It is adhered by. The bonding means may be arbitrarily determined as long as the bonding is performed. However, it is desirable that the adhesive does not protrude into the opening 9. Although the size of the mesh of the mesh sheet 10 is not specified, the mesh is made into a fine mesh and is made of a synthetic resin such as polyester or a thin wire such as gold.

【0013】前記基板5へのエラストマ−1の塗布は、
前記のように基板5上に網目状シ−ト10を置き、図3
に示すようにその上面にエラストマ−1を供給し、スキ
−ジ11により押し進めながら開口部9から練り込んで
前記基板5に塗布して行く。
The application of the elastomer-1 to the substrate 5 is as follows.
The mesh sheet 10 is placed on the substrate 5 as described above, and FIG.
As shown in (1), the elastomer-1 is supplied to the upper surface, kneaded from the opening 9 while being pushed by the squeegee 11, and applied to the substrate 5.

【0014】該塗布の際、マスク8には前記のように網
目状シ−ト10が設けられているので、開口部9上でエ
ラストマ−1が押し延ばされ一様な状態から網目を経て
細条にて流下し塗布される。これにより、前記スキ−ジ
11の進行方向の開口部9端部側に盛り上がりや傾きを
生じることなく一定厚みに均一に塗布される。該塗布さ
れたエラストマ−1の上面には微細な凹凸があるが、厚
みが全体を通して均一であるので問題ない。
At the time of the application, since the mesh sheet 10 is provided on the mask 8 as described above, the elastomer 1 is pushed out over the opening 9 and is made to pass through the mesh from a uniform state. It is applied down the strip. Thereby, the squeegee 11 is uniformly applied to a constant thickness without swelling or inclination on the end side of the opening 9 in the traveling direction of the squeegee 11. Although the upper surface of the applied elastomer-1 has fine irregularities, there is no problem because the thickness is uniform throughout.

【0015】その後、半導体チップ3を基板5に搭載す
るために、前記エラストマ−1上に接着剤4を塗布する
が、前記のようにエラストマ−1には突起した箇所がな
いので、薄く塗布すればよく、半導体チップ3を搭載す
る際等に接着剤4のはみ出しが全くなく、図4に示すよ
うに半導体チップ3が傾くことなく正姿勢に精度く搭載
される。
Thereafter, in order to mount the semiconductor chip 3 on the substrate 5, an adhesive 4 is applied on the elastomer 1, but since the elastomer 1 does not have any protruding portions as described above, it may be thinly applied. It is sufficient that the adhesive 4 does not protrude when mounting the semiconductor chip 3 or the like, and the semiconductor chip 3 is accurately mounted in a normal posture without tilting as shown in FIG.

【0016】これ以後、公知のように、半導体チップ3
の端子と基板5の導体回路パタ−ン7がワイヤ−(図示
しない)で接続され、当該接続部をエンキャップし、半
田ボ−ル(図示しない)等の外部端子を設置し半導体装
置が製造される。
Thereafter, as is well known, the semiconductor chip 3
And the conductor circuit pattern 7 of the substrate 5 are connected by wires (not shown), the connection portion is encapsulated, and external terminals such as solder balls (not shown) are provided to manufacture a semiconductor device. Is done.

【0017】また、前記本発明の網目状シ−ト10を設
けたマスク8は、エラストマ−1を基板5に塗布する際
の耐摩耗性が高く、摩滅が殆どなくその開口部9の形状
も永く変わらず使用寿命が大幅に例えば5倍以上に向上
する。
The mask 8 provided with the mesh sheet 10 of the present invention has a high abrasion resistance when the elastomer 1 is applied to the substrate 5, has almost no abrasion, and has a shape of the opening 9 thereof. For a long time, the service life is greatly improved, for example, by a factor of 5 or more.

【0018】[0018]

【発明の効果】本発明は、前述のようであるから基板に
エラストマ−を一定厚みに塗布でき、信頼性のすぐれた
半導体装置が製造される。また製造途中でエラストマ−
の塗布形状の修正等が不要であるので生産性が向上す
る。さらに、マスクは寿命が永くなるとともに、コスト
低減が図れる。
According to the present invention, as described above, the elastomer can be applied to the substrate to a constant thickness, and a semiconductor device having excellent reliability can be manufactured. Elastomers are also in the process of being manufactured.
Since there is no need to correct the coating shape of the coating, productivity is improved. Further, the life of the mask is extended and the cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の1実施例におけるエラストマ−を塗布
する基板を示す図。
FIG. 1 is a diagram showing a substrate on which an elastomer is applied according to an embodiment of the present invention.

【図2】本発明の1実施例におけるマスクを示す図。FIG. 2 is a diagram showing a mask according to one embodiment of the present invention.

【図3】本発明の1実施例におけるエラストマ−塗布を
示す図。
FIG. 3 is a diagram showing an elastomer coating in one embodiment of the present invention.

【図4】本発明の1実施例による半導体装置を示す図。FIG. 4 is a diagram showing a semiconductor device according to one embodiment of the present invention.

【図5】従来のエラストマ−塗布にかかわる課題を説明
するための図。
FIG. 5 is a view for explaining a problem relating to a conventional elastomer coating.

【符号の説明】[Explanation of symbols]

1 エラストマ− 2 盛り上がり 3 半導体チップ 4 接着剤 5 基板 6 絶縁フィルム 7 導体回路パタ−ン 8 マスク 9 開口部 10 網目状シ−ト 11 スキ−ジ REFERENCE SIGNS LIST 1 elastomer 2 swell 3 semiconductor chip 4 adhesive 5 substrate 6 insulating film 7 conductor circuit pattern 8 mask 9 opening 10 mesh sheet 11 squeegee

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 導体回路パタ−ンを設けた基板にエラス
トマ−を塗布し、該エラストマ−を介し半導体チップを
搭載する半導体装置の製造方法において、前記エラスト
マ−をマスクの開口部から網目状シ−トを経て基板に塗
布することを特徴とする半導体装置の製造方法。
In a method of manufacturing a semiconductor device in which an elastomer is applied to a substrate provided with a conductive circuit pattern and a semiconductor chip is mounted via the elastomer, the elastomer is meshed through an opening of a mask. A method of manufacturing a semiconductor device, wherein the method is applied to a substrate via a substrate.
【請求項2】 導体回路パタ−ンを設けた基板に半導体
チップを搭載するに先立ってエラストマ−を前記基板に
塗布するマスクにおいて、網目状シ−トを開口部を形成
したマスクに設けたことを特徴とする半導体装置製造用
マスク。
2. A mask for applying an elastomer to said substrate prior to mounting a semiconductor chip on a substrate provided with a conductive circuit pattern, wherein a mesh sheet is provided on a mask having openings formed therein. A mask for manufacturing a semiconductor device, comprising:
JP24959197A 1997-08-29 1997-08-29 Semiconductor device manufacturing method and semiconductor device manufacturing mask Expired - Fee Related JP3339808B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24959197A JP3339808B2 (en) 1997-08-29 1997-08-29 Semiconductor device manufacturing method and semiconductor device manufacturing mask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24959197A JP3339808B2 (en) 1997-08-29 1997-08-29 Semiconductor device manufacturing method and semiconductor device manufacturing mask

Publications (2)

Publication Number Publication Date
JPH1174289A true JPH1174289A (en) 1999-03-16
JP3339808B2 JP3339808B2 (en) 2002-10-28

Family

ID=17195302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24959197A Expired - Fee Related JP3339808B2 (en) 1997-08-29 1997-08-29 Semiconductor device manufacturing method and semiconductor device manufacturing mask

Country Status (1)

Country Link
JP (1) JP3339808B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007510306A (en) * 2003-10-28 2007-04-19 ダウ・コーニング・コーポレイション Method for manufacturing a pad having a flat upper surface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007510306A (en) * 2003-10-28 2007-04-19 ダウ・コーニング・コーポレイション Method for manufacturing a pad having a flat upper surface

Also Published As

Publication number Publication date
JP3339808B2 (en) 2002-10-28

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