JPH1173163A - Output circuit for liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit for liquid crystal display device low in power consumption and small in the variation of power output potential. SOLUTION: In this output circuit for liquid crystal display device having plural output buffers 16-1 to 16-n corresponding to each column line 20-1 to 20-n, analog switches 18-1 to 18-n are arranged between output ends of the buffers 16-1 to 16-n and the column lines 20-1 to 20-n, and these analog switches 18-1 to 18-n are made into OFF (open) state for the D/A conversion period or a precharge period for the D/A conversion by switch control pulses generated from a switch control pulse generating circuit 19 to cut off the output buffers 16-1 to 16-n from column line capacitance loads C1 to Cn.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an output circuit of a liquid crystal display device, and more particularly to an output circuit for a column line in a column line driving circuit of an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art An example of the structure of an active matrix type liquid crystal display device is shown in FIG. In the figure, a liquid crystal panel 102 is formed by two-dimensionally arranging liquid crystal cells (pixels) 101 in a matrix.
2 are provided with a vertical (row) driver 103 for selecting rows and a horizontal (column) driver (column line driving circuit) 104 for selecting columns.

As shown in FIG. 7, a horizontal driver 104 has a number of shift registers 111 corresponding to the number n of column lines, a shift register control circuit 112 for controlling the shift registers 111, and a sequential output from the shift registers 111. Sampling circuit 113 which samples data on the data bus line in synchronization with the sampling pulse to be sampled, a latch circuit 114 which holds the sampled data for one horizontal period, and a DA converter 115 which converts the latched data into an analog signal. And n output buffers 1 for driving the respective column lines 116-1 to 116-n
17-1 to 117-n.

[0004]

In the conventional output circuit having the above configuration, each output terminal of the output buffers 117-1 to 117-n is directly connected to the column lines 116-1 to 116-n. If the configuration of the output buffers 117-1 to 117-n has sufficient driving capability for both input and output of current, there is no particular problem.
A problem arises when 7-n is composed of, for example, a source follower circuit and has sufficient driving capability only in one direction.

In other words, the output buffer 117 is still charged until the initial state is restored after charging a large load.
If the output terminals of -1 to 117-n are connected to this load,
Sufficient characteristics or time for discharging the load is required for the output circuit. For example, when the output buffers 117-1 to 117-n are configured using a source follower circuit, the current source of the source follower circuit requires a current required to discharge a capacitive load, and therefore a large power consumption is required. Needed regularly.

[0006] Increasing the DC current value of the source follower circuit leads to a decrease in dynamic range, an increase in circuit area, and an increase in output variation at the time of offset cancellation. This is especially true for polysilicon TF
When the output buffers 117-1 to 117-n are configured by a source follower circuit using T (thin film transistor), the threshold voltage Vth of the polysilicon TFT is large and the variation in Vth is large. .

For the above reasons, it has been difficult to form an output circuit using an output buffer having one polarity. Similarly, even when an output buffer having current output capability in both directions, such as a push-pull type buffer, is used, unnecessary capacitance load is generated during the DA conversion time of the DA converter 115 and the preparation period (precharge period). It may be charged and discharged. In that case, power is unnecessarily consumed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an output circuit of a liquid crystal display device which consumes less power and has less variation in output potential.

[0009]

The output circuit of the liquid crystal display device according to the present invention has a plurality of output buffers corresponding to each column line, and a plurality of output buffers between each output terminal of the output buffers and each of the column lines. Analog switches are provided, and these switches are controlled to be opened and closed by a switch control circuit.

In the output circuit having the above configuration, the output buffer is disconnected from the column line when the analog switch is opened, and both are connected when the analog switch is closed. Therefore, the output circuit is disconnected from the capacitive load by opening the analog switch and disconnecting the output buffer and the column line during the DA conversion period of the DA converter provided before the output circuit or the precharge period for DA conversion. Therefore, the output current of the output buffer does not increase,
The signal potential can be changed sufficiently.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention applied to a column line drive circuit (horizontal driver) of a liquid crystal display device.

As is apparent from FIG. 1, the column line driving circuit according to the present invention comprises a shift register 11 having a number of stages corresponding to the number n of column lines, a shift register control circuit 12 for controlling the shift register 11, Shift register 1
A sampling circuit 13 for sampling data on a data bus line in synchronization with a sampling pulse sequentially output from 1, a latch circuit 14 for holding the sampled data for one horizontal period, and converting the latch data to an analog signal In addition to a DA converter 15 and an output circuit 17 including n output buffers 16-1 to 16-n for driving each column line, and n analog switches 18-1 to 18-n and switches The configuration has a control pulse generation circuit 19.

One end of each of the analog switches 18-1 to 18-n is connected to each output end of each of the output buffers 16-1 to 16-n. Column lines 20-1 to 20-n are connected to the other ends of the analog switches 18-1 to 18-n. These column lines 20-1 to 20-n have capacitive loads C1 to Cn. The switch control pulse generation circuit 19 turns on (closes) / off (opens) the analog switches 18-1 to 18-n.
Generates a switch control pulse for performing control.

More specifically, the switch control pulse generation circuit 19 supplies the analog switches 18-1 to 18 during a period in which the DA converter 15 performs DA conversion or a preparation period (precharge period) in which pre-charge for DA conversion is performed. output buffers 16-1 to 16-n
And the column lines 20-1 to 20-n are disconnected, and the analog switches 18-1 to 18-n are turned on only for a certain period to connect them.

FIG. 2 shows an example of the configuration of output buffers 16-1 to 16-n using a source follower circuit. In the figure, one end of a first capacitor 23 is connected to the gate of an NMOS source follower transistor 21, and a first analog switch 25 is provided between the gate of the source follower transistor 21 and a precharge power supply 24.
A second analog switch 26 is connected between the other end of the first capacitor 23 and the source of the source follower transistor 21.
However, a third analog switch 27 is connected between the other end of the first capacitor 23 and the signal source (Vin).

An NMOS transistor 28 is cascode-connected to the drain side of the source follower transistor 21, and the source follower transistor 21
A second capacitor 29 is connected between the gate of the cascode connection transistor 28 and the gate of the cascode connection transistor 28.
The fourth analog switch 31 is connected between the power supplies 30 of c. The voltage value Vc of the power supply 30 is set to a value shifted from the voltage value of the precharge voltage Vpre of the source follower transistor 21 by a certain amount. The shift amount is obtained from the saturation condition of the source follower transistor 21 and the cascode connection transistor 28.

Next, the circuit operation of the source follower circuit having the above configuration will be described with reference to the timing chart of FIG.

First, in the precharge period T1, the first and second analog switches 25 and 26 are turned on, and the third analog switch 27 is turned off. As a result, a specific precharge voltage Vpre is applied to the gate of the source follower transistor 21 from the precharge power supply 24 via the first analog switch 25. At this time, a charge corresponding to the offset Vos (= Vgs) is accumulated in the first capacitor 23 connected between the gate and the source of the source follower transistor 21.

Thereafter, in the output period T2, the first and second analog switches 25 and 26 are turned off, and the third analog switch 27 is turned on. As a result, the other end of the first capacitor 23 (the source side of the source follower transistor 21) is reconnected to the input signal Vin side (the signal source side), and the gate of the source follower transistor 21 is disconnected from the precharge power supply 24. . At this time, the gate potential of the source follower transistor 21 is Vin
+ Vos.

As a result, the source follower transistor 2
Offset V corresponding to one gate-source voltage Vgs
Even if os 'occurs, offset cancellation is performed because Vos' = Vos (that is, Vos-
Vos'), the output potential Vout in the output period T2.
Is almost the same as the input potential Vin. This is equivalent to reducing output potential fluctuations due to variations in transistor characteristics.

In the precharge period, the first and second
Similarly to the analog switches 25 and 26, the fourth analog switch 31 is also turned on to precharge the gate of the cascode connection transistor 28 to the voltage value Vc. Then, by turning off the fourth analog switch 31 during the output period, the gate of the cascode connection transistor 28 is disconnected from the power supply 30.

Turning on / off of the fourth analog switch 31
By the OFF operation, the gate potential of the cascode connection transistor 28 can be set higher than the power supply voltage VCC, so that the drain voltage of the source follower transistor 21 increases. Accordingly, even if a source follower circuit is configured using a transistor having a high threshold voltage Vth and a large variation such as a polysilicon TFT as the source follower transistor 21, as a result, the drain voltage range of the transistor 21 is increased. Therefore, the dynamic range of the output can be expanded.

Further, in the above-described circuit configuration, the precharge of the first capacitor 23 can be performed by the independent precharge power supply 24 instead of the signal source, so that the output impedance of the signal source does not need to be extremely small. The advantage associated with this is extremely large when the present source follower circuit is used as an output circuit of a reference voltage selection type DA converter in a horizontal driver of a liquid crystal display device. That is, since the line width of the reference voltage line can be reduced, the area of the entire circuit can be reduced.

The above-described effect of the circuit operation is particularly effective when the source follower circuit is formed of a polysilicon TFT. The reason is as follows. That is, since the polysilicon TFT has no substrate potential, there is no substrate bias effect. Therefore, even when the input voltage (the input potential of the source follower transistor 21) changes and the output voltage (the source potential of the source follower transistor 21) changes, the threshold voltage Vth does not change.
The offset cancel operation is performed with high accuracy. Also,
Since there is no substrate potential, the parasitic capacitance on one end side (the base side of the source follower transistor 21) of the first analog switch 25 becomes small, and the source follower transistor 2
Even when the base potential of the first capacitor changes, the offset charge accumulated in the first capacitor 23 does not easily escape.

FIG. 4 shows a specific configuration when the source follower circuit having the above-described offset canceling structure is used as an output circuit in a column line driving circuit. Note that FIG. 4 shows only the circuit configuration for a certain column line 20-k, and in the figure, the same parts as those in FIG. 2 are denoted by the same reference numerals.

In this specific example, the D / A converter 15 provided before the output circuit 17 includes the upper three bits b0 to b
2 and a switched capacitor array type DA converter 42 for the lower three bits b3 to b5, respectively, the capacitor of the switched capacitor array type DA converter 42 is used. In this case, the offset follower capacitor 23 of the source follower circuit having the above configuration is used.

That is, four capacitors 4 provided corresponding to the lower three bits b3 to b5 and having one end commonly connected to the gate of the source follower transistor 21
The combined capacitance of 3, 44, 45 and 46 corresponds to the capacitor 23 for offset storage. Here, the capacitance ratio of the four capacitors 43, 44, 45, 46 is 4Co: 2Co:
Co: Co is set to be Co.

Further, four analog switches 47 to 50 connected between the other ends of the capacitors 43 to 46 and the source of the source follower transistor 21 are connected to the second analog switch 26, respectively. Four analog switches 51 to 54 connected between the ends and the signal source
Correspond to the third analog switches 26, respectively. The opening and closing of the analog switches 25 and 47 to 50 are controlled by a precharge pulse control circuit 55.

On the other hand, an analog switch 18-k provided between the output terminal of the output buffer 16-k and the column line 20-k.
Is controlled by a switch control pulse generated by a switch control pulse generation circuit 19. In particular,
As shown in the timing chart of FIG. 5, the analog switch 18-k is turned off during the precharge period and the DA conversion period. Then, it is turned on only during other specific periods.

As described above, the lower three bits b3 to b5
In a column line drive circuit of a liquid crystal display device including a DA converter 14 having a switched capacitor array type on the side, a source follower circuit having an offset cancel structure is used as output buffers 16-1 to 16-n. Since the capacitor 23 for offset storage and the capacitor of the switched capacitor array type DA converter 42 can also be used, the number of newly added circuit elements can be reduced, and the efficiency is high.

Generally, the output current of the source follower circuit as shown in FIG. 4 can be obtained without limitation at the time of rising of the signal, but the current source 2 at the time of falling of the signal.
2 can be obtained only up to the magnitude of the current Iref. Therefore, if a large output load is connected when the signal falls, the signal cannot be changed sufficiently. Alternatively, in order to sufficiently change the signal, a large value of the current Iref is required.

However, in the present invention, when the signal potential decreases significantly during the precharge period or the like, the analog switch 18-k is turned off during these periods, and the output buffer 16-k is disconnected from the capacitive load Ck. Therefore, the output current of the source follower circuit does not increase,
The signal potential can be changed sufficiently. In other words, a sufficient output circuit can be configured with a small value of the current Iref. Note that the output period for turning on the analog switch 18-k may be set to a specific period other than the precharge period and the DA conversion period.

Further, forming the output circuit with a small value of the current Iref leads to suppressing the variation in the output potential. The reason will be described below.

Generally, the offset potential Vgs of the source follower circuit (gate-source voltage of the source follower transistor 21) is expressed by the following equation. Vgs = Vth + √ (Iref / k) where k = 0.5 × μ × Cox × W / L. Here, k is a constant, and Cox, W, and L are the oxide film capacitance, gate length, and gate width of the transistor, respectively.

Therefore, as the value of the current Iref increases, the offset potential Vgs increases. This generally leads to a reduction in the output dynamic range of the circuit. In other words, the transistor size must be increased to secure a dynamic range. If the value of the current Iref is small, the transistor size can be reduced, so that the area of the circuit can be reduced.

When the value of the current Iref is large, the variation of the offset potential Vgs with respect to the variation of the constant k (that is, the variation of the device characteristics of the transistor) becomes large. Such a relationship basically does not change even when an offset canceling structure as shown in FIG. 2 (FIG. 4) is employed. Therefore, a decrease in the value of the current Iref leads to a reduction in output variations.

The source follower circuit having the above-described offset cancel structure is particularly useful when a column line drive circuit (horizontal driver) is formed integrally with a liquid crystal panel using a polysilicon TFT. The reason is as follows. The polysilicon TFT has a very large variation in the constant k. The gate bias effect and the parasitic capacitance are small, and it is easy to form a source follower circuit having an offset cancel structure.

As described above, according to the present invention, in an output circuit of a liquid crystal display device having a plurality of output buffers corresponding to each column line, an analog switch is provided between the output terminal of the output buffer and the column line. By controlling the opening and closing of the analog switch, when the analog switch is open, the output buffer and the column line are disconnected, and the output circuit is disconnected from the capacitive load, so that the output current of the output buffer does not increase. Therefore, a system for charging a column line load with a one-way current buffer can be easily configured, power consumption can be reduced, a circuit area can be reduced, a wide dynamic range can be achieved, and variations in output potential can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of an output buffer using a source follower circuit.

FIG. 3 is a timing chart for explaining the operation of the circuit in FIG. 2;

FIG. 4 is a circuit diagram showing a specific application example of the present invention.

FIG. 5 is a timing chart for explaining the operation of the present invention.

FIG. 6 is a schematic configuration diagram illustrating an example of an active matrix liquid crystal display device.

FIG. 7 is a block diagram illustrating an example of a configuration of a horizontal driver (column line driving circuit).

[Explanation of symbols]

11 shift register, 13 sampling circuit, 14
... Latch circuit, 15 ... DA converter, 16-1 to 16-n
... output buffer, 17 ... output circuit, 18-1 to 18-n, 2
5 to 26, 31: analog switch, 19: switch control pulse generation circuit, 20-1 to 20-n: column line, 21:
Source follower transistor, 22 ... current source, 23, 2
9: capacitor, 24: precharge power supply, 28: cascode connection transistor, 41: reference voltage selection type DA converter, 42: switched capacitor array type DA converter

Claims (4)

[Claims] 1. An output circuit of a liquid crystal display device having a plurality of output buffers corresponding to each column line, comprising: a plurality of analog circuits provided between output terminals of the plurality of output buffers and each of the column lines. An output circuit for a liquid crystal display device, comprising: a switch; and a switch control circuit that controls opening and closing of the plurality of analog switches. 2. The liquid crystal display device according to claim 1, further comprising a D / A converter in a stage preceding the output circuit, wherein the switch control circuit is configured to switch the analog switch during a D / A conversion period of the D / A converter or a D / A conversion precharge period. 2. The output circuit according to claim 1, wherein the analog switch is in an open state, and the analog switch is in a closed state in other specific periods. 3. Each of the plurality of output buffers includes a first capacitor having one end connected to a gate of a source follower transistor, and a first capacitor connected between a gate of the source follower transistor and a precharge power supply. An analog switch, a second analog switch connected between the other end of the first capacitor and the source of the source follower transistor, and interlocking with the first analog switch; and an other end of the first capacitor. A third analog switch that is connected between the signal sources and performs an inversion operation with respect to the opening and closing operation of the first and second analog switches; and a cascode connection transistor cascode-connected to a drain side of the source follower transistor. ,
A second capacitor connected between the gate of the source follower transistor and the gate of the cascode connection transistor, and a first capacitor connected between the gate of the cascode connection transistor and a predetermined power supply; 2. The output circuit according to claim 1, further comprising a source follower circuit including a fourth analog switch interlocked with the first analog switch. 4. The output circuit according to claim 3, wherein the source follower circuit is constituted by a polysilicon thin film transistor.