JPH1166025A - Arbitration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arbitration circuit with which the bias in the processing between request system and a reply system is reduced and the throughput of an entire system can be prevented from being lowered. SOLUTION: A request system arbitration circuit 1 arbitrates the transfer request of the request system, and a reply system arbitration circuit 2 arbitrates the transfer request of the reply system. A switching flip-flop 3, AND circuits 8-13 and 16-19, OR. circuit 14 and exclusive OR circuit 15 suppress the output of the result of one processing operation during the processing operation between the request system and reply system arbitration circuits 1 and 2 and permit the output of the result of one processing operation after the completion of the other processing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration circuit, and more particularly to an arbitration method for switching requests such as inter-node communication and data transfer from each node in a crossbar switch.

[0002]

2. Description of the Related Art Conventionally, there is a crossbar switch for realizing a multi-node model in which a single node model (up to 32 processors) is used as a node and 2 to 16 nodes are used as a single system connected in a cluster. .

In this crossbar switch, switching requests such as inter-node communication and data transfer from each node are received, and the switching requests are arbitrated to perform switching.

As an arbitration method for a request for use of a transmission path in inter-node communication or data transfer, a bus arbiter provided in a general-purpose system bus used for an information processing apparatus uses a bus arbiter for a unit connected to the bus. There is a centralized arbitration method that grants authority. This concentrated arbitration method is disclosed in Japanese Patent Laid-Open No. 5-1349.
No. 81 discloses this.

In the centralized arbitration method described in the above publication, a plurality of units connected to a bus request a bus use right to a bus arbiter, and thereafter, only when the bus arbiter permits use of the bus. In a device which can use a bus, a bus use request signal from each unit is temporarily held, and the bus use request signal held until all the held bus use request signals are cleared by acquisition of a use right is cleared.
At each turn, a plurality of priority circuits, each having a different priority order, give different priorities to the held bus use request signals, so that each unit is equally given the right to use the bus. ing.

FIG. 4 shows the configuration of the above bus arbiter.
Hereinafter, the centralized arbitration method described in the above publication will be described with reference to FIG. Here, the bus arbiter 60 includes AND circuits 61 to 65, flip-flops (hereinafter, referred to as FFs) 66 to 69, a select circuit 70,
It is composed of priority (PRIORITY) circuits 71 to 74 having different priorities of the set units, and a multiplexer 75.

The bus use requests BRQ1 to BRQ4 asserted from each unit (not shown) are transmitted to the bus arbiter 60.
Are latched by the FFs 66 to 69 at the same time.
The latched bus use requests BRQ1 to BRQ4 are first taken into the priority circuit 71, and the bus use permission BGR1 to BGR4 is asserted for a unit having a higher priority defined by the priority circuit 71.

When the bus use permission BGR1 to BGR4 is asserted, the asserted bus use permission BGR1 to BGR1
FFs 66 to 69 are cleared by GR4. When the data transfer end CPT is asserted for the asserted bus use permission BGR1 to BGR4, the currently used bus use permission BGR1 to BGR4 is negated. At this time, the bus use permission BGR1 to BGR4 is asserted to the next unit having the highest priority among the bus use requests BRQ1 to BRQ4 latched by the FFs 66 to 69. The above processing operation is performed until the bus use requests BRQ1 to BRQ4 latched in the FFs 66 to 69 disappear.

Next, when all the FFs 66 to 69 latching the bus use requests BRQ1 to BRQ4 are cleared, the next bus use request BR asserted at that time is cleared.
Q1 to BRQ4 are latched by the FFs 66 to 69 at the same time. At this time, the asserted bus use permission B
When the data transfer end CPT for GR1 to BGR4 is asserted, the FF 66 is
６９69 are changed from the priority circuit 71 to the priority circuit 72.

In this case, the bus use requests BRQ1 to BRQ4 latched by the FFs 66 to 69 are taken into the priority circuit 72 whose unit priority is different from the priority circuit 71, and the bus use requests latched by the FFs 66 to 69. Until all of BRQ1 to BRQ4 are cleared, the bus use permission BGR1 to BGR4 is set in order from the unit having the highest priority determined by the priority circuit 72.
Asserts.

Thereafter, the above-described processing operation is sequentially performed by the priority circuit 73 → the priority circuit 74, and thereafter, the process returns to the priority circuit 71 and is performed in the same order as described above. This makes it possible to equally give the right to use the bus to a plurality of units.

[0012]

In the above-described conventional arbitration method, data transfer requests from a plurality of devices constituting the system are divided into (A) system / (B) system and processed by either one system. If the processing capacity of the entire system is reduced if the processing is biased, if all requests are processed by one arbitration circuit as in the related art, the (A) system /
(B) The processing between the two systems is biased, and the processing performance of the entire system is reduced.

For example, when a read request is sent from the device A to the device B, and data is transferred from the device B to the device A in response to the read request, a transfer request when the read request is sent from the device A to the device B is sent. Is a request transfer request, and a transfer request at the time of data transfer from the device B to the device A is a reply transfer request.

In this case, if the processing in the arbitration circuit is biased toward a request-based transfer request or the response-based transfer request is biased, the device cannot obtain the requested data. Therefore, a deadlock may occur and the system may be stopped. that time,
The processing capacity of the entire system is reduced.

Therefore, an object of the present invention is to solve the above-mentioned problems, to reduce the processing bias between the (A) system / (B) system (request system / reply system), and to provide an overall system. Arbitration circuit capable of preventing a reduction in the processing capacity of the arbitration.

[0016]

SUMMARY OF THE INVENTION An arbitration circuit according to the present invention provides a first transfer request for requesting data transfer when performing data transfer between a plurality of devices capable of mutually transferring data, and the data transfer. An arbitration circuit that arbitrates a second transfer request for performing the first transfer request, a first arbitration unit that arbitrates the first transfer request, and a second arbitration unit that arbitrates the second transfer request. Issuing means for alternately issuing transfer permission for the first transfer request arbitrated by the first arbitration means and transfer permission for the second transfer request arbitrated by the second arbitration means; ing.

That is, the arbitration circuit of the present invention has a plurality of devices constituting a system, and when performing data transfer between two devices in a configuration in which each of the devices can mutually transfer data, the data transfer is performed. And a second arbitration circuit for arbitrating a transfer request for performing the data transfer.

A device that performs data transfer issues a transfer request to an arbitration circuit of a data transfer destination. Here, the transfer request is divided into (A) system / (B) system, and is taken into separate first and second arbitration circuits ((A) arbitration circuit and (B) arbitration circuit). It is. However, the fetch timing is when all the transfer requests in the respective arbitration circuits have been processed.

Each of the arbitration circuit (A) / arbitration circuit (B) selects the transfer source device having the highest priority among the fetched transfer requests. A transfer permission is given to one of the transfer source devices selected by the (A) system arbitration circuit / (B) system arbitration circuit.

Here, when permission is given to the (A) system, after all transfer requests taken into the arbitration circuit of the (A) system are processed, the transfer to the (B) system is performed. Permission is given. Thereafter, the (A) system / (B) system is alternately switched in this manner.

However, when the (A) / (B) data buffers are separately present, the transfer cannot be performed because there is no free space in the buffer of the transfer destination device of the system to which the transfer permission is currently given. In this case, transfer of the other system is performed until transfer becomes possible.

As a result, it is possible to reduce the processing bias between the (A) system / (B) system (request system / reply system) and to prevent a reduction in the processing capacity of the entire system. Become.

[0023]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an arbitration circuit according to one embodiment of the present invention. In the figure, an arbitration circuit according to one embodiment of the present invention includes a request arbitration circuit 1, a reply arbitration circuit 2, a switching flip-flop (hereinafter, referred to as FF) 3, a selector 4, an encoder 5, a request Data buffer 6-i (i
= 1,...) And the reply data buffer 7-j (j
= 1,...) And AND circuits 8-13, 16-19,
An OR circuit 14 and an exclusive OR circuit 15 are provided.

The request-related arbitration circuit 1 includes transfer request signals STA11 and STA11 from the request-related data buffer 6-i.
1, 31, 41 and the transfer end signals END 11, 21, 3
1, 41 are input to arbitrate the transfer requests of the request system, and the arbitration results TYO 11, 21, 31, 41 are output.

The reply arbitration circuit 2 transfers transfer request signals STA12, STA22, STA22 from the reply data buffer 7-j.
32, 42 and transfer end signals END12, 22, 32, 4
2 to arbitrate the transfer request of the reply system and output the arbitration results TYO 12, 22, 32, 42.

Switching flip-flop 3 and AND circuit 8
, 13, 16 to 19, the OR circuit 14, and the exclusive OR circuit 15, when one of the request arbitration circuit 1 and the reply arbitration circuit 2 is processing, the output of the result of the other processing operation is output. When one processing operation is completed, the output of the result of the other processing operation is permitted.

That is, when “0” is input from the exclusive OR circuit 15, the AND circuits 8 to 11 receive the arbitration results TYO 11, 21, 31, 4 from the request-related arbitration circuit 1.
1 is output as transfer permission CHO 11, 21, 31, 41. When "1" is input from the exclusive OR circuit 15, the AND circuits 16 to 19 transfer the arbitration results TYO12, 22, 32, and 42 from the reply arbitration circuit 2 to the transfer permission CH.
Output as O12,22,32,42.

The selector 4 comprises AND circuits 8-11, 16-
19, the encoding result of the output of the encoder 5 is input as a select signal SEL, and the select signal SE
According to L, one of the data stored in the request data buffer 6-i and the data stored in the reply data buffer 7-j is selected and output.

FIG. 2 is a block diagram showing the configuration of the request arbitration circuit 1 of FIG. In the figure, a request arbitration circuit 1 includes AND circuits 21 to 28, 34 to 37, and 39.
, The transfer request holding FFs 29 to 32, and the NOR circuit 3
3 and off circuits 38 and 43. still,
Although not shown, the reply arbitration circuit 2 has the same configuration as the request arbitration circuit 1.

FIG. 3 is a block diagram showing a system configuration according to an embodiment of the present invention. In the figure, a system according to an embodiment of the present invention includes four nodes 51 to 54 and a crossbar switch 5 for switching between the nodes 51 to 54.
And 5.

The crossbar switch 55 includes the above-described arbitration circuit, and data sent from each of the nodes 51 to 54 is stored in the request data buffer 6-i and the reply data buffer 7-j.

The arbitration operation of the arbitration circuit according to one embodiment of the present invention will be described with reference to FIGS.

The request-related data buffer 6-i and the reply-related data buffer 7-j are respectively divided into one for the node 51, one for the node 52, one for the node 53, and one for the node 54. The obtained data is stored in the corresponding data buffers.

When the data is stored, the request data buffer 6-i sends a transfer request signal STA to the request arbitration circuit 1 corresponding to the transfer destination node of the data.
When the data is stored, the reply data buffer 7-j issues a transfer request signal STA12,22,21 to the reply system arbitration circuit 2 corresponding to the transfer destination node of the data. 32 and 42 are issued.

When all of the transfer request holding FFs 29 to 32 holding the transfer requests fetched in the request arbitration circuit 1 and the reply arbitration circuit 2 become "0", the request arbitration circuit 1 and the reply arbitration circuit 2 receives new transfer request signals STA1 to STA4.

Here, the data buffer on the destination node side is flow-controlled by a flow counter (not shown) provided in the crossbar switch 55, and among the received transfer requests, the information transmitted together with the transfer request is included. Comparing the included data transfer amount with the free space of the data buffer of the data transmission destination, when the data transfer amount is larger, the hold signal H
Since the LDs 1 to 4 are set to be in the hold state, the transfer request cannot participate in the arbitration.

When all the transfer requests that can participate in arbitration disappear, the signal ERQ becomes "1". The hold signals HLD1 to HLD4 become "0" when the free space of the data buffer of the data transmission destination becomes larger than the data transfer amount. Then, the request arbitration circuit 1 and the reply arbitration circuit 2 arbitrate the transfer requests that are not in the hold state among the fetched transfer requests and set one of the arbitration results TYO1 to TYO4 to “1”.

When the arbitration results of the request arbitration circuit 1 and the reply arbitration circuit 2 become valid, one of the transfer permission CHO1 to CHO4 is "1".
When the transfer is started and the transfer end signals END1 to END4 become "1", the transfer request holding FFs 29 to 32 become "0".
And the transfer ends. Transfer request holding FFs 29 to 32
Transfer end signal EN for the remaining one transfer request
When D1 to D4 become "1", the signal TRM becomes "1".

Next, the switching procedure of the request arbiter 1 and the reply arbiter 2 when all the transfer requests are not in the hold state, that is, when the signal ERQ is "0" will be described.

When the switching FF3 is "0", the arbitration results TYO11, 21, 31, 41 of the request-related arbitration circuit 1 become valid, and the transfer permission CHOs 11, 21, 31, 41 become "1". Then, the last transfer data corresponding to the arbitration request taken into the request arbitration circuit 1 is output, and at the same time when the signal TRM1 becomes "1", the switching FF is output.
3 is set.

As a result, the arbitration results TY012, 22, 32, and 42 of the reply arbitration circuit 2 become valid, and the transfer permission CH012, 22, 32, and 42 become "1".
Then, the last transfer data corresponding to the arbitration request taken into the reply arbitration circuit 2 is output, and the signal TRM2
Becomes "1" at the same time, the switching FF3 is reset.

A description will now be given of the processing when a hold occurs in a case where the data buffer on the destination node side is divided into a request system and a reply system and flow control is performed separately for each.

When the switching FF3 is "0" and all the transfer requests that can participate in arbitration disappear before all the transfer requests taken into the request arbitration circuit 1 disappear (signal TR).
If the signal ERQ1 becomes "0" before M1 becomes "1", and if there is a transfer request that can be transferred to the reply arbitration circuit 2 (signal ERQ2 is "1"), it is related to the contents of the switching FF3. And the transfer of the reply arbitration circuit 2 is performed.

Request arbitration circuit 1 which should originally perform transfer
To enable transfer (signal ERQ1 becomes "1")
Then, the transfer of the request arbitration circuit 1 is restarted after the transfer of the transfer performed by the reply arbitration circuit 2 is completed (the transfer end signals END12, 22, 32, and 42 are "1"). When the switching FF3 is "1", the same processing operation is performed.

As described above, the transfer request is arbitrated by dividing it into the request system and the reply system, the transfer permission is given to one of the systems (two-stage arbitration), and the transfer request is taken into the arbitration circuit of the system. When all of the transfer requests that have been completed are completed, a transfer permission is given to the other system, so that transfer requests from a plurality of devices are transferred to the (A) system / (B) system (request system /
Replies), two (A) /
(B) Processing bias among systems can be reduced, and a reduction in the processing capacity of the entire system can be prevented.

Here, in the above-described processing, a plurality of transfer requests are input to the request-related arbitration circuit 1 and the reply-related arbitration circuit 2 at a time from each of the nodes 51 to 54, respectively. The arbitration circuit 1 and the reply arbitration circuit 2 are configured to process the plurality of transfer requests one by one.

In this case, in the above processing, the other processing is not performed until one of the request arbitration circuit 1 and the reply arbitration circuit 2 processes all of the plurality of transfer requests. Each time one of the plurality of transfer requests is completed, one of the reply arbitration circuits 2 may perform the other process.

The present invention can take the following aspects in connection with the description of the claims.

(1) When performing data transfer between a plurality of devices capable of mutually transferring data, a request transfer request for requesting the data transfer and a reply transfer request for performing the data transfer are arbitrated. An arbitration circuit,
Request arbitration means for arbitrating the request transfer request; reply arbitration means for arbitrating the reply transfer request; transfer permission for the request transfer request arbitrated by the request arbitration means; and reply arbitration. Issuing means for alternately issuing transfer permission for the reply transfer request arbitrated by the means.

(2) The issuing means issues all transfer requests for the request-related transfer requests incorporated in the request-related arbitration means, and thereafter issues all transfer-related transfer requests incorporated in the reply-related arbitration means. (1) wherein the transfer arbitration circuit is configured to issue a transfer permission to the arbitration circuit.

(3) The request arbitration means is configured to fetch the request transfer request after all the replies transfer request received by the reply arbitration means are processed. The arbitration according to (1) or (2), wherein the means is configured to fetch the reply transfer request after all the request transfer requests taken into the request arbitration means are processed. circuit.

(4) The request arbitration means and the reply arbitration means are each configured to select the fetched request transfer request and the reply transfer request based on their priority. The arbitration circuit according to any one of (1) to (3).

(5) When the transfer corresponding to the arbitrated transfer request is disabled in one of the request arbitration means and the reply arbitration means, the request system arbitration means continues until the transfer by the transfer request becomes possible. The arbitration circuit according to any one of (1) to (4), wherein the arbitration circuit is configured to perform a transfer corresponding to the transfer request arbitrated by the other of the arbitration unit and the reply arbitration unit.

[0054]

As described above, according to the present invention, when performing data transfer between a plurality of devices capable of mutually transferring data, a request-related transfer request for requesting the data transfer and the data transfer are performed. Request arbitration means for arbitrating a request transfer request, a reply arbitration means for arbitrating a reply transfer request, and a request arbitration means arbitrated by the request arbitration means. By alternately issuing a transfer permission for the transfer request and a transfer permission for the reply transfer request arbitrated by the reply arbitration means,
It is possible to reduce the processing bias between the request system and the reply system, and to prevent a reduction in the processing capacity of the entire system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an arbitration circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a request arbitration circuit of FIG. 1;

FIG. 3 is a block diagram illustrating a system configuration according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of an arbitration circuit according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Request system arbitration circuit 2 Reply system arbitration circuit 3 Switching flip-flop 4 Selector 5 Encoder 6-1 Request system data buffer 7-1 Reply system data buffer 8-13, 16-19 AND circuit 14 OR circuit 15 Exclusive OR circuit

Claims (5)

[Claims] 1. A method for arbitrating a first transfer request for requesting a data transfer and a second transfer request for performing the data transfer when performing data transfer between a plurality of devices capable of mutually transferring data. An arbitration circuit that arbitrates the first transfer request, a second arbitration unit that arbitrates the second transfer request, and the arbitration circuit that is arbitrated by the first arbitration unit. An arbitration circuit comprising: issuing means for alternately issuing a transfer permission for a first transfer request and a transfer permission for the second transfer request arbitrated by the second arbitration means. 2. The issuing means according to claim 1, wherein said issuing means issues a transfer permission for all of said first transfer requests taken in by said first arbitration means, and thereafter issues said second permission received by said second arbitration means.
2. The arbitration circuit according to claim 1, wherein a transfer permission is issued for all the transfer requests. 3. The first arbitration means is configured to fetch the first transfer request after all of the second transfer requests fetched by the second arbitration means are processed, Second
2. The arbitration means according to claim 1, wherein said second transfer request is fetched after all of said first transfer requests fetched by said first arbitration means have been processed. Item 2. The arbitration circuit according to Item 2. 4. The first arbitration unit and the second arbitration unit each receive the first transfer request and the second
4. The arbitration circuit according to claim 1, wherein each of the transfer requests is selected based on its priority. 5. When the transfer corresponding to the transfer request arbitrated by one of the first arbitration means and the second arbitration means becomes impossible, the transfer is performed until the transfer by the transfer request becomes possible. 5. The arbitration circuit according to claim 1, wherein a transfer corresponding to the transfer request arbitrated by the other of the first arbitration unit and the second arbitration unit is performed.