JPH1165978A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer which can read the contents of a control command or the like outputted to a peripheral device dedicated to outputting. SOLUTION: When the address of the peripheral device such as a timer 60 is designated from a CPU 10 through an address bus 21 and the control command is outputted to a data bus 22, the same control command is written in the timer 60 and a memory 61 in which the same address as this timer is written. When reading the control command set to the timer 60 by a CPU 10, on the other hand, the control command held in the memory 61 is outputted to the data bus 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a function of reading control information and the like for peripheral devices.

[0002]

2. Description of the Related Art FIG. 2 is a schematic block diagram showing an example of a conventional microcomputer. This microcomputer has a central processing unit (hereinafter referred to as a “CPU”) 10.
The CPU 10 has a read-only memory (hereinafter referred to as “ROM”) 3 via a common bus 20.
0, and a readable / writable memory (hereinafter, “RAM”)
40) are connected. The common bus 20 has a CP
An address bus 21 for transferring an address signal ADR output from U10, a data bus 22 for transferring a data signal DATA between the CPU 10 and the ROM 20, etc., and a read control for the CPU 10 to input the data signal DATA. Read control line 2 for outputting signal RD
3, and a write control line 2 for outputting a write control signal WR for the CPU 10 to output the data signal DATA
4 and so on. The ROM 30 is, for example, 000
Address H (however, "H" means hexadecimal notation)-1F
This is a memory to which an address of the address FH is assigned and in which a data processing program and fixed data are stored. on the other hand,
The RAM 40 is a memory to which, for example, addresses of addresses 200H to 2FFH are assigned and data for processing is stored.

The address bus 21 is connected to an address decoder 50. The address decoder 50 decodes the address signal ADR and outputs, for example, addresses 300H, 3
It outputs a selection signal for an individual address such as address 01H. On the output side of the address decoder 50,
For example, output-only peripheral devices such as a timer 60 and a serial port 70, and input / output units 80 and 90 capable of input and output such as a parallel input / output device are connected. These timer 60, serial port 70, input / output unit 80,
90 is connected to the CPU 10 via a data bus 22, a read control line 23, a write control line 24, and the like. In such a microcomputer, the CPU
An address signal ADR is sequentially output from 10 to an address bus 21, and at the same time, a read control signal RD or a write control signal WR is output to a read control line 23 or a write control line 24. ROM30, RAM4
0, timer 60, serial port 70, and input / output unit 8
0, 90, etc., when specified by the address signal ADR, output the data signal DATA to the data bus 22 or take in the data signal DATA output on the data bus 22. I have. CPU
10 sequentially reads out the programs stored in the ROM 30 and, according to the read out programs, the RAM 40
And executes data processing by accessing a peripheral device such as a memory or a timer 60.

[0004]

However, the conventional microcomputer has the following problems.
That is, for example, after outputting a control command from the CPU 10 to an output-only peripheral device such as the timer 60, the CPU 10 may need to read the control command. However, the timer 60 does not have a function of outputting the set control command to the data bus 22. Therefore, the CPU 10 previously sets a specific address (for example, address 2F0H) in the RAM 40 as a storage area for storing a control command for the timer 60, and writes the control command to the timer 60 (that is, address 300H). , A more specific address (ie, 2F
0H) is written in the same control command. When the control command for the timer 60 is read, the address 2F0H of the RAM 40 is read. As described above, in setting a control command for an output-only peripheral device, it is necessary to write the same control command at two different addresses, which increases the processing time and the number of program steps. An object of the present invention is to solve the problem of the prior art and to provide a microcomputer capable of reading the contents of control commands and the like output to peripheral devices dedicated to output.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a microcomputer which performs digital processing based on a processing program including a data processing instruction and an external input / output instruction, and performs address processing together with an address signal. A CPU that outputs output data by outputting a write control signal and inputs input data by outputting a read control signal together with the address signal; and a CPU that outputs the output data and the input data that are output from the CPU. A data bus for transferring the input data to be processed, the processing program and the data for digital processing, and a plurality of storage areas for storing the data for digital processing and the processing program. A first address given a series of first addresses identifying And a peripheral function for receiving the output data on the data bus when a second address different from the first address is assigned and specified by the address signal and the write control signal is given. And a second address same as that of the peripheral function unit. The output data on the data bus is held when the write control signal is given while the address is specified by the address signal. When specified by a signal and the read control signal is given,
Outputting the held output data onto the data bus;
Storage means.

According to the present invention, since the microcomputer is configured as described above, the following operation is performed. When the second address given to the peripheral function unit is specified by an address signal output from the CPU and a write control signal is applied, the peripheral function unit fetches output data on the data bus. At the same time, the output data on the data bus is held by the second storage unit to which the same second address as that of the peripheral function unit is assigned. Next, when the second address assigned to the peripheral function unit is specified by the address signal output from the CPU and the read control signal is applied, the output data held in the second storage means is changed to the data Output on the bus.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram of a microcomputer showing a first embodiment of the present invention. Elements common to those of the conventional microcomputer shown in FIG. Is attached. This microcomputer has a CPU 10 similar to that of FIG. The CPU 10 performs digital processing based on a processing program including a data processing instruction, an external input / output instruction, and fixed data for data processing. C
The PU 10 has a function of outputting output data by outputting a write control signal WR together with the address signal ADR, and has a function of inputting input data by outputting a read control signal RD together with the address signal ADR. The CPU 10 has first storage means (for example, the ROM 30 and the RAM 4
0) is connected. The common bus 20 includes an address bus 21 for transferring an address signal ADR output from the CPU 10, a data bus 22, for transferring a data signal DATA between the CPU 10 and the ROM 20, and the like.
A read control line 23 for outputting a read control signal RD for the PU 10 to input the data signal DATA;
The PU 10 includes a write control line 24 for outputting a write control signal WR for outputting the data signal DATA.

The ROM 30 is connected to an address bus 21, a data bus 22, and a read control line 23. The ROM 30 is provided with addresses of, for example, addresses 000H to 1FFH, and the stored contents once written are retained regardless of the presence or absence of a power supply. A processing program including the fixed data is stored. Meanwhile, RA
M40 is connected to the address bus 21, the data bus 22, the read control line 23, and the write control line 24. For example, addresses of addresses 200H to 2FFH are assigned, and temporary data for processing is stored. Memory. An address decoder 50 is connected to the address bus 21. The address decoder 50 decodes an address signal ADR provided through the address bus 21 and outputs a selection signal for an individual address such as addresses 300H and 301H. For example,
A peripheral function unit (for example, a timer) 60 and a second storage unit (for example, a memory) 61 are connected to the output side of the address decoder 50 of the selection signal at the address 300H. A peripheral function unit (for example, a serial port) 7 is provided on the output side of the address decoder 50 at the address 301H.
0 and a second storage means (for example, a memory) 71 are connected. The data bus 22 and the write control line 24 are commonly connected to the timer 60 and the serial port 70. On the other hand, a read control line 23 is commonly connected to the memories 61 and 71 in addition to the data bus 22 and the write control line 24.

When the timer 60 and the serial port 70 are designated by the address signal ADR via the address decoder 50 and the write control signal WR is given, the timer 60 and the serial port 70 fetch the data signal DATA on the data bus 22 and read the fetched data. The operation specified by the signal DATA is performed. Also, the memories 61 and 71
Is an address signal ADR via an address decoder 50.
And when the write control signal WR is given, the data signal DATA on the data bus 22 is held. When the read control signal RD is given and the read control signal RD is given, the held data is held. It has a function of outputting the signal DATA on the data bus 22. Further, input / output units 80 and 90 capable of input and output of a parallel input / output device or the like are connected to the output side of the address decoder 50 of the selection signal after address 400H. These input / output units 80 and 90 are connected to the data bus 22,
It is connected to the CPU 10 via a read control line 23, a write control line 24, and the like.

Next, the data read / write access operation between the CPU 10 and the timer 60 will be described. First, C
When writing data from the PU 10 to the timer 60, “300H” is output from the CPU 10 to the address signal ADR for the address bus 21. The address signal ADR is decoded by the address decoder 50, and 3
The selection signal corresponding to the address 00H is output and the timer 60
And only the memory 61 are selected. Further, a control command for the timer 60, for example, data “40H” is output from the CPU 10 as the data signal DATA for the data bus 22. Subsequently, the CPU 10 sends a write control signal WR to the write control line 24.
Is output. Thereby, the data bus 22 is stored in the timer 60 and the memory 61 selected by the address signal ADR.
The upper data “40H” is written. That is, the timer 6
In 0, data “40H” is taken in as a control command, and data “40H” is held in the memory 61.
Next, when reading the control data written in the timer 60 by the CPU 10, "300H" is output from the CPU 10 as the address signal ADR to the address bus 21, as in the writing. The address signal ADR is decoded by the address decoder 50, and a selection signal corresponding to the address 300H is output.
Only is selected.

Subsequently, the CPU 10 outputs a read control signal RD to the read control line 23. As a result, the data “40H” held in the memory 61 is output from the memory 61 selected by the address signal ADR onto the data bus 22. On the other hand, since the timer 60 does not have a function of outputting data to the data bus 22, the data output on the data bus 22 is only the data “40H” from the memory 61. C
The PU 10 can read the control command output to the timer 60 by inputting the data “40H” on the data bus 22. As described above, in the microcomputer of this embodiment, the readable / writable memory 61 to which the same address as that of the output-only peripheral device such as the timer 60 is connected is connected to the common bus 20. Thus, there is an advantage that data such as a control command output to the timer 60 can be read out by designating the address of the timer 60.

Second Embodiment FIG. 3 is a block diagram of a microcomputer according to a second embodiment of the present invention, in which components common to those in FIG. 2 are denoted by common reference numerals. In this microcomputer, instead of the RAM 40 in the first embodiment of FIG. 1, a storage area corresponding to addresses 200H to 2FFH as a first storage means and a storage area corresponding to a second storage means as 300H
RA having a storage area corresponding to addresses 3FFH
M40A is provided. Accordingly, the timer 6 in FIG.
0 and the memories 61 and 62 corresponding to the serial port 70
Has been deleted. Other configurations are the same as those in FIG.
With such a configuration, for example, the CPU 10 to 3
The data “40” written in the timer 60 at the address 00H
H "is also written simultaneously to the address 300H of the RAM 40A. On the other hand, when the CPU 10 reads the data of the timer 60, no data is output from the timer 60,
The data “4” written at the address 300H of the RAM 40A
0H "is output to the data bus 22. This has the same advantages as the first embodiment. Further, since the memories can be integrated in the RAM 40A without being distributed, the configuration of the microcomputer is simplified. There is an advantage that you can.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (c). (A) The addresses of the ROM 30, the RAM 40, the timer 60, and the like are not limited to the addresses exemplified in the above embodiment, and any address can be set according to the scale and application of the microcomputer. (B) The memory 61 or the RAM 40A provided with the same address as the peripheral device such as the timer 60 is not limited to the RAM. For example, a so-called flash memory, which is electrically erasable and once written data is retained as it is even without a power supply, may be used. Thus, there is an advantage that data can be retained even during a power failure. (C) In FIGS. 1 and 3, the ROM 30 and the RAM 4
Although the same address system is used for the address of the memory of 0, 40A and the address of the peripheral device such as the timer 60, the memory and the peripheral device may have different address systems.

[0014]

As described in detail above, according to the present invention, since the second storage means provided with the same address as that of the peripheral function unit is provided, the second storage means is provided from the CPU to the peripheral function unit. The output data obtained can be held in the second storage means. For this reason, it becomes possible to read output data such as a control command output to the output-only peripheral function unit from the address of the peripheral function unit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram illustrating an example of a conventional microcomputer.

FIG. 3 is a configuration diagram of a microcomputer according to a second embodiment of the present invention.

[Explanation of symbols]

 10 CPU 20 common bus 21 address bus 22 data bus 23 read control line 24 write control line 30 ROM 40, 40A RAM 50 address decoder 60 timer 61, 71 memory 70 serial port 80, 90 input / output unit ADR address signal RD read control signal WR write control signal

Claims (1)

[Claims] The digital processing is performed based on a processing program including a data processing instruction and an external input / output instruction, and output data is output by outputting a write control signal together with an address signal. A central processing unit for inputting input data by outputting a read control signal; the output data output from the central processing unit, the input data input by the central processing unit, the processing program, and the digital processing And a plurality of storage areas for storing data for the digital processing and the processing program, and a series of first addresses for specifying the storage areas are provided. First storage means, and a second address different from the first address is assigned. A peripheral function unit that captures the output data on the data bus when specified by the address signal and the write control signal is supplied; and a second address identical to the peripheral function unit is provided. Holding the output data on the data bus when specified by the address signal and the write control signal is applied, and holding the output data when the read control signal is specified and specified by the address signal And a second storage means for outputting the output data to the data bus.