JPS6385954A - Memory control system - Google Patents

Abstract

PURPOSE:To prevent the constitution of hardware from being complicated, by transferring a bit of status/command information between a CPU module and a memory module through a memory bus without making the constitution into a large size. CONSTITUTION:An address register 8 is a register which inputs an address supplied from a CPU5 through the memory bus 3, and selects a prescribed memory module out of plural memory modules based on the address. On a memory array 10, the readout of a bit of information stored and held, or the write of the bit of information, is performed by an instruction from a control circuit 9. A buffer circuit 11 is connected between the memory array 10 and the memory bus 3, and performs the transfer of the bit of information between the memory array 10 and the memory bus 3 in both ways, according to an enable signal supplied from the control circuit 9. A status register 12 supplies the bit of information to the memory bus 3, and a command register 13 stores and holds a bit of command information supplied through the memory bus 3.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention provides a system in which a CPU and a main storage device are each constructed from separate modules, and information is input via a dedicated bus. It relates to a memory control method for outputting.

(Prior Art) In recent microcomputers, the central processing unit (CPU) and the main memory (memory) in which various information is stored are configured as separate modules, and each is connected to a dedicated bus. There are things that are connected to form a system.

Figure 2 shows a separate module for the CPU and main memory as described above.
FIG. This system includes a CPU module 1 equipped with a CPU, a plurality of memory modules 2 composed of memories storing instruction codes, oborands, etc., and a memory bus 3 connecting the CPU module 1 and the memory module 2. , and a common bus 4. In such a configuration, the instruction code or operand information stored and held in the memory module 2 is transferred to the CPU module 1 via the memory bus 3.

In such a system, in order to input the information stored and held in the memory module 2 to the CPU module 1, there is a method of allocating a part of the memory address space on the memory module 2 to the status/command register. be. In addition, a dedicated bus (not shown) for transferring information stored and held in the memory module 2 is connected to a memory bus 3.
memory module 2 via this dedicated bus.
There is a method of transferring information stored and held between. Furthermore, there is a method of using the common bus 4 and inputting information stored and held in the memory module 2 via this common bus.

(Problems to be Solved by the Invention) As explained above, in the above-described configuration, in order to input the information stored and held in the memory module 2 to the CPU module 1, the memory address on the memory module 2 must be One method is to allocate part of the space to status/command registers. However, this method has a problem in that if real memory addresses exist in the entire memory address space of the memory module 2, the above method cannot be used.

Further, in the method of providing a dedicated bus on the memory bus 3 or using the common bus 4, there is a problem that the hardware configuration becomes complicated.

Therefore, the present invention has been made in view of the above, and its purpose is to transmit status/command information to a CPU via a memory bus without increasing the size of the configuration.
An object of the present invention is to provide a memory control method capable of transferring data between a U module and a memory module.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a CPU module and a memory module are provided, and information input and output between the CPU module and the memory module is conducted via a memory bus. In the memory control method carried out, the present invention provides
The PU module shares the status/status with the memory module.
A register in which information indicating that command information is to be input/output is stored, and an output of this register and a signal indicating that the CPU module performs an operand fetch operation are input and the CPU module is fetching an operand. A logic gate circuit that outputs status/command information to the memory module, a status register that outputs status information, a command register that stores and holds command information, and a base for status/command information from the logic gate circuit. and a control circuit that outputs status information to the CPU module via the memory bus and stores and holds command information given from the CPU module via the memory bus in the command register.

(Operation) In the memory control method of the present invention, when the CPU module performs an operand fetch operation, the CPU
If information indicating that the module performs status/command information input/output operations to the memory module is set in the register, the CPU module instructs the memory module to input/output status/command information, and the status information is The status register of the selected memory module is given to the CPU module via the memory bus, and command information given from the CPU module via the memory bus is now stored in the command register of the selected memory module. ing.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

1(A) and FIG. 1(B) are block diagrams showing the configuration of a memory control system according to an embodiment of the present invention.The memory control system of this embodiment is based on the CPU module shown in FIG. 1 and a plurality of memory modules 2.

FIG. 1(A) is a block diagram showing the configuration of the CPU module 1 side in the memory control method of this embodiment.

In the figure, the configuration on the CPU module 1 side is
5, a register 6, and a gate circuit 7. C.P.L.
J5 uses CP when fetching operands.
U5 supplies the gate circuit 7 with an operand fetch signal indicating that the operand is to be fetched.

When the CPU module 1 requests the memory module 2 to input/output status/command information, the register 6 stores and holds command information indicating the request.

The gate circuit 7 receives an operand fetch signal given from the CPU 5, command information given from the register 6,
is input, performs AND logic processing, and outputs a command/status signal for inputting/outputting command/status information.

FIG. 1(B) is a block diagram showing the configuration of the memory module 2 in the memory control system of this embodiment.

In the figure, the configuration on the memory module 2 side includes an address decoder 8, a control circuit 9, a memory array 101, a buffer circuit 11, a status register 12, and a command register 13.

The address decoder 8 is connected to the CPU 5 via the memory bus 3.
A predetermined memory module is selected from among a plurality of memory modules based on this address. The memory array 10 is
According to instructions from control circuit 9, stored and held information is read out or information is loaded into memory array 10.

The buffer circuit 11 connects the memory array 10 and the memory bus 3.
According to an enable signal given from control circuit 9, information is transferred between memory array 10 and memory bus 3 in both directions.

The status register 12 holds status information, and provides the held status information to the memory bus 3 in accordance with an enable signal applied from the control circuit 9. The command register 13 holds command information from the CPU 5, and stores and holds command information given via the memory bus 3 in accordance with an enable signal given from the control circuit 9.

When the memory module 2 is in normal operation, the control circuit 9 inputs a request signal given via the memory bus 3 and supplies an enable signal to the buffer circuit 11 to activate the buffer circuit 11. , which instructs the memory array 10 to read information from or write information to the memory array 10. Furthermore, when a command/status signal is input via the memory bus 3, the control circuit 9 provides an enable signal to the status register 12 and command register 13.

In such h1 configuration, when the CPtJ module 1 attempts to input/output status and /command information to the memory module 2, a command is given from the CPU 5 to the register 6, and the command information is held. In such a state, when the CPIJ 5 attempts to fetch an operand, an operand fetch signal is applied to the gate circuit 7. As a result, the command/status instruction is supplied from the gate circuit 7 to the memory module 2 via the memory bus 3.

When the control circuit 9 of the memory module 2 receives the above-mentioned command/status command transferred together with the operand fetch command and the memory address, the control circuit 9 controls the buffer 7 circuit 11.
The output of the enable signal to the status register 12 and the command register 13 is stopped, and the enable signal is given to the status register 12 and the command register 13. Upon receiving this enable signal, the status register 12 and command register 13 transfer the status information of the status register 12 to the CPL via the memory bus 3.
Supply to I5. Also, the command register 13 is CPL
Holds command information given from J5 via memory bus 3.

Note that the command/status signal is sent from the gate circuit 7 on the CPtj module 1 side to the memory module 21Qll only when the CPU 5 performs the 7-etch of the operand.
i, II of I11 is given to the circuit 9, and is not given to the control circuit 9 when the CPU 5 fetches an instruction. Therefore, it is possible to store a program that performs command/status signal generation operations in the memory array 10 on the memory module 2 side, and the CPU module 1
There is no need to store it in 1O1 memory (RO to 1, etc.).

[Effects of the Invention] As explained above, according to the present invention, when the CPLI module performs the 7-etch of the operand based on the information indicating that the input/output operation of status/command information set in the register is to be performed. In order to instruct the memory module to input/output status/command information, we changed the configuration to a large one. ! without becoming cluttered,
Status/command information is sent to the CPU via the memory bus.
Transfers can be made between the module and the memory module.

[Brief explanation of the drawing]

FIG. 1(A) is a diagram illustrating conjunctivity on the CPU module side in a memory control method according to an embodiment of the present invention, and FIG. 1(B) is a diagram showing a conjunctive state on the memory module side in a memory control method according to an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of the memory i1. FIG. 2 is a diagram showing an example of a configuration of an IJ control method. (Explanation of symbols representing main parts of the diagram) 1...CPU
Module 2...Memory module 3...Memory bus 6...Register 7...Gate circuit 9...υ control circuit 12...Status register 13...Command register

Claims (1)

[Claims] comprising a CPU module and a memory module;
In a memory control method that inputs and outputs information between a PU module and the plurality of memory modules via a memory bus, information indicating that the CPU module inputs and outputs status/command information to and from the memory module is stored. and a logic that receives the output of this register and a signal indicating that the PUC module performs an operand fetch operation, and outputs status/command information to the memory module only when the CPU module performs an operand fetch operation. a gate circuit, a status register that outputs the status information, a command register that stores and holds the command information, and a gate circuit that transmits status information to the CPU module via the memory bus based on the status/command information from the logic gate circuit. and the above-mentioned C
A memory control system comprising: a control circuit that causes the command register to store and hold command information given from a PU module via the memory bus.