JPH1154674A - Hybrid integrated circuit device and its manufacture - Google Patents
Hybrid integrated circuit device and its manufactureInfo
- Publication number
- JPH1154674A JPH1154674A JP9212296A JP21229697A JPH1154674A JP H1154674 A JPH1154674 A JP H1154674A JP 9212296 A JP9212296 A JP 9212296A JP 21229697 A JP21229697 A JP 21229697A JP H1154674 A JPH1154674 A JP H1154674A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- hybrid integrated
- integrated circuit
- heat sink
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、混成集積回路装置
及びその製造方法に関し、特に、放熱構造を有する混成
集積回路装置及びその製造方法に関するものである。The present invention relates to a hybrid integrated circuit device and a method of manufacturing the same, and more particularly to a hybrid integrated circuit device having a heat dissipation structure and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、導体材料や抵抗体材料等により回
路パターンが形成された回路基板上に半導体素子や各種
電子部品が搭載された混成集積回路装置は、装置の小型
化、軽量化、高速化を目的として通信機器をはじめ多く
の分野で用いられている。装置の小型化、軽量化、高速
化が進むにつれて、装置からの発熱をいかにして放熱す
るかが問題となるが、混成集積回路装置においては、放
熱に対しては特に対策は取られていないのが通例であっ
た。2. Description of the Related Art Conventionally, a hybrid integrated circuit device in which semiconductor elements and various electronic components are mounted on a circuit board on which a circuit pattern is formed by a conductor material, a resistor material, and the like has been reduced in size, weight, and speed. It is used in many fields including communication equipment for the purpose of realization. As devices become smaller, lighter, and faster, how to radiate heat from the devices becomes a problem. However, no measures have been taken against heat radiation in hybrid integrated circuit devices. Was customary.
【０００３】そこで、近年、半導体素子等を実装した回
路基板の部品実装面に、封止樹脂あるいは接着樹脂を用
いて放熱板を取り付ける構造のものが提案されている
（例えば、特開昭５９−５１５８８号公報等を参照のこ
と）。Therefore, in recent years, a structure has been proposed in which a heat radiating plate is attached to a component mounting surface of a circuit board on which a semiconductor element or the like is mounted using a sealing resin or an adhesive resin (for example, Japanese Patent Laid-Open No. See, for example, JP-A-51588).
【０００４】図６は従来の混成集積回路装置を示す断面
図であり、図において、１は回路パターンが形成された
回路基板、２は回路基板１上に搭載された半導体素子
（回路素子）、３は回路基板１と半導体素子２とを電気
的に接続するボンディングワイヤ、４は半導体素子２を
封止するプリコート樹脂、５はプリコート樹脂４の周囲
に供給された接着樹脂、６は接着樹脂５により回路基板
１の部品実装面上に固定された放熱板である。FIG. 6 is a cross-sectional view showing a conventional hybrid integrated circuit device. In the figure, 1 is a circuit board on which a circuit pattern is formed, 2 is a semiconductor element (circuit element) mounted on the circuit board 1, 3 is a bonding wire for electrically connecting the circuit board 1 and the semiconductor element 2, 4 is a precoat resin for sealing the semiconductor element 2, 5 is an adhesive resin supplied around the precoat resin 4, 6 is an adhesive resin 5 Is a heat radiating plate fixed on the component mounting surface of the circuit board 1.
【０００５】この混成集積回路装置は、回路基板１と半
導体素子２とをボンディングワイヤ３で接続した後、プ
リコート樹脂４により半導体素子２を封止し、接着樹脂
５により回路基板１の部品実装面上に放熱板６を取り付
けている。この混成集積回路装置では、熱源となる半導
体素子２と放熱板６との間にプリコート樹脂４や接着樹
脂５が介在しているので、放熱効果は期待した程大きく
はない。また、放熱板６の形状については特に考慮され
ておらず、単に板状のものが用いられており、半導体素
子２との対向面も単なる平坦面である。In this hybrid integrated circuit device, after connecting a circuit board 1 and a semiconductor element 2 with bonding wires 3, the semiconductor element 2 is sealed with a precoat resin 4, and a component mounting surface of the circuit board 1 is bonded with an adhesive resin 5. The heat sink 6 is mounted on the top. In this hybrid integrated circuit device, since the precoat resin 4 and the adhesive resin 5 are interposed between the semiconductor element 2 serving as a heat source and the heat sink 6, the heat dissipation effect is not as large as expected. Further, the shape of the heat radiating plate 6 is not particularly considered, and a plate-like one is used, and the surface facing the semiconductor element 2 is also a mere flat surface.
【０００６】[0006]
【発明が解決しようとする課題】第１の問題点は、放熱
板６の接着面が平坦面であるため、該放熱板６と回路基
板１の部品実装面との間隔は、回路基板１上に実装され
る半導体素子２や電子部品のうち最も高い部品に合わせ
て設定することとなるので、放熱板６と回路基板１の部
品実装面との間を埋めるためにかなりの量のプリコート
樹脂４や接着樹脂５が必要となり、同時に放熱効果も低
下するという点である。The first problem is that since the adhesive surface of the heat sink 6 is a flat surface, the distance between the heat sink 6 and the component mounting surface of the circuit board 1 is limited on the circuit board 1. Since it is set according to the highest component among the semiconductor elements 2 and the electronic components mounted on the circuit board 1, a considerable amount of the precoat resin 4 is required to fill the space between the heat sink 6 and the component mounting surface of the circuit board 1. And the adhesive resin 5 is required, and at the same time, the heat radiation effect is reduced.
【０００７】第２の問題点は、放熱効果を高めるために
は、放熱板６と半導体素子２との間を詰める必要があ
り、そのためには放熱板６でプリコート樹脂４や接着樹
脂５を押さえる工程が必要となるが、放熱板６が平坦で
あるため、接着樹脂５により回路基板１上に放熱板６を
取り付ける際に、僅かに傾いても接着樹脂５の広がりに
片寄りが生じ、接着樹脂５の広がり方が均一になり難い
点である。The second problem is that it is necessary to close the gap between the heat radiating plate 6 and the semiconductor element 2 in order to enhance the heat radiating effect. To this end, the heat radiating plate 6 holds down the precoat resin 4 and the adhesive resin 5. Although a process is required, since the heat radiating plate 6 is flat, when the heat radiating plate 6 is mounted on the circuit board 1 with the adhesive resin 5, even if slightly inclined, the spread of the adhesive resin 5 is offset, and the bonding is performed. The point is that it is difficult for the resin 5 to spread uniformly.
【０００８】本発明は上記の事情に鑑みてなされたもの
であって、放熱特性が優れるとともに厚みが薄くなり、
小型化、軽量化に対応することができ、また、安定した
製造条件が得られ、封止樹脂の使用量を削減することが
可能になり、コストダウンを図ることのできる混成集積
回路装置及びその製造方法を提供することを目的とす
る。The present invention has been made in view of the above circumstances, and has excellent heat dissipation characteristics and a reduced thickness.
A hybrid integrated circuit device that can cope with miniaturization and weight reduction, can obtain stable manufacturing conditions, can reduce the amount of sealing resin used, can reduce the cost, and the hybrid integrated circuit device. It is intended to provide a manufacturing method.
【０００９】[0009]
【課題を解決するための手段】上記課題を解決するため
に、本発明は次の様な混成集積回路装置及びその製造方
法を採用した。すなわち、請求項１記載の混成集積回路
装置は、回路素子を搭載した回路基板と、該回路素子を
含む回路基板の表面を覆い封止する樹脂と、少なくとも
該樹脂の表面の一部に固定された放熱板とを備え、該放
熱板の前記回路素子と対向する面にキャビティ部を形成
したものである。In order to solve the above-mentioned problems, the present invention employs the following hybrid integrated circuit device and a method of manufacturing the same. In other words, the hybrid integrated circuit device according to claim 1 is a circuit board on which a circuit element is mounted, a resin that covers and seals a surface of the circuit board including the circuit element, and is fixed to at least a part of the surface of the resin. And a cavity portion is formed on a surface of the heat dissipation plate facing the circuit element.
【００１０】請求項２記載の混成集積回路装置は、前記
キャビティ部を、複数の前記回路素子に跨るように形成
したものである。According to a second aspect of the present invention, in the hybrid integrated circuit device, the cavity is formed so as to extend over a plurality of the circuit elements.
【００１１】請求項３記載の混成集積回路装置は、前記
放熱板の前記回路素子と対向する面に、溝を１つ以上形
成したものである。According to a third aspect of the present invention, in the hybrid integrated circuit device, at least one groove is formed on a surface of the heat sink facing the circuit element.
【００１２】請求項４記載の混成集積回路装置は、前記
溝を、前記放熱板の１つの辺に平行になるように形成し
たものである。According to a fourth aspect of the present invention, in the hybrid integrated circuit device, the groove is formed so as to be parallel to one side of the heat sink.
【００１３】請求項５記載の混成集積回路装置は、前記
放熱板の前記回路素子と対向する面に、突条を１つ以上
形成したものである。According to a fifth aspect of the present invention, in the hybrid integrated circuit device, at least one ridge is formed on a surface of the heat sink facing the circuit element.
【００１４】請求項６記載の混成集積回路装置は、前記
突条を、前記放熱板の１つの辺に平行になるように形成
したものである。According to a sixth aspect of the present invention, in the hybrid integrated circuit device, the ridge is formed so as to be parallel to one side of the heat sink.
【００１５】請求項７記載の混成集積回路装置の製造方
法は、回路素子を搭載した回路基板上に、樹脂を介して
放熱板を固定する方法であり、前記放熱板の所定位置に
樹脂を供給する樹脂供給工程と、前記放熱板に供給され
た樹脂が前記回路基板に搭載された回路素子と対向する
ように位置合わせを行い、該放熱板を前記樹脂を介して
前記回路基板に圧接する圧接工程とを備えた方法であ
る。According to a seventh aspect of the present invention, there is provided a method of manufacturing a hybrid integrated circuit device, comprising the steps of fixing a heat sink through a resin on a circuit board on which circuit elements are mounted, and supplying the resin to a predetermined position of the heat sink. A resin supply step to perform the positioning, so that the resin supplied to the heat radiating plate faces the circuit element mounted on the circuit board, and presses the heat radiating plate to the circuit board via the resin. And a process.
【００１６】請求項８記載の混成集積回路装置の製造方
法は、前記樹脂供給工程を、前記放熱板に形成されたキ
ャビティ部に樹脂を供給することとした方法である。According to a eighth aspect of the present invention, in the method of manufacturing a hybrid integrated circuit device, the resin supply step includes supplying a resin to a cavity formed in the heat sink.
【００１７】本発明の請求項１または２記載の混成集積
回路装置では、放熱板の前記回路素子と対向する面にキ
ャビティ部を形成したことにより、前記回路素子の周囲
の最小の領域を封止樹脂で封止することが可能になり、
前記放熱板と該回路素子が搭載される回路基板との間隔
を小さくすることが可能になり、搭載される回路素子か
らの熱放散が速やかに行われ、放熱特性が向上する。In the hybrid integrated circuit device according to the first or second aspect of the present invention, a minimum area around the circuit element is sealed by forming a cavity on a surface of the heat sink facing the circuit element. It becomes possible to seal with resin,
The distance between the heat radiating plate and the circuit board on which the circuit element is mounted can be reduced, and heat can be quickly dissipated from the mounted circuit element, thereby improving heat radiation characteristics.
【００１８】請求項３ないし６のいずれか１項記載の混
成集積回路装置では、前記放熱板の前記回路素子と対向
する面に、溝または突条のいずれか１種を１つ以上形成
したことにより、封止樹脂は前記溝または突条のいずれ
かに沿って流れることになり、封止樹脂のはみ出しが抑
えられるとともに封止・接続を行いたい領域に該封止樹
脂を広げることが可能になり、該封止樹脂の厚みの均一
性が高まり、放熱特性のばらつきが小さくなる。In the hybrid integrated circuit device according to any one of claims 3 to 6, at least one of a groove and a ridge is formed on a surface of the heat sink facing the circuit element. Thereby, the sealing resin flows along either the groove or the ridge, and the protrusion of the sealing resin is suppressed, and the sealing resin can be spread to a region where sealing and connection are to be performed. As a result, the uniformity of the thickness of the sealing resin is increased, and the dispersion of the heat radiation characteristics is reduced.
【００１９】本発明の混成集積回路装置の製造方法で
は、前記放熱板の所定位置に樹脂を供給する樹脂供給工
程と、前記放熱板に供給された樹脂が前記回路基板に搭
載された回路素子と対向するように位置合わせを行い、
該放熱板を前記樹脂を介して前記回路基板に圧接する圧
接工程とを備えたことにより、前記放熱板と回路基板と
の間隔が小さくなり、使用される封止樹脂の量が削減さ
れる。また、前記放熱板と回路基板との間隔が小さくな
るので、搭載される回路素子からの熱放散が速やかにな
り、優れた放熱特性を有する混成集積回路装置を得るこ
とが可能になる。In the method of manufacturing a hybrid integrated circuit device according to the present invention, a resin supply step of supplying a resin to a predetermined position of the heat sink, a circuit element having the resin supplied to the heat sink mounted on the circuit board, Align so that they face each other,
A pressure contact step of pressing the heat radiating plate to the circuit board via the resin is provided, so that a space between the heat radiating plate and the circuit board is reduced, and the amount of sealing resin used is reduced. In addition, since the distance between the heat radiating plate and the circuit board is reduced, heat dissipation from the mounted circuit element is accelerated, and a hybrid integrated circuit device having excellent heat radiation characteristics can be obtained.
【００２０】[0020]
【発明の実施の形態】以下、本発明の混成集積回路装置
及びその製造方法の各実施形態について図面に基づき説
明する。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a hybrid integrated circuit device according to a first embodiment of the present invention;
【００２１】（第１の実施形態）図１は本発明の第１の
実施形態の混成集積回路装置を示す断面図、図２は同分
解斜視図であり、図において、１１は放熱板、１２は該
放熱板１１と半導体素子２が搭載される回路基板１との
間を封止し接着固定する封止樹脂、１３は半導体素子２
を回路基板１上に電気的に接続するバンプ電極、１４は
アンダーフィル樹脂である。(First Embodiment) FIG. 1 is a sectional view showing a hybrid integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is an exploded perspective view of the hybrid integrated circuit device. Is a sealing resin for sealing and bonding between the heat sink 11 and the circuit board 1 on which the semiconductor element 2 is mounted.
Are electrically connected to the circuit board 1, and 14 is an underfill resin.
【００２２】回路基板１は、ガラスやエポキシ樹脂を用
いたプリント配線基板、アルミナ（Ａｌ2Ｏ3）等のセラ
ミック基板、ポリイミドテープを用いたフレキシブル基
板等が好適であり、該回路基板１の中央部に長手方向に
沿って複数の半導体素子２（この場合、４個）が搭載さ
れている。これらの半導体素子２のバンプ電極１３によ
る実装高さは約Ｏ．４〜０．６ｍｍ程度である。ここで
は、半導体素子２は単数でも複数でもよく、また、チッ
プ抵抗やチップコンデンサ等の受動部品を含んでももち
ろんかまわない。また、回路パターンとなる導体構成や
材質等は特に問わない。The circuit board 1 is preferably a printed wiring board using glass or epoxy resin, a ceramic substrate such as alumina (Al 2 O 3 ), a flexible substrate using a polyimide tape, or the like. A plurality of semiconductor elements 2 (in this case, four) are mounted on the portion along the longitudinal direction. The mounting height of these semiconductor elements 2 by the bump electrodes 13 is about O.D. It is about 4 to 0.6 mm. Here, the semiconductor element 2 may be singular or plural, and may include passive components such as a chip resistor and a chip capacitor. In addition, there is no particular limitation on the conductor configuration and material used as the circuit pattern.
【００２３】放熱板１１は、長尺の板状のもので、前記
回路基板１の複数の半導体素子２に跨るように、これら
半導体素子２に対向する下面中央部に長手方向に沿って
幅広のキャビティ２１が形成されており、キャビティ２
１の両側には、樹脂の流れを案内する断面半円状の溝２
２が２つずつ互いに平行に形成されている。この放熱板
１１は、アルミニウム、あるいはマグネシウムやシリコ
ン等を含むアルミニウム合金を用いるが、銅、ニッケ
ル、鉄あるいはこれらの合金でもよく、また、窒化ホウ
素や珪化炭素のようなセラミックスを用いてもよい。The heat radiating plate 11 is a long plate-like member. The heat radiating plate 11 has a wide width along the longitudinal direction at the center of the lower surface facing the semiconductor elements 2 so as to straddle the plurality of semiconductor elements 2 of the circuit board 1. A cavity 21 is formed, and a cavity 2 is formed.
A groove 2 having a semicircular cross section for guiding resin flow
2 are formed two by two in parallel with each other. The heat radiating plate 11 uses aluminum or an aluminum alloy containing magnesium, silicon, or the like, but may use copper, nickel, iron, or an alloy thereof, or may use a ceramic such as boron nitride or carbon silicide.
【００２４】キャビティ２１の深さは、半導体素子２の
実装高さに合わせるか、あるいは半導体素子２表面と放
熱板１１との接合を確実にするために、０．１〜０．３
ｍｍ程度浅く形成してもよい。溝２２は、深さが０．１
〜０．３ｍｍ程度でも効果を呈するが、キャビティ２１
の深さに合わせることもできる。また、溝２２の幅は基
本的には任意であるが、０．１〜２．０ｍｍ幅で十分効
果がある。The depth of the cavity 21 is set to 0.1 to 0.3 in order to match the mounting height of the semiconductor element 2 or to secure the bonding between the surface of the semiconductor element 2 and the heat sink 11.
It may be formed as shallow as about mm. The groove 22 has a depth of 0.1
Although an effect is exhibited even when the cavity 21
You can also adjust to the depth of the. The width of the groove 22 is basically arbitrary, but a width of 0.1 to 2.0 mm is sufficiently effective.
【００２５】キャビティ２１と溝２２の形状は、半円状
等のように角のない形状にした方が、封止樹脂１２の回
り込みが良好になり、気泡の巻き込み等の不具合が発生
し難い。このように放熱板１１を加工しておくことは、
長手方向の側面側への封止樹脂１２のはみ出しを押さえ
る意味で都合がよいと同時に、放熱板１１を加工する上
で絞り出し加工が行い易く、放熱板１１の加工を廉価に
行なう上でも都合がよくなる。When the cavities 21 and the grooves 22 are formed in a shape having no corners, such as a semicircle, the sealing resin 12 wraps around better, and problems such as entrapment of air bubbles are less likely to occur. Processing the heat sink 11 in this way is
This is convenient in terms of suppressing the protrusion of the sealing resin 12 to the side surface in the longitudinal direction, and at the same time, it is easy to perform the squeezing process in processing the heat radiating plate 11, which is also convenient for performing the processing of the heat radiating plate 11 at low cost. Get better.
【００２６】封止樹脂１２は、エポキシ系樹脂に特性調
整のためのフィラー材を混入したものを用いるが、シリ
コーン系樹脂、フェノール系樹脂等を用いてもよい。封
止樹脂１２の粘度は、２００〜２０００Ｐｏｉｓｅのも
のが好適である。As the sealing resin 12, an epoxy resin mixed with a filler material for adjusting characteristics is used, but a silicone resin, a phenol resin or the like may be used. The viscosity of the sealing resin 12 is preferably 200 to 2000 Poise.
【００２７】次に、この混成集積回路装置の製造方法に
ついて図３に基づき説明する。まず、同図（ａ）に示す
ように、放熱板１１のキャビティ２１の周囲に所定量の
封止樹脂１２を供給する。次いで、同図（ｂ）に示す回
路基板１に搭載された半導体素子２に、この放熱板１１
の封止樹脂１２を対向させて位置合わせを行い、次い
で、同図（ｃ）に示すように、放熱板１１を封止樹脂１
２を介して回路基板１に所定の圧力Ｐで圧接する。Next, a method of manufacturing the hybrid integrated circuit device will be described with reference to FIG. First, as shown in FIG. 1A, a predetermined amount of the sealing resin 12 is supplied around the cavity 21 of the heat sink 11. Next, the heat sink 11 is mounted on the semiconductor element 2 mounted on the circuit board 1 shown in FIG.
Then, the positioning is performed with the sealing resin 12 facing the sealing resin 12, and then, as shown in FIG.
2 and is pressed against the circuit board 1 at a predetermined pressure P.
【００２８】この時、封止樹脂１２はキャビティ２１の
周囲から外方へ押し広げられるが、溝２２により放熱板
１１の長手方向に沿って広がるため、長手方向の側面か
らの封止樹脂１２のはみ出しが抑えられ、封止・接続を
行いたい領域に該封止樹脂１２を広げることができる。
封止樹脂１２としてエポキシ系樹脂を用いた場合、この
圧接した状態で、１００〜１５０℃で１〜３時間、キュ
アーを行なう。At this time, the sealing resin 12 is pushed outward from the periphery of the cavity 21, but spreads along the longitudinal direction of the heat radiating plate 11 by the groove 22. Extrusion is suppressed, and the sealing resin 12 can be spread over a region where sealing and connection are desired.
When an epoxy resin is used as the sealing resin 12, curing is performed at 100 to 150 ° C. for 1 to 3 hours in this pressed state.
【００２９】本実施形態の混成集積回路装置によれば、
半導体素子２を放熱板１１のキャビティ２１中に入り込
ませて固定する構造としたので、放熱板１１と半導体素
子２及び回路基板１との間隔を小さくすることができ、
少量の封止樹脂１２で放熱板１１を回路基板１に固定す
ることができ、放熱の効果を高めることができる。According to the hybrid integrated circuit device of the present embodiment,
Since the semiconductor element 2 is inserted into the cavity 21 of the heat sink 11 and fixed, the distance between the heat sink 11 and the semiconductor element 2 and the circuit board 1 can be reduced.
The heat radiating plate 11 can be fixed to the circuit board 1 with a small amount of the sealing resin 12, and the heat radiation effect can be enhanced.
【００３０】また、放熱板１１に形成した溝２２によ
り、封止樹脂１２の広がり方向を案内するとともに、は
み出しの生じる方向に対しては堰となってはみ出しを防
止するので、封止樹脂１２の広がりをコントロールする
ことができる。特に、列状に実装された半導体素子２に
放熱板１１を取り付ける際の封止樹脂１２のはみ出し不
具合を低減することができる。The groove 22 formed in the heat radiating plate 11 guides the spreading direction of the sealing resin 12 and acts as a weir in the direction in which the sealing resin 12 protrudes. You can control the spread. In particular, it is possible to reduce the problem that the sealing resin 12 protrudes when the heat radiating plate 11 is attached to the semiconductor elements 2 mounted in rows.
【００３１】本実施形態の混成集積回路装置の製造方法
によれば、放熱板１１を封止樹脂１２を介して回路基板
１に圧接するので、放熱板１１と半導体素子２との間隔
を小さくすることができ、良好な放熱構造の混成集積回
路装置を作製することができる。また、放熱板１１と回
路基板１との間隔も小さくすることができ、使用する封
止樹脂１２の量を削減することができる。According to the method of manufacturing a hybrid integrated circuit device of the present embodiment, the heat sink 11 is pressed into contact with the circuit board 1 via the sealing resin 12, so that the distance between the heat sink 11 and the semiconductor element 2 is reduced. Thus, a hybrid integrated circuit device having a favorable heat dissipation structure can be manufactured. Further, the distance between the heat sink 11 and the circuit board 1 can be reduced, and the amount of the sealing resin 12 used can be reduced.
【００３２】また、回路基板１と放熱板１１との間に封
止樹脂１２を充填し、キュアーする場合、封止樹脂１２
の硬化収縮によってモジュール全体に反りや撓みが発生
し易いが、放熱板１１にキャビティ２１及び複数の溝２
２を形成しているので、長手方向の反りや撓みが生じ難
くなり、かつ使用する封止樹脂１２の量も少なくするこ
とができるため、反りや撓みを抑制する効果は非常に大
きなものとなる。When the sealing resin 12 is filled between the circuit board 1 and the radiator plate 11 and cured, the sealing resin 12 is used.
Although the module is likely to be warped or bent due to the curing shrinkage of the heat sink, the heat sink 11 has a cavity 21 and a plurality of grooves 2.
2, the warpage and bending in the longitudinal direction are less likely to occur, and the amount of the sealing resin 12 to be used can be reduced. Therefore, the effect of suppressing the warping and bending is very large. .
【００３３】なお、キャビティ２１の形状や寸法、溝２
２の形状や寸法及び本数は、使用する封止樹脂１２の粘
度によって適宜調整してもよい。また、本実施形態で
は、モジュールの取り付けを考慮して放熱板１１の上面
を平坦な構造としたが、放熱効果を高めるために放熱フ
ィンを形成した構造としてもよい。The shape and size of the cavity 21 and the groove 2
The shape, size and number of 2 may be appropriately adjusted according to the viscosity of the sealing resin 12 to be used. Further, in the present embodiment, the upper surface of the heat radiating plate 11 has a flat structure in consideration of the mounting of the module, but may have a structure in which a heat radiating fin is formed to enhance a heat radiating effect.
【００３４】（第２の実施形態）図４は本発明の第２の
実施形態の混成集積回路装置を示す断面図であり、本実
施形態の放熱板３１が上述した第１の実施形態の放熱板
１１と異なる点は、放熱板３１の前記回路基板１の半導
体素子２を挟む両側の位置に、堰となるような突起部
（突条）３２を該放熱板３１の長手方向に沿ってそれぞ
れ複数本（ここでは３本）ずつ互いに平行に形成した点
である。(Second Embodiment) FIG. 4 is a sectional view showing a hybrid integrated circuit device according to a second embodiment of the present invention. The difference from the plate 11 is that the projections (protrusions) 32 serving as weirs are provided along the longitudinal direction of the heat sink 31 at the positions on both sides of the heat sink 31 sandwiching the semiconductor element 2 of the circuit board 1. The point is that a plurality (three in this case) is formed in parallel with each other.
【００３５】この混成集積回路装置においても、放熱板
３１の取り付け高さを調整し、封止樹脂１２の流れをコ
ントロールすることができ、第１の実施形態の放熱板１
１と同様の効果を得ることができる。Also in this hybrid integrated circuit device, the flow of the sealing resin 12 can be controlled by adjusting the mounting height of the radiator plate 31, and the radiator plate 1 of the first embodiment can be controlled.
The same effect as that of No. 1 can be obtained.
【００３６】（第３の実施形態）図５は本発明の第３の
実施形態の混成集積回路装置を示す断面図であり、本実
施形態の放熱板４１が上述した第１及び第２の実施形態
の放熱板１１、３１と異なる点は、平板な放熱板４１の
前記回路基板１の半導体素子２を挟む両側の位置に、該
放熱板４１とは異なる材質の堰状の突起部（突条）４２
を複数本（ここでは３本）ずつ形成した点である。(Third Embodiment) FIG. 5 is a sectional view showing a hybrid integrated circuit device according to a third embodiment of the present invention. The difference from the heat radiating plates 11 and 31 is that a flat heat radiating plate 41 is provided on both sides of the circuit board 1 with the semiconductor element 2 interposed therebetween in the form of a weir-like projection made of a material different from that of the heat radiating plate 41. ) 42
Are formed by a plurality (here, three).
【００３７】この突起部４２は、枠状の桟を取り付けた
り、あるいは樹脂を印刷し硬化させる等の方法を用いて
放熱板４１に簡単に形成することができる。この混成集
積回路装置においても、放熱板４１の取り付け高さを調
整し、封止樹脂１２の流れをコントロールすることがで
き、第１及び第２の実施形態の放熱板１１、３１と同様
の効果を得ることができる。The protruding portion 42 can be easily formed on the heat radiating plate 41 by using a method such as attaching a frame-shaped bar or printing and curing a resin. Also in this hybrid integrated circuit device, the mounting height of the heat radiating plate 41 can be adjusted and the flow of the sealing resin 12 can be controlled, and the same effect as the heat radiating plates 11 and 31 of the first and second embodiments can be obtained. Can be obtained.
【００３８】[0038]
【発明の効果】以上説明した様に、本発明の請求項１ま
たは２記載の混成集積回路装置によれば、放熱板の前記
回路素子と対向する面にキャビティ部を形成したので、
前記回路素子の周囲の最小の領域を封止樹脂で封止する
ことができ、前記放熱板と該回路素子が搭載される回路
基板との間隔を小さくすることができ、厚みを薄くする
ことができ、小型化、軽量化に対応することができる。
また、搭載される回路素子からの熱放散を速やかに行な
うことができ、放熱特性を向上させることができる。As described above, according to the hybrid integrated circuit device of the first or second aspect of the present invention, the cavity portion is formed on the surface of the heat sink facing the circuit element.
The smallest area around the circuit element can be sealed with a sealing resin, the distance between the heat sink and the circuit board on which the circuit element is mounted can be reduced, and the thickness can be reduced. It is possible to cope with miniaturization and weight reduction.
In addition, heat can be quickly dissipated from the mounted circuit element, and heat radiation characteristics can be improved.
【００３９】請求項３ないし６のいずれか１項記載の混
成集積回路装置によれば、前記放熱板の前記回路素子と
対向する面に、溝または突条のいずれか１種を１つ以上
形成したので、封止樹脂は前記溝または突条のいずれか
に沿って流れることになり、封止樹脂のはみ出しを抑制
するとともに封止・接続を行いたい領域に該封止樹脂を
広げることができ、該封止樹脂の厚みの均一性を高め、
放熱特性のばらつきを小さくすることができる。According to the hybrid integrated circuit device of any one of claims 3 to 6, at least one kind of a groove or a ridge is formed on a surface of the heat sink that faces the circuit element. As a result, the sealing resin flows along either the groove or the ridge, so that the sealing resin can be prevented from protruding and the sealing resin can be spread to a region where sealing and connection are desired. Increasing the uniformity of the thickness of the sealing resin,
Variations in heat radiation characteristics can be reduced.
【００４０】本発明の混成集積回路装置の製造方法によ
れば、前記放熱板の所定位置に樹脂を供給する樹脂供給
工程と、前記放熱板に供給された樹脂が前記回路基板に
搭載された回路素子と対向するように位置合わせを行
い、該放熱板を前記樹脂を介して前記回路基板に圧接す
る圧接工程とを備えたので、前記放熱板と回路基板との
間隔を小さくすることができ、使用される封止樹脂の量
を削減することができ、安定した製造条件が得られ、コ
ストダウンを図ることができる。また、前記放熱板と回
路基板との間隔が小さくなるので、搭載される回路素子
からの熱放散が速やかになり、優れた放熱特性を有する
混成集積回路装置を得ることができる。According to the method of manufacturing a hybrid integrated circuit device of the present invention, a resin supply step of supplying a resin to a predetermined position of the heat sink, and a circuit in which the resin supplied to the heat sink is mounted on the circuit board And a pressure contact step of pressing the heat radiating plate to the circuit board via the resin, so that a distance between the heat radiating plate and the circuit board can be reduced, The amount of sealing resin used can be reduced, stable manufacturing conditions can be obtained, and cost reduction can be achieved. Further, since the distance between the heat radiating plate and the circuit board is reduced, heat dissipation from the mounted circuit element is quickened, and a hybrid integrated circuit device having excellent heat radiating characteristics can be obtained.
【図１】 本発明の第１の実施形態の混成集積回路装置
を示す断面図である。FIG. 1 is a sectional view showing a hybrid integrated circuit device according to a first embodiment of the present invention.
【図２】 本発明の第１の実施形態の混成集積回路装置
を示す分解斜視図である。FIG. 2 is an exploded perspective view showing the hybrid integrated circuit device according to the first embodiment of the present invention.
【図３】 本発明の第１の実施形態の混成集積回路装置
の製造方法を示す過程図である。FIG. 3 is a process chart showing a method of manufacturing the hybrid integrated circuit device according to the first embodiment of the present invention.
【図４】 本発明の第２の実施形態の混成集積回路装置
を示す断面図である。FIG. 4 is a sectional view showing a hybrid integrated circuit device according to a second embodiment of the present invention.
【図５】 本発明の第３の実施形態の混成集積回路装置
を示す断面図である。FIG. 5 is a sectional view showing a hybrid integrated circuit device according to a third embodiment of the present invention.
【図６】 従来の混成集積回路装置を示す断面図であ
る。FIG. 6 is a cross-sectional view showing a conventional hybrid integrated circuit device.
１ 回路基板 ２ 半導体素子（回路素子） ３ ボンディングワイヤ ４ プリコート樹脂 ５ 接着樹脂 ６ 放熱板 １１ 放熱板 １２ 封止樹脂 １３ バンプ電極 １４ アンダーフィル樹脂 ２１ キャビティ ２２ 溝 ３１ 放熱板 ３２ 堰となる突起部（突条） ４１ 放熱板 ４２ 堰状の突起部（突条） Ｐ 圧力 DESCRIPTION OF SYMBOLS 1 Circuit board 2 Semiconductor element (circuit element) 3 Bonding wire 4 Precoat resin 5 Adhesive resin 6 Heatsink 11 Heatsink 12 Sealing resin 13 Bump electrode 14 Underfill resin 21 Cavity 22 Groove 31 Heatsink 32 Projection to be a weir ( 41) Heat sink 42 Weir-shaped protrusion (protrusion) P Pressure
Claims (8)
素子を含む回路基板の表面を覆い封止する樹脂と、少な
くとも該樹脂の表面の一部に固定された放熱板とを備え
た混成集積回路装置において、 前記放熱板の前記回路素子と対向する面にキャビティ部
を形成したことを特徴とする混成集積回路装置。1. A hybrid comprising a circuit board on which a circuit element is mounted, a resin for covering and sealing a surface of the circuit board including the circuit element, and a heat sink fixed to at least a part of the surface of the resin. The hybrid integrated circuit device according to claim 1, wherein a cavity portion is formed on a surface of the heat sink facing the circuit element.
子に跨るように形成されていることを特徴とする請求項
１記載の混成集積回路装置。2. The hybrid integrated circuit device according to claim 1, wherein said cavity is formed so as to straddle a plurality of said circuit elements.
に、溝を１つ以上形成したことを特徴とする請求項１ま
たは２記載の混成集積回路装置。3. The hybrid integrated circuit device according to claim 1, wherein one or more grooves are formed on a surface of said heat sink facing said circuit element.
になるように形成されていることを特徴とする請求項３
記載の混成集積回路装置。4. The groove according to claim 3, wherein the groove is formed to be parallel to one side of the heat sink.
A hybrid integrated circuit device as described.
に、突条を１つ以上形成したことを特徴とする請求項１
または２記載の混成集積回路装置。5. The radiator plate according to claim 1, wherein one or more ridges are formed on a surface facing the circuit element.
Or the hybrid integrated circuit device according to 2.
行になるように形成されていることを特徴とする請求項
５記載の混成集積回路装置。6. The hybrid integrated circuit device according to claim 5, wherein said ridge is formed so as to be parallel to one side of said heat sink.
を介して放熱板を固定する混成集積回路装置の製造方法
であって、 前記放熱板の所定位置に樹脂を供給する樹脂供給工程
と、 前記放熱板に供給された樹脂が前記回路基板に搭載され
た回路素子と対向するように位置合わせを行い、該放熱
板を前記樹脂を介して前記回路基板に圧接する圧接工程
と、を備えたことを特徴とする混成集積回路装置の製造
方法。7. A method of manufacturing a hybrid integrated circuit device for fixing a heat sink through a resin on a circuit board on which a circuit element is mounted, the method comprising: supplying a resin to a predetermined position of the heat sink. A pressure contact step of positioning the resin supplied to the heat sink to face a circuit element mounted on the circuit board, and pressing the heat sink to the circuit board via the resin. A method of manufacturing a hybrid integrated circuit device.
されたキャビティ部に樹脂を供給することを特徴とする
請求項７記載の混成集積回路装置の製造方法。8. The method for manufacturing a hybrid integrated circuit device according to claim 7, wherein in the resin supply step, a resin is supplied to a cavity formed in the heat sink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9212296A JP2924867B2 (en) | 1997-08-06 | 1997-08-06 | Hybrid integrated circuit device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9212296A JP2924867B2 (en) | 1997-08-06 | 1997-08-06 | Hybrid integrated circuit device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1154674A true JPH1154674A (en) | 1999-02-26 |
| JP2924867B2 JP2924867B2 (en) | 1999-07-26 |
Family
ID=16620238
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9212296A Expired - Lifetime JP2924867B2 (en) | 1997-08-06 | 1997-08-06 | Hybrid integrated circuit device and method of manufacturing the same |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030092538A (en) * | 2002-05-30 | 2003-12-06 | 주식회사 칩팩코리아 | Tebga package |
| JP2006294983A (en) * | 2005-04-13 | 2006-10-26 | Ricoh Co Ltd | Three-dimensional compact circuit component and its manufacturing method |
| JP2007148439A (en) * | 2001-07-30 | 2007-06-14 | Fujitsu Hitachi Plasma Display Ltd | Plasma display device and flat display device |
| JP2008021810A (en) * | 2006-07-13 | 2008-01-31 | Shinko Electric Ind Co Ltd | Semiconductor module and radiation plate |
| JP2011155147A (en) * | 2010-01-27 | 2011-08-11 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
-
1997
- 1997-08-06 JP JP9212296A patent/JP2924867B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007148439A (en) * | 2001-07-30 | 2007-06-14 | Fujitsu Hitachi Plasma Display Ltd | Plasma display device and flat display device |
| JP4528795B2 (en) * | 2001-07-30 | 2010-08-18 | 日立プラズマディスプレイ株式会社 | Plasma display device and flat display device |
| KR20030092538A (en) * | 2002-05-30 | 2003-12-06 | 주식회사 칩팩코리아 | Tebga package |
| JP2006294983A (en) * | 2005-04-13 | 2006-10-26 | Ricoh Co Ltd | Three-dimensional compact circuit component and its manufacturing method |
| JP4590294B2 (en) * | 2005-04-13 | 2010-12-01 | 株式会社リコー | Manufacturing method of three-dimensional molded circuit components |
| JP2008021810A (en) * | 2006-07-13 | 2008-01-31 | Shinko Electric Ind Co Ltd | Semiconductor module and radiation plate |
| JP2011155147A (en) * | 2010-01-27 | 2011-08-11 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2924867B2 (en) | 1999-07-26 |
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