JPH1152920A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device which displays an inputted image in the center without needing complicated adjustment. SOLUTION: A discriminating circuit 2 compares the voltage set at a level larger than the black level of images with the inputted image data VID. Depending on the presence or not of image information, the numerical value of the horizontal position of the horizontal counter 7H counted by a second clock signal DCLK is held in a first horizontal holding circuit 81H and a first horizontal comparing circuit 91H as the horizontal starting position of images and in the second horizontal holding circuit 82H and the second horizontal comparing circuit 92H as the horizontal finishing position of images. The numerical value of the vertical position of the vertical counter 7V counted by the horizontal synchronizing signal Hs is held in the first vertical holding circuit 81V and the first vertical comparing circuit 91V as the vertical starting position of images and in the second vertical holding circuit 82V and the second vertical comparing circuit 92V as the vertical finishing position of images. The CPU 10 reads the numerical values of the horizontal comparing circuit, controls the divided frequency value of the clock so that the horizontal displaying period is equal to the number of horizontal display pixels of the LCD 14, and a controller 13 displays and controls inputted images in the center of the LCD 14, using the numerical values of the horizontal comparing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device,
In particular, the present invention relates to a display device provided with a display position adjusting unit.

[0002]

2. Description of the Related Art In a conventional display device (not shown), when image data is input, a CPU determines the type of timing of input image data from the frequencies of a horizontal synchronizing signal and a vertical synchronizing signal. The clock division number, the position correlation data, and the delay time for the image data of the type are read out and output to the clock circuit, the controller, and the delay circuit.
The clock circuit is a clock signal of the frequency obtained by multiplying the frequency of the horizontal synchronization signal by the frequency division number, the delay circuit is a clock signal that delays the clock signal by the delay time, and the controller is based on the position correlation data from the horizontal synchronization signal and the vertical synchronization signal. And outputs a signal indicating a display position in the image data.
The image data is latched and displayed by the clock signal during the period indicated by the signal.

When the frequency division number, delay time and position correlation data read from the memory match the timing of input image data, the image data is displayed at the center of the LCD and the correlation position data does not match. Sometimes, the display position is displayed shifted, and when the frequency division number does not match, the width is displayed narrow or wide, and when the delay time does not match, the data of one pixel is displayed on the LCD for two pixels, The display flickers.

Further, when image data is not displayed at the center of the LCD, UP, DOWN, RIGHT, LE
By pressing the FT key, the CPU corrects the correlation data output to the controller corresponding to each switch, and
When the position of the image to be displayed is adjusted and the frequency division number is adjusted, by pressing the NARROW and WIDE keys, the control circuit corrects the frequency division number output to the clock circuit corresponding to each switch, The width of the image to be displayed on the LCD is adjusted. If the delay time does not match, the + and-keys of the PHASE key are operated so that one pixel of the input image data is displayed on one pixel of the LCD. The delay time output to the delay circuit is corrected.

[0005]

SUMMARY OF THE INVENTION In a conventional display device,
If the frequency of the synchronization signal of the input image data and the correlation timing of the horizontal synchronization signal and the vertical synchronization signal are different, the display position of the image data is shifted. There was a problem that it was necessary to adjust mainly.

Accordingly, an object of the present invention is to provide a display device capable of easily adjusting a display image.

[0007]

In order to solve the above-mentioned problems, a display device according to the present invention is arranged so that the display device according to the frequency division number synchronized with the image data transmitted based on the horizontal synchronizing signal and the vertical synchronizing signal. A clock circuit for generating one clock signal, a delay circuit for delaying a first clock signal of the clock circuit by a predetermined delay amount and outputting a second clock signal,
A horizontal counter for counting the horizontal synchronization signal by the second clock signal of the delay circuit to count the number of clocks in one horizontal synchronization period; and a horizontal synchronization for one vertical period by counting the vertical synchronization signal by the horizontal synchronization signal. A vertical counter for counting the number of pixels, a discrimination circuit for comparing the voltage between the black level and the white level of the image data with the voltage of the image data, and outputting a discrimination signal. A control circuit for outputting a timing signal for outputting image data other than black in the vertical direction, and the timing signal of the control circuit holds the value of the horizontal counter and holds the image start position and image end position in the horizontal direction A vertical holding circuit that holds the value of the vertical counter and holds the image start position and the image end position in the vertical direction by the output of the control circuit. A circuit, display means for displaying the image data, a controller for controlling a display position of the image data displayed on the display means, and a switch for setting the image data controlled by the controller to be displayed at the center. And a CPU for reading the image start position and the image end position by this switch and controlling the image data to be displayed at the center of the display means.

[0008]

Next, a display device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of the display device according to one embodiment of the present invention.

FIG. 3 is a signal waveform diagram of the display device according to one embodiment of the present invention.

A display device according to an embodiment of the present invention comprises:
As shown in FIG. 1, image data VID latched by the first clock signal CLK during the display period of the signal DE and transmitted based on the horizontal synchronization signal Hs and the vertical synchronization signal Vs.
, A clock circuit 3 that generates a first clock signal CLK having a frequency controlled by the serial signal SER and multiplied by the frequency division number, and transmitted by the serial signal SER. A delay circuit 4 for outputting a second clock signal DCLK delayed by a predetermined delay time, and a signal DE indicating the display position of the image data VID from the horizontal synchronization signal Hs and the vertical synchronization signal Vs based on the correlation data transmitted by the serial signal SER. , A memory 11 for holding correlation data of a clock division number, a clock delay time, and a display position which are different for each timing signal of the image data VID, a switch 12, and a binary number 11111111 by an RST signal.
Hs is set to 111 or 2047 in decimal.
The value held internally at the falling edge of the signal and HB (0: 1
0), a first horizontal comparison circuit 91H provided with an 11-bit register holding the smaller value, and RS
It is reset to 0 by the T signal, compares the internally held value at the falling edge of the horizontal synchronization signal Hs with the value of HF (0:10), and includes an 11-bit register that holds the larger value. 2 The horizontal comparison circuit 92H is set to 2047 by the RST signal, compares the internally held value at the falling edge of the Vs signal with the value of VB (0:10), and holds the smaller value of 11 bits. A first vertical comparison circuit 91V having a register and 0
And compares the internally held value with the value of VF (0:10) at the fall of the Vs signal, and provides a second vertical comparison circuit 92V having an 11-bit register for holding the larger value. , The latch signal LHB changes from LOW to HIG
Holds the value of Hc (0:10) when changed to H 11
The first horizontal holding circuit 81H provided with a bit register and the H level when the latch signal LHF changes from LOW to HIGH.
The second horizontal holding circuit 82H provided with an 11-bit register holding the value of c (0:10) and the latch signal LVB
A first vertical holding circuit 81V provided with an 11-bit register for holding the value of Vc (0:10) when OW changes to HIGH, and Vc (0:10) when the latch signal LVF changes from LOW to HIGH ), And a control circuit that generates latch signals LHB, LHF, LVB, and LVF using the horizontal synchronization signal Hs, the vertical synchronization signal Vs, and the determination signal VD as inputs. 5, the voltage of the image data VID and the voltage V1
Are compared, and when the voltage of the image data VID is higher than the voltage V1, the signal VD is set to HIGH and the image data VI
When the voltage of D is lower than the voltage V1, the signal VD is set to LOW.
, A D / A converter 1 that outputs a voltage V1 controlled by the serial signal SER, and 11 bits that are reset during the LOW period of the horizontal synchronization signal Hs and counted by the second clock signal DCLK Is reset during the LOW period of the horizontal counter 7H and the signal Vs,
An 11-bit vertical counter 7V counting by the horizontal synchronizing signal Hs and the second clock signal DCLK are detected by the detection signal VD.
The timing of the image data VID is determined from the detection circuit 6 that latches at the rising edge of the signal and outputs the detection signal CD, and the input horizontal synchronization signal Hs and vertical synchronization signal Vs.
The position correlation data indicating the display position is read from the frequency division number, the clock delay time, and the synchronization signal of the determined mode from the memory 11 and the serial signal SER is controlled to set the frequency division number to the clock circuit 3 and the delay time to the delay circuit 4. To output the position correlation data to the controller 13,
The signal RST is generated by the operation of the switch 12, and the first horizontal comparison circuit 91H and the second
Data obtained by reading the values of the horizontal comparison circuit 92H, the first vertical comparison circuit 91V, and the second vertical comparison circuit 92V and the detection signal C
It comprises a delay circuit 4, a clock circuit 3, and a CPU 10 for controlling the controller 13 based on the value of D.

The switch 12 includes an UP, DOWN, RIGHT, and LEFT key for correcting correlation data, a NARROW, WIDE key for correcting the frequency division number, and an LCD.
+ And-keys of a PHASE key for correcting the delay time by adjusting the width of the image data VID displayed at 14
And an AUTO key for adjusting the display position of the image data VID.

Next, the operation of the display device according to one embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 1, when the horizontal synchronizing signal Hs and the vertical synchronizing signal Vs are inputted, the CPU 10 determines the inputted image data VID. Do, VGA, SVGA, XG
A frequency division number, a clock delay time and position correlation data corresponding to the determined image mode such as A are read out from the memory 11 and the clock circuit 3 controls the frequency division number via the serial signal SER to control the horizontal synchronization signal. Control is performed so as to output a first clock signal CLK having a frequency obtained by multiplying the frequency of Hs by the frequency division number, and output a delay time to the delay circuit 4 to delay the first clock signal CLK by a predetermined time. Control is performed so as to output the correlation data and output a signal DE indicating the display position of the image data VID, and the LCD 14 latches the second clock signal DCLK to display the image data VID during a period designated by the signal DE.

If the frequency division number and the position correlation data read from the memory 11 match the image timing of the input image data VID, the image data VID is displayed at the center of the LCD 14, but the correlation data is not displayed. If they do not match, the display position is shifted or the number of divisions is not set, and the image is displayed short in the horizontal direction or long in the horizontal direction. If the delay time does not match, one pixel is displayed. Is displayed on the LCD 14 for two pixels, or the display flickers.

If the displayed image does not match, the display position is adjusted by pressing the AUTO key of the switch 12, and the CPU 10 receives the voltage V via the serial signal SER.
1, the D / A converter 1 is controlled so as to output a voltage which can determine that an image is present in the signal VID, the discrimination circuit 2 compares the voltage of the image data VID with the voltage V1, and outputs If it is determined that an image is present, a signal VD is output as shown in the waveform diagram of FIG.

Further, when the AUTO key of the switch 12 is pressed, the CPU 10 outputs a HIGH pulse signal as the signal RST, and sets the register values of the first horizontal comparison circuit 91H and the first vertical comparison circuit 91V to 2047 and to the second signal. The values of the horizontal comparison circuit 92H and the second vertical comparison circuit 92V are reset to 0. First, the horizontal position detection operation is performed by the horizontal counter 7H at the falling edge of the horizontal synchronization signal Hs (T1 in FIG. 2).
Is reset and the rising edge of the horizontal synchronizing signal Hs (FIG. 2)
From the second clock signal DCLK at T2), counting until the next fall of the synchronization signal Hs (T5 in FIG. 2), outputting the counted value as Hc (0:10), and 5, the latch signal LHB becomes LOW at the fall of the horizontal synchronization signal Hs as shown in FIG.
When the detection signal VD becomes HIGH (T3 in FIG. 2), H
Output as IGH level.

On the other hand, the first horizontal holding circuit 81H outputs Hc (0: 1) at the rise of the latch signal LHB (T3 in FIG. 2).
0) is held, and the held value is output to the first horizontal comparison circuit 91H as HB (0:10), and the first horizontal comparison circuit 91H outputs the next falling edge of the horizontal synchronization signal Hs (FIG. 2).
The value held in T5) is compared with the value of HB (0:10), and the smaller value is held, and this operation is repeated for one vertical period, so that one screen is displayed from the fall of the horizontal synchronization signal Hs. Of the displayed image up to the leftmost pixel is held in the first horizontal comparison circuit, and the control circuit 5 similarly controls the latch signal LH
F is output as an inverted signal of the detection signal VD as shown in FIG. 2, and the second horizontal holding circuit 82H holds the value of Hc (0:10) at the rise of the latch signal LHF.

The held value is output to the second horizontal comparison circuit 92H as HB (0:10), and the second horizontal comparison circuit 92H holds the value at the next fall of the horizontal synchronization signal Hs (T5 in FIG. 2). HB (0:10) held at the last rising edge of the latched signal LHF (T4 in FIG. 2).
By repeating this operation for one vertical period, the position from the fall of the synchronizing signal Hs to the rightmost pixel of the display image in one screen is compared with the second horizontal comparison. It is held in the circuit 92H.

Next, in the vertical position detecting operation, the vertical counter 11 is reset at the falling edge of the vertical synchronizing signal Vs (T6 in FIG. 3), and the horizontal synchronizing signal Hs is used as a clock to detect the next vertical synchronizing signal Vs. Fall (T1 in FIG. 3)
0), and counts the value to Vc (0: 1).
0), the control circuit 5 latches the detection signal VD at the rising edge of the horizontal synchronization signal Hs, and holds the detection signal VD held in the horizontal synchronization period of the next line where the detection signal VD is generated.
Create a DH.

Thereafter, the control circuit 5 outputs the vertical synchronization signal Vs
At the falling edge (T6 in FIG. 3), the detection signal V
When HD becomes HIGH (T8 in FIG. 3), the latch signal LVB which becomes HIGH level is output, and the first vertical holding circuit 81V rises the latch signal LVB (T8 in FIG. 3).
8), the value of Vc (0:10) is held, and the held value is output to the first vertical comparison circuit 91V as VB (0:10), and the first vertical comparison circuit 91V outputs the next synchronization signal Vs
At the falling edge (T10 in FIG. 3) and VB
Compare the value of (0:10), hold the smaller value,
By repeating this operation for several vertical periods, the position from the falling edge of the synchronization signal Vs to the top pixel of the display image in one screen is held in the first vertical comparison circuit 91V.

Similarly, the control circuit 5 outputs the latch signal LVF as an inverted signal of the detection signal VHD as shown in FIG.
The second vertical holding circuit 82V holds the value of Vc (0:10) at the rising edge of the latch signal LVF (T9 in FIG. 3),
The held value is output to the second vertical comparison circuit 92V as VB (0:10), and the second vertical comparison circuit 92V outputs the value held at the next fall of the vertical synchronization signal Vs (T10 in FIG. 3). And the value of VB (0:10) is compared, and the larger value is held. By repeating this operation for several vertical periods, the position from the fall of the vertical synchronization signal Vs to the lowest pixel of the display image in one screen is held in the second vertical comparison circuit 92V.

Next, the CPU 10 sends the first horizontal comparator 91H and the second horizontal comparator 92 via the serial signal SER.
H, first vertical comparison circuit 91V, second vertical comparison circuit 92V
The CPU 10 reads the position data of the horizontal synchronization signal Hs held in the first horizontal comparison circuit 91H from the rightmost pixel position of the image from the fall of the horizontal synchronization signal Hs held in the second horizontal comparison circuit 92H. The period of the second clock signal DCLK obtained by equation (1) so that the value obtained by subtracting the leftmost pixel position of the image from the falling edge, that is, the number of horizontal display pixels is equal to the number of horizontal pixels of the LCD 14. Is calculated, and the frequency division number for generating the cycle is output to the clock circuit 3, whereby the image of the input signal is displayed on the entire LCD 14 in the horizontal direction. DCLK cycle to be calculated = (number of horizontal display pixels) × (current DCLK cycle) ÷ (number of pixels in horizontal direction of LCD) --- Equation (1)

The CPU 19 also includes a first horizontal comparison circuit 91
The controller 13 is controlled based on the horizontal image position information of the leftmost pixel held in H so that the leftmost pixel is LC
The display position is controlled in the horizontal direction so that the leftmost pixel of D14 can be displayed, and the position information of the uppermost pixel held in the first vertical comparison circuit 91V and the second vertical comparison circuit 92V
The controller 13 controls the controller 13 based on the position information of the lowermost pixel stored in the LCD 14 to control the display position so that the display image is displayed at the center of the LCD 14.

Further, the CPU 10 outputs the serial signal SE
By controlling the delay circuit 4 via R to gradually change the delay time, the signal of the detection signal CD at that time is changed from LOW to HI.
The CPU 10 measures the delay time at which the signal GH is changed to GH, and the CPU 10 adds the measured delay time to the delay time at which the image displayed on the LCD 14 can be clearly displayed from the delay time at which the predetermined detection signal CD changes from LOW to HIGH. The time is output to the delay circuit 4, and the LCD 14 can reliably latch the image data VID with the DCLK signal controlled by the delay circuit 4.

[0027]

As described above, according to the display device of the present invention, it is possible to display image data that is not correctly displayed with preset adjustment values in the center of the display means without requiring complicated adjustment. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display device according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of a display device according to an embodiment of the present invention.

FIG. 3 is a signal waveform diagram of a display device according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 D / A converter 2 discriminating circuit 3 clock circuit 4 delay circuit 5 control circuit 6 CPU (detection circuit) 10 CPU 11 CPU (memory) 12 switch 13 controller 14 LCD 7H horizontal counter 7V vertical counter 91H horizontal comparison circuit (first circuit) Horizontal comparison circuit) 92H Horizontal comparison circuit (second horizontal comparison circuit) 91V Vertical comparison circuit (first vertical comparison circuit) 92V Vertical comparison circuit (second vertical comparison circuit)

Claims (1)

[Claims] 1. A first synchronization method according to a frequency division number synchronized with image data transmitted based on a horizontal synchronization signal and a vertical synchronization signal.
A clock circuit for generating a clock signal, and a second clock signal obtained by delaying a first clock signal of the clock circuit by a predetermined delay amount.
A delay circuit that outputs a clock signal; a horizontal counter that counts the number of clocks in one horizontal synchronization period by counting the horizontal synchronization signal with a second clock signal of the delay circuit; A vertical counter that counts and counts the number of horizontal synchronizations in one vertical period; a discrimination circuit that compares a voltage between the black level and the white level of the image data with a voltage of the image data to output a discrimination signal; A control circuit for outputting a timing signal in which image data other than black is output in the horizontal / vertical direction from a determination signal of the determination circuit; and a timing signal of the control circuit for holding a value of a horizontal counter, A horizontal holding circuit for holding an image start position and an image end position, and an output of the control circuit holds a value of a vertical counter to start a vertical image. A vertical holding circuit for holding a position and an image end position, a display means for displaying the image data, a controller for controlling a display position of the image data displayed on the display means, and the image controlled by the controller A switch for setting the data to be displayed at the center, and a CPU for reading the image start position and the image end position by the switch and controlling the image data to be displayed at the center of the display means. Characteristic display device.