JPH11511941A - 動作プログラム可能論理装置における部分的プログラミング回路 - Google Patents
動作プログラム可能論理装置における部分的プログラミング回路Info
- Publication number
- JPH11511941A JPH11511941A JP10503122A JP50312298A JPH11511941A JP H11511941 A JPH11511941 A JP H11511941A JP 10503122 A JP10503122 A JP 10503122A JP 50312298 A JP50312298 A JP 50312298A JP H11511941 A JPH11511941 A JP H11511941A
- Authority
- JP
- Japan
- Prior art keywords
- programmable
- instruction
- function
- functional unit
- functional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17752—Structural details of configuration resources for hot reconfiguration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.プログラム可能論理装置において、 プログラミング命令を受取る命令バス、 前記命令バスへ接続されている第一のプログラム可能な機能ユニット、 前記命令バスへ接続されている第二のプログラム可能な機能ユニット、 前記第一及び第二プログラム可能な機能ユニットの各々へ接続されている命令 ブロッキング回路であって、前記命令バスから前記第一及び第二のプログラム可 能な機能ユニットのうちの1つへのプログラミング命令を選択的にブロッキング する命令ブロッキング回路、 を有している装置。 2.請求項1において、前記命令ブロッキング回路がコマンドバスへ接続し ているレジスタである装置。 3.請求項1において、前記第一のプログラム可能な機能ユニットが再プロ グラム可能である装置。 4.請求項1において、前記第一のプログラム可能な機能ユニットが第一論 理機能を実施すべくプログラムされ且つ前記第二のプログラム可能な機能ユニッ トが第二の論理機能を実施すべくプログラムされ、且つ前記第二のプログラム可 能な機能ユニッ トが、前記第一のプログラム可能な機能ユニットが前記第一の論理機能を実施し ている期間中に、再プログラム可能である装置。 5.請求項1において、前記ブロッキング回路が、 前記命令バスへ接続している入力ノード、 前記第一及び第二の機能ユニットへ夫々接続している第一及び第二の出力ノー ド、 を有している装置。 6.請求項5において、前記入力ノードが、前記命令バス上のブロッキング 命令を受取るべく形態とされ、前記ブロッキング命令が前記第一及び第二の命令 ユニットのうちのいずれが前記命令バス上の爾後のプログラミング命令に応答す るかを表わす装置。 7.集積回路において、 第一及び第二の論理機能を夫々実施すべくプログラムされる第一及び第二のプ ログラム可能な機能ユニット、 前記第二のプログラム可能な機能ユニットが前記第二の論理機能を実施してい る期間中に前記第一のプログラム可能な機能ユニットを再プログラムする手段、 を有している集積回路。 8.請求項7において、更に、前記第一のプログラム可能な機能ユニットが 前記第一の論理機能を実施している期間中に、前記第二のプログラム可能な機能 ユニットを再プログラムする手段を有している回路。 9.第一及び第二の機能ユニットを具備するプログラム可能な論理装置を部 分的に再プログラミングする方法において、前記第一及び第二の機能ユニットが 夫々第一及び第二の論理機能を実施すべくプログラムされるものであって、前記 プログラム可能な論理装置へプログラミング命令を供給し、且つ前記第一機能ユ ニットが該命令に応答することがないように前記第一機能ユニットに対して前記 命令をブロッキングする方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/670,472 | 1996-06-26 | ||
US08/670,472 US5764076A (en) | 1996-06-26 | 1996-06-26 | Circuit for partially reprogramming an operational programmable logic device |
PCT/US1997/010147 WO1997050177A1 (en) | 1996-06-26 | 1997-06-11 | Circuit for partially reprogramming an operational programmable logic device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11511941A true JPH11511941A (ja) | 1999-10-12 |
JP3930053B2 JP3930053B2 (ja) | 2007-06-13 |
Family
ID=24690534
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50312298A Expired - Lifetime JP3930053B2 (ja) | 1996-06-26 | 1997-06-11 | 動作プログラム可能論理装置における部分的プログラミング回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5764076A (ja) |
EP (1) | EP0846370A2 (ja) |
JP (1) | JP3930053B2 (ja) |
WO (1) | WO1997050177A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005510781A (ja) * | 2001-10-17 | 2005-04-21 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 取り付け可能なサブモジュールを有する電子装置のオンザフライコンフィギュレーション |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5986467A (en) * | 1997-10-31 | 1999-11-16 | Xilinx, Inc. | Time-multiplexed programmable logic devices |
US6102963A (en) * | 1997-12-29 | 2000-08-15 | Vantis Corporation | Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's |
US5968196A (en) * | 1998-04-21 | 1999-10-19 | Atmel Corporation | Configuration control in a programmable logic device using non-volatile elements |
US5889701A (en) * | 1998-06-18 | 1999-03-30 | Xilinx, Inc. | Method and apparatus for selecting optimum levels for in-system programmable charge pumps |
US6463588B1 (en) * | 1998-10-08 | 2002-10-08 | Scientific-Atlanta, Inc. | Method and apparatus for restoring port status in a cable television tap |
US6107821A (en) * | 1999-02-08 | 2000-08-22 | Xilinx, Inc. | On-chip logic analysis and method for using the same |
US6507211B1 (en) | 1999-07-29 | 2003-01-14 | Xilinx, Inc. | Programmable logic device capable of preserving user data during partial or complete reconfiguration |
US6748456B1 (en) * | 2000-09-29 | 2004-06-08 | Cypress Semiconductor Corp. | PLD configuration port architecture and logic |
US6981153B1 (en) | 2000-11-28 | 2005-12-27 | Xilinx, Inc. | Programmable logic device with method of preventing readback |
US7117373B1 (en) | 2000-11-28 | 2006-10-03 | Xilinx, Inc. | Bitstream for configuring a PLD with encrypted design data |
US6965675B1 (en) * | 2000-11-28 | 2005-11-15 | Xilinx, Inc. | Structure and method for loading encryption keys through a test access port |
US7058177B1 (en) | 2000-11-28 | 2006-06-06 | Xilinx, Inc. | Partially encrypted bitstream method |
US6931543B1 (en) | 2000-11-28 | 2005-08-16 | Xilinx, Inc. | Programmable logic device with decryption algorithm and decryption key |
US6957340B1 (en) | 2000-11-28 | 2005-10-18 | Xilinx, Inc. | Encryption key for multi-key encryption in programmable logic device |
US7117372B1 (en) | 2000-11-28 | 2006-10-03 | Xilinx, Inc. | Programmable logic device with decryption and structure for preventing design relocation |
GB2407730A (en) * | 2003-10-30 | 2005-05-04 | Agilent Technologies Inc | Programmable network monitoring element |
US20050099832A1 (en) * | 2003-11-12 | 2005-05-12 | Agere Systems, Incorporated | System and method for securing an integrated circuit as against subsequent reprogramming |
US7752004B1 (en) * | 2004-01-09 | 2010-07-06 | Cisco Technology, Inc. | Method and apparatus for configuring plurality of devices on printed circuit board into desired test port configuration |
US7343578B1 (en) * | 2004-08-12 | 2008-03-11 | Xilinx, Inc. | Method and system for generating a bitstream view of a design |
US7406673B1 (en) | 2004-08-12 | 2008-07-29 | Xilinx, Inc. | Method and system for identifying essential configuration bits |
US7519823B1 (en) | 2004-08-12 | 2009-04-14 | Xilinx, Inc. | Concealed, non-intrusive watermarks for configuration bitstreams |
US20060080632A1 (en) * | 2004-09-30 | 2006-04-13 | Mathstar, Inc. | Integrated circuit layout having rectilinear structure of objects |
US20070247189A1 (en) * | 2005-01-25 | 2007-10-25 | Mathstar | Field programmable semiconductor object array integrated circuit |
JP4388903B2 (ja) * | 2005-02-09 | 2009-12-24 | 富士通マイクロエレクトロニクス株式会社 | Jtag試験方式 |
US7406642B1 (en) * | 2005-10-03 | 2008-07-29 | Altera Corporation | Techniques for capturing signals at output pins in a programmable logic integrated circuit |
US20090079467A1 (en) * | 2007-09-26 | 2009-03-26 | Sandven Magne V | Method and apparatus for upgrading fpga/cpld flash devices |
US20090144595A1 (en) * | 2007-11-30 | 2009-06-04 | Mathstar, Inc. | Built-in self-testing (bist) of field programmable object arrays |
US8174287B2 (en) * | 2009-09-23 | 2012-05-08 | Avaya Inc. | Processor programmable PLD device |
KR20140134797A (ko) * | 2013-05-14 | 2014-11-25 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이의 동작 방법 |
US9164939B2 (en) * | 2013-10-21 | 2015-10-20 | Altera Corporation | Circuitry and techniques for updating configuration data in an integrated circuit |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63245016A (ja) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | プログラマブル・ロジツク・デバイス |
US5412260A (en) * | 1991-05-03 | 1995-05-02 | Lattice Semiconductor Corporation | Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device |
US5550782A (en) * | 1991-09-03 | 1996-08-27 | Altera Corporation | Programmable logic array integrated circuits |
US5329179A (en) * | 1992-10-05 | 1994-07-12 | Lattice Semiconductor Corporation | Arrangement for parallel programming of in-system programmable IC logical devices |
GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
JPH06276086A (ja) * | 1993-03-18 | 1994-09-30 | Fuji Xerox Co Ltd | フィールドプログラマブルゲートアレイ |
US5654650A (en) * | 1995-12-11 | 1997-08-05 | Hewlett-Packard Company | High throughput FPGA control interface |
US5623217A (en) * | 1996-02-26 | 1997-04-22 | Lucent Technologies Inc. | Field programmable gate array with write-port enabled memory |
-
1996
- 1996-06-26 US US08/670,472 patent/US5764076A/en not_active Expired - Lifetime
-
1997
- 1997-06-11 JP JP50312298A patent/JP3930053B2/ja not_active Expired - Lifetime
- 1997-06-11 EP EP97929942A patent/EP0846370A2/en not_active Withdrawn
- 1997-06-11 WO PCT/US1997/010147 patent/WO1997050177A1/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005510781A (ja) * | 2001-10-17 | 2005-04-21 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 取り付け可能なサブモジュールを有する電子装置のオンザフライコンフィギュレーション |
Also Published As
Publication number | Publication date |
---|---|
JP3930053B2 (ja) | 2007-06-13 |
EP0846370A2 (en) | 1998-06-10 |
US5764076A (en) | 1998-06-09 |
WO1997050177A1 (en) | 1997-12-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH11511941A (ja) | 動作プログラム可能論理装置における部分的プログラミング回路 | |
US5237218A (en) | Structure and method for multiplexing pins for in-system programming | |
US6614259B2 (en) | Configuration memory integrated circuit | |
US7652500B1 (en) | Reconfiguration of programmable logic devices | |
US7576561B1 (en) | Device and method of configuring a device having programmable logic | |
US7330912B1 (en) | Configuration in a configurable system on a chip | |
US5809281A (en) | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM | |
US7630259B1 (en) | Programmable logic device with built in self test | |
JP2818803B2 (ja) | プログラム可能な論理装置 | |
US7463056B1 (en) | Writeable shift register lookup table in FPGA with SRAM memory cells in lookup table reprogrammed by writing after initial configuration | |
US7489163B2 (en) | FPGA powerup to known functional state | |
US7864620B1 (en) | Partially reconfigurable memory cell arrays | |
US7304493B2 (en) | FPGA powerup to known functional state | |
US8174287B2 (en) | Processor programmable PLD device | |
US8689068B2 (en) | Low leakage current operation of integrated circuit using scan chain | |
US6029236A (en) | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM | |
US6327632B1 (en) | Adaptable I/O pins manifesting I/O characteristics responsive to bit values stored in selected addressable storage locations, each pin coupled to three corresponding addressable storage locations | |
US7579865B1 (en) | Selective loading of configuration data into configuration memory cells | |
EP0420388A2 (en) | Test latch circuit | |
US20060017461A1 (en) | Methods and systems for providing hardware assisted programming of a programmable logic device in an embedded system | |
US7570078B1 (en) | Programmable logic device providing serial peripheral interfaces | |
US7876125B1 (en) | Register data retention systems and methods during reprogramming of programmable logic devices | |
US6900661B2 (en) | Repairable finite state machines | |
KR100733636B1 (ko) | 프로그램가능한 디바이스 및 그 프로그래밍 방법 | |
US6680871B1 (en) | Method and apparatus for testing memory embedded in mask-programmable logic device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040610 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060328 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060628 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060905 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061205 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20070206 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20070308 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100316 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110316 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120316 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130316 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130316 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140316 Year of fee payment: 7 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |