JPH1148975A - Double system electronic interlocking device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a device in scale, simplify the device and reduce the number of developing process by mutually exchanging arithmetic result of each arithmetic processing means and interrupting each arithmetic processing means and an external device when a mismatch is generated at least one side by collating each arithmetic result of one side and the other side. SOLUTION: An arithmetic result of a CPU 1 is transmitted to a CPU 2 through a serial communication line 3, an arithmetic result of the CPU 2 is transmitted to the CPU 1 through a serial communication line 4 and the arithmetic results are collated at each of the CPU 1 and the CPU 2. Exciting signals are inputted into a CPU mismatch detector 5 from the CPU 1 and the CPU 2. The CPU mismatch detector 5 detects that at least either one of the collating results of each arithmetic result in the CPU 1, 2 is mismatched when either one of the exciting signals are interrupted. When the CPU mismatch detector 5 detects that the collating result is mismatching, the detector 5 energizes a relay 6 and interrupts an interface between the detector 5 and an external device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dual CPU.
(Central Processing Unit)
In particular, the present invention relates to a dual-system electronic interlocking device that supports high-speed processing and improves the processing accuracy.

[0002]

2. Description of the Related Art FIG. 16 schematically shows a conventional electronic interlocking device disclosed in, for example, the 24th JSTI Reliability and Maintainability Symposium Paper "Fault-Tolerant Design of a Controller for CARAT with Multiprocessor Configuration". FIG.

The CPU 14 and the CPU 15 are connected to the system bus 9 via a bus 16 and a bus 17, respectively, and receive a clock output from an oscillator (not shown). In addition, the general-purpose comparison circuit 18 and the FS (F
aile Safe) matching circuit 19 is provided between the bus 16 and the bus 17, and includes the CPU 14 and the CPU
Fifteen calculation results are input. In addition,
A ROM / RAM 20 is connected to the bus 16 and the bus 17, respectively.

In such an electronic interlocking device, a CPU
14 and the CPU 15 perform processing completely in synchronization with each other at the clock level, and check the bus data in the machine cycle for each cycle to diagnose the soundness. Realizes safety by bringing down the electronic interlocking device.

[0005] The content of the collation processing of each CPU will be described below. The CPU 14 and the CPU 15 execute the same program in synchronization with the same clock. CPU 14, C
The calculation result as the data output by the PU 15 is
6. The signal is input to the pre-comparison circuit 18 via the bus 17. After comparing the respective calculation results by the pre-use general comparison circuit 18, if the comparison results match, the result is represented by F
S is transmitted to the S matching circuit 19 to activate the FS matching circuit 19,
Advance the machine cycle.

If the collation results do not match, a cycle retry signal for restarting a series of processing operations from the arithmetic processing is sent from the general-purpose pre-comparison circuit 18 to the CPU 1.
Sent to 4, 15 to re-execute the machine cycle.
If such machine cycle repetition (retry) is performed three or more times in succession, an interrupt signal is transmitted to proceed to the next step.

When the comparison result in the pre-general-purpose comparison circuit 18 matches, the FS collation circuit 19 receives the start signal from the pre-general-purpose comparison circuit 18 and receives the bus 16 and the bus 17.
The above data is collated, and the computation result is output to the system bus 9 only when the collation results match. If the collation results are inconsistent, the system is brought down by determining that an abnormality has occurred, and if the system has a redundant system, further processing such as system switching is performed.

[0008]

However, since the conventional electronic interlocking device is configured as described above, the configuration of the matching circuit is complicated. For this reason, if a high-speed, high-performance processor is used in order to fulfill the demand for higher performance of the device accompanying the sophistication of train operation control, the verification circuit becomes complicated and the circuit scale becomes large, Further, there is a problem that the development cost is increased and the development period is lengthened, such as the necessity of developing a new dedicated LSI.

Accordingly, the present invention has been made to solve the above-described problems, and has safety without requiring a complicated and large-scale circuit, and can be developed in a short time. It is an object of the present invention to provide a dual electronic interlocking device.

[0010]

The dual electronic interlocking device according to the present invention comprises a first arithmetic processing means and a second arithmetic processing means for performing the same arithmetic processing based on the same input information;
An operation result exchange means for mutually exchanging the operation results by each operation processing means based on an operation result transmission request command, and the other operation processing means received via the operation result exchange means of each operation processing means and its own operation result When the collation result confirmation means for confirming each collation result with the computation result and the collation result confirmation means determine that a mismatch has occurred in the collation result by at least one of the computation processing means, , The first and second arithmetic processing means and an external device.

Each of the arithmetic processing means includes a first communication time for transmitting an operation result transmission request command via the operation result exchange means and then waiting for reception of the operation result; Setting a second communication time for transmitting the operation result to the other operation processing unit and then waiting for the other operation processing unit to receive the operation result when the operation result transmission request command is received. Features.

Further, each of the arithmetic processing means sets a third communication time for waiting for reception of a calculation result transmission request command after receiving a standby command during the first communication time. I do.

The first communication time and the second communication time are based on an arithmetic processing time for performing an arithmetic processing, a transmission time of an arithmetic result transmission request command, and a transmission time of an arithmetic result. Is set.

Further, the first communication time and the second communication time are set based on a required time for transmission of a calculation result and a required time for transmission of a calculation result transmission request command.

The first communication time and the second communication time are based on an average required time of a predetermined number of past times of a required transmission time of the calculation result and a required transmission time of the calculation result transmission request command. It is characterized by being set.

Further, the third communication time is set based on a calculation processing time for performing a calculation process, a required transmission time of a calculation result, and a required transmission time of a calculation result transmission request command. Features.

Each of the arithmetic processing means transmits a collation processing end signal to the other arithmetic processing means when the collation results of the respective arithmetic results match.

If the first arithmetic processing means or the second arithmetic processing means does not establish communication with the other arithmetic processing means a predetermined number of times or more, the first arithmetic processing means or the second arithmetic processing means activates the cutoff means to activate the first and second arithmetic processing means. And the external device is shut off.

Further, the present invention is characterized in that data indicating the current processing stage is added to communication contents exchanged between the first and second arithmetic processing means via the arithmetic result exchange means.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a block diagram schematically showing a main configuration of a dual electronic interlocking device according to Embodiment 1 of the present invention. In the figure, reference numeral 1 denotes C as a first calculating means.
PU 2 is a CPU serving as a second calculating means, and these execute a calculating program that functions as an interlocking device.

Reference numerals 3 and 4 denote serial communication lines as operation result exchange means.
The serial communication line 4 is provided for transmitting the calculation result of the CPU 2 to the CPU 1 as collation data.

In the figure, reference numeral 5 denotes a mismatch detector as a verification result confirmation means. The mismatch detector 5 includes the CPU 1 and C
An excitation signal from PU2 is input. Discrepancy detector 5
When any one of the excitation signals is interrupted, it detects that at least one of the comparison results of the computation results in the CPUs 1 and 2 does not match. A relay 6 is provided between the electronic interlocking device and an external device (not shown).

When the inconsistency detector 5 detects that the collation results of the CPUs 1 and 2 are inconsistent, the inconsistency detector 5 excites the relay 6 and an interface (not shown) between the electronic interlocking device and the outside. ). In the figure, reference numeral 7 denotes a bus for connecting the CPUs 1 and 2 to the system bus 9, and reference numeral 8 denotes a serial communication LSI for realizing serial communication with the outside.

FIG. 2 is a flowchart showing the contents of processing by a program executed by each CPU. In the figure, S1 and S2 constitute one machine cycle, and after the arithmetic processing in S1, in S2, the CPU
The results of the operations 1 and 2 are collated. As a result of the collation processing in S2, if the collation results match, the flow proceeds to S3, and the supply of the excitation signal to the mismatch detector 5 is continued. On the other hand, if the matching result does not match,
The flow proceeds to S9, in which the CPUs 1 and 2 output the mismatch detector 5
The supply of the excitation signal to is stopped.

Thereafter, as in S1 and S2, the arithmetic processing and the collation processing are repeatedly performed, and S2, S4, S6 and S8 are performed.
When all the comparison results match, the flow returns to S1, and the same operation is repeated to realize the function of the electronic interlocking device.

FIG. 3 shows a second embodiment according to the second embodiment of the present invention.
It is a figure which shows notionally the state of communication between CPU1 and CPU2 in a heavy electronic interlocking device. Also, FIG.
FIG. 4 is a flowchart showing the content of the matching process in S2 of the CPU 1 as a diagram showing the matching process in each CPU.

In FIG. 3, when the calculation processing in S1 is completed, the CPU 1 transmits a calculation result transmission request command to the CPU 2 via the serial communication line 3 in order to obtain the calculation result of the CPU 2. Similarly, the CPU 2 also executes S1
Is completed, the CPU transmits a calculation result transmission request command to the CPU 1 via the serial communication line 4 in order to obtain the calculation result of the CPU 1.

As a result, the CPU 1 transmits the calculation result of the CPU 1 in S1 to the CPU 2 as collation data.
The CPU 2 sends the calculation result of the CPU 2 in S1 to the CPU 1 as collation data. And CPU1,2
In each of the above, the comparison result of its own calculation with the calculation result of the other CPU is performed.

Next, the contents of a series of collation processing in the CPU 1 will be specifically described with reference to FIG. In FIG. 4, S
At 10, a timeout time t1 is set as a first communication time until the calculation result of the CPU 2 is received.
At this time t1, the CPU 1 issues a calculation result transmission request command to the CPU.
2, a time required for transmitting a calculation result transmission request command required for transmission to the second, a calculation processing time for performing the calculation processing, and a CP.
Based on the time required for U2 to transmit the calculation result to the CPU 1 and the required time for transmitting the calculation result, the time is set by adding a further spare time.

The CPU 1 transmits an operation result transmission request command to the CPU 2 (S11), and waits for reception of the operation result transmitted from the CPU 2 (S12). In S12, when the CPU 1 receives the calculation result of the CPU 2 within the time t1, the flow is S
Proceed to 13. In S13, the calculation result of CPU1 is CP
Sent to U2. Then, in the CPU 1, the self (CP)
A comparison process is performed between the calculation result of U1) and the calculation result of the other (CPU2) (S17).

If the collation results in S17 match, S
A series of collation processing (S10 to S17) of 2 is completed,
If the collation results do not match, the flow proceeds from S17 to S
Proceeding to 18, the supply of the excitation signal from the CPU 1 to the mismatch detector 5 is cut off.

At S12, the CPU 1 sets the time t.
If the calculation result of CPU 2 cannot be received within 1 and a calculation result transmission request command is received from CPU 2,
From 12 to 14, the calculation result of CPU1 is changed to CPU2.
(S14). After transmitting the calculation result to the CPU 2 in S14, a timeout time t1 until receiving the calculation result of the CPU 2 as the second communication time is set (S15).

The time t1 is the time required for the CPU 1 to transmit the calculation result transmission request command to the CPU 2, the time required to transmit the calculation result transmission request command, the calculation processing time for performing the calculation processing, and the CPU 2 Based on the required transmission time of the calculation result required for transmission to the CPU 1, it is set with a little extra time added. The timeout time t1 is the same as the time set in S10.

After setting the timeout time t1 in S15, the process waits for the CPU 2 to receive the calculation result (S16). S
In step 16, if the calculation result of the CPU 2 is received within the time t1, the flow proceeds to S17, where a comparison process between the two calculation results is performed (S17), while the calculation result of the CPU 2 can be received within the time t1. If not, the flow proceeds to S18, and the supply of the excitation signal to the mismatch detector 5 is cut off (S18).

The collation processing as described above is performed in steps S4 and S4.
6 and S8 are performed in the same manner. In this way, a complicated and large-scale circuit is used by connecting the two CPUs with a full-duplex serial communication line and performing collation processing for each arithmetic processing. Even if an abnormality occurs, the abnormality can be detected within a short period of time, and safety can be ensured when the electronic interlocking device is applied to an operation control device such as a railway.

Embodiment 2 FIG. 5 is a diagram conceptually showing a state of communication between CPU 1 and CPU 2 in the dual electronic interlocking device according to Embodiment 2 of the present invention.
FIG. 6 is a flowchart showing the content of the collation processing in the dual electronic interlocking device according to Embodiment 2 of the present invention. In the second embodiment, the configuration of the apparatus (corresponding to FIG. 1) and the processing contents (corresponding to FIG. 2) by the program executed by each CPU are similar to those of the first embodiment. The steps will be described with the same reference numerals.

As shown in FIG. 5, when the CPU 2 receives an operation result transmission request command from the CPU 1 during the operation in the operation result collation processing in the second embodiment, the CPU 1 waits for the operation result via the serial communication line 4. Command (wai
Send t). Thus, the CPU 2 issues the standby command to C
By transmitting to the PU1, the CPU 1 is notified that the arithmetic processing is being performed.

The CPU 1 having received the standby command is the CPU 2
And waits until a calculation result transmission request command is received. When the command is received, the calculation result is transmitted to the CPU 2. Subsequent processing is according to the second embodiment.

Therefore, the above-described processing will be described in detail with reference to the flowchart of FIG. 6. Steps S10 to S12 in the first embodiment are performed.
When 1 receives the standby command from the CPU 2, a timeout time t1 as a third communication time is set in S20. This timeout time t1 is the same as that in the first embodiment. Note that the time t1 as the third communication time is a waiting time from when the CPU 1 receives the standby command of the CPU 2 to when it receives the calculation result transmission request command of the CPU 2, but with a margin, Embodiment 1
Is set to the same time as the time t1.

When the time t1 is set as described above (S2
0), the CPU 1 waits for the CPU 2 to receive the calculation result transmission request command (S21). Then, within the time t1, the CPU
When 1 receives the calculation result transmission request command of the CPU 2, the flow proceeds to S14, and the calculation result of the CPU 1 is transmitted to the CPU 2 (S14). After that, the flow from S15 to S18 is performed in the same manner as in the first embodiment.

On the other hand, if the CPU 1 cannot receive the calculation result transmission request command of the CPU 2 within the time t1 in S21, the flow proceeds to S18, and the supply of the excitation signal to the mismatch detector 5 is cut off ( S18).

The collation processing described above is similarly performed after each arithmetic processing. In this way, the two CPUs are connected by a full-duplex serial communication line, and the collation processing is performed for each arithmetic processing. By doing so, it is possible to detect an abnormality within a short time even if an abnormality occurs without using a complicated and large-scale circuit, and to apply an electronic interlocking device to an operation control device such as a railway. Safety can be ensured. Further, by providing the standby command setting process, the processing accuracy can be further enhanced.

Embodiment 3 FIG. 7 is a flowchart showing the content of the collation processing in the dual electronic interlocking device according to Embodiment 3 of the present invention. In the figure, the collation processing and the device configuration are according to the second embodiment,
The set time in the step (S30 to be described later) corresponding to S10 (the first step of the collation processing) and the set time in the step (S31 to be described later) corresponding to S15 (the step after S14) in the second embodiment. Is different. The other steps having the same processing content are described with the same reference numerals as in the second embodiment (FIG. 6).

As shown in FIG. 7, in S30 and S31, a first operation for waiting until the result of the operation of the CPU 2 is received.
And the timeout time t2 as the second communication time. In this setting of t2, C
It is assumed that PU2 has completed the arithmetic processing. Accordingly, t2 is the transmission time of the calculation result required for the CPU 2 to transmit the calculation result to the CPU 1, and the transmission time of the calculation result transmission request command required for the CPU 1 to transmit the calculation result transmission request command to the CPU 2. It is set based on time and t2 <t1.

Further, the timeout time t2 is set as described above (S30). If the CPU 1 transmits a calculation result transmission request command to the CPU 2 in S11, if the CPU 2 is performing the calculation processing, the CPU 2 By transmitting a standby command (wait) to the CPU 1, the flow proceeds to S20, and the timeout time becomes t1 (S20). Therefore, the CPU 1 waits for the completion of the arithmetic processing of the CPU 2 and reception of the arithmetic result.

As described above, the timeout time t2 for the CPU 1 to wait for the CPU 2 to receive the calculation result is
Since the time required for the PU to perform the arithmetic processing is not taken into consideration, it can be determined in a shorter time whether or not the processing operation of each CPU is normally performed. In addition, such a matching process is similarly performed after each arithmetic process, and can secure safety when the electronic interlocking device is applied to a driving control device such as a railway. Further, by providing the standby command setting process, the processing accuracy can be further enhanced.

Embodiment 4 FIG. 8 is a flowchart showing the content of the collation processing of the dual electronic interlocking device according to Embodiment 4 of the present invention. In the figure, the collation processing and the device configuration are similar to those of the second and third embodiments, but the timeout time set in steps S40 and S41 corresponding to S30 and S31 of the third embodiment is t3 (≦ t2). The other steps having the same processing contents will be described with the same reference numerals as in the second and third embodiments (FIGS. 6 and 7).

As shown in FIG. 8, in S40 and S41, a first operation for waiting until the result of the operation of the CPU 2 is received.
And the timeout time t2 as the second communication time. In this setting of t3, C
It is assumed that PU2 has completed the arithmetic processing.

Further, at t3, the CPU 2 calculates the calculation result as CP
The time required to transmit the operation result required to transmit to U1,
It is set based on the average time in the past predetermined number of times and the required transmission time of the calculation result transmission request command required for the CPU 1 to transmit the calculation result transmission request command to the CPU 2, and t3 ≦ t2.

As described above, the timeout time t3 for the CPU 1 to wait for the result of the calculation by the CPU 2 is
The time required for the PU to perform the arithmetic processing is not taken into consideration, and further, in order to set the optimal time based on the average time in the past predetermined number of times, it is necessary to determine whether the processing operation of each CPU is normally performed. It can be judged in a short time.

Further, such collation processing is similarly performed after each arithmetic processing, and security can be ensured when the electronic interlocking device is applied to an operation control device such as a railway. In addition, by providing the standby command setting process, the processing accuracy can be made higher.

Embodiment 5 FIG. FIG. 9 is a diagram conceptually showing a state of communication between CPU 1 and CPU 2 in the dual electronic interlocking device according to Embodiment 5 of the present invention.
FIG. 10 is a flowchart showing the content of the collation processing in the dual electronic interlocking device according to Embodiment 5 of the present invention. In FIG. 10, the steps having the same contents in the first embodiment are denoted by the same reference numerals, and the description thereof will be made. The device configuration and the like are all the same as in the first embodiment.

In FIG. 9, the processing for transmitting and receiving the operation result transmission request command between CPUs 1 and 2 and exchanging the operation result are the same as those in the first embodiment, but a match is first obtained in the operation result collation processing. The other sends a collation processing end signal to the other CPU.

Such processing is performed in steps S50 and S50 in FIG.
When the CPU 1 receives the calculation result of the CPU 2 in S16, it transmits a collation processing end signal to the CPU 2 (S50), and waits for a collation processing end signal to be transmitted from the CPU 2 (S51). ).

Further, as shown in FIG.
In steps S12, S16, S17, S50, and S51, if a communication error such as a transmission / reception failure, a timeout due to the expiration of the waiting time, or a mismatch in the collation results, the flow returns to S10. (Returns to A in the figure). When such a return of the flow occurs three or more times in succession in the same step, the flow proceeds to S18, that is, the return is over at the third time, and the supply of the excitation signal from the CPU 1 to the mismatch detector 5 is cut off. It is.

The collation processing as described above is similarly performed in S4, S6 and S8 shown in FIG. 2. In this way, the two CPUs are connected by a full-duplex serial communication line, and each operation is performed. By performing the matching process for each process, it is possible to detect the abnormality within a short time even if an abnormality occurs without using a complicated and large-scale circuit. Safety when applied to the device can be ensured.

Further, a timeout, a communication error,
Alternatively, when the matching result does not match, the flow is returned to the first step of the matching process, and the flow is terminated when the matching process returns more than a predetermined number of times. Processing can be performed, and safety in application of the device can be improved.

Embodiment 6 FIG. FIG. 11 is a diagram conceptually showing a state of communication between CPU 1 and CPU 2 in the dual electronic interlocking device according to Embodiment 6 of the present invention. FIG. 12 is a flowchart showing the content of the collation processing in the dual electronic interlocking device according to Embodiment 6 of the present invention. In FIG. 12, steps having the same contents in the second embodiment are denoted by the same reference numerals, and the description thereof will be made. The device configuration and the like all conform to the second embodiment.

In FIG. 11, the processing of transmitting and receiving the operation result transmission request command between CPUs 1 and 2 and the processing of exchanging the operation result are the same as those in the second embodiment. The other sends a collation processing end signal to the other CPU.

Such processing is performed in steps S50 and S50 in FIG.
When the CPU 1 receives the calculation result of the CPU 2 in S16, it transmits a collation processing end signal to the CPU 2 (S50), and waits for a collation processing end signal to be transmitted from the CPU 2 (S51). ).

Further, as shown in FIG.
In steps S12, S16, S17, S21, S50, and S51, if a communication error such as a transmission / reception failure, a timeout due to the expiration of the waiting time, or a mismatch in the collation results, the flow returns to step S10. (Return to A in the figure). When such a return of the flow occurs three or more times consecutively in the same step, the flow proceeds to S18, that is, the return is over at the third time, and the CPU returns to step S18.
The supply of the excitation signal from 1 to the mismatch detector 5 is cut off.

The collation processing described above is similarly performed after each arithmetic processing. In this way, the two CPUs are connected by a full-duplex serial communication line, and the collation processing is performed for each arithmetic processing. By doing so, it is possible to detect an abnormality within a short time even if an abnormality occurs without using a complicated and large-scale circuit, and to apply an electronic interlocking device to an operation control device such as a railway. Safety can be ensured. Further, by providing the standby command setting process, the processing accuracy can be further enhanced.

Further, a timeout, a communication error,
Alternatively, when the matching result does not match, the flow is returned to the first step of the matching process, and the flow is terminated when the matching process returns more than a predetermined number of times. Processing can be performed, and safety in application of the device can be improved.

Embodiment 7 FIG. FIG. 13 is a flowchart showing the content of the collation processing in the dual electronic interlocking device according to Embodiment 7 of the present invention. In the figure, the collation processing and the device configuration are according to the sixth embodiment.
The set time in step (S30) corresponding to S10 of the sixth embodiment and the step (S3
The set time in 1) is the timeout time t2 described in the third embodiment.

The collation processing set in this manner is performed similarly after each arithmetic processing as in all the above-described embodiments, and thus the full-duplex serial communication between the two CPUs is performed. By connecting via a line and performing the matching process for each operation process, it is possible to detect an abnormality within a short time even if an abnormality occurs without using a complicated and large-scale circuit. Can be ensured when the system is applied to an operation control device such as a railway. Further, by providing the standby command setting process, the processing accuracy can be further enhanced.

When a time-out, a communication error, or a mismatch in the collation result occurs, the flow is returned to the first step of the collation process. If the flow returns more than a predetermined number of times, the flow is terminated. , It is possible to perform a more accurate collation process, and it is possible to improve safety in application of the device.

Further, the timeout time t2 for the CPU 1 to wait for the reception of the calculation result of the CPU 2
Since the time required for the U to perform the arithmetic processing is not considered, it can be determined in a shorter time whether or not the processing operation of each CPU is normally performed. In addition, such a matching process is similarly performed after each arithmetic process, and can secure safety when the electronic interlocking device is applied to a driving control device such as a railway. Also,
By providing the setting process of the standby command, the processing accuracy can be made higher.

Embodiment 8 FIG. FIG. 14 is a flowchart showing the content of the collation processing in the dual electronic interlocking device according to Embodiment 8 of the present invention. In the figure, the collation processing and the device configuration are according to the sixth embodiment.
The set time in step (S40) corresponding to S10 of the sixth embodiment and the step (S4) corresponding to S15
The set time in 1) is the timeout time t3 described in the fourth embodiment.

The collation processing set in this manner is performed in the same manner after each arithmetic processing as in all the above-described embodiments, and thus the full-duplex serial communication between the two CPUs is performed. By connecting via a line and performing the matching process for each operation process, it is possible to detect an abnormality within a short time even if an abnormality occurs without using a complicated and large-scale circuit. Can be ensured when the system is applied to an operation control device such as a railway. Further, by providing the standby command setting process, the processing accuracy can be further enhanced.

When a time-out, a communication error, or a mismatch in the collation result occurs, the flow is returned to the first step of the collation processing. If the flow returns more than a predetermined number of times, the flow is terminated. , It is possible to perform a more accurate collation process, and it is possible to improve safety in application of the device.

A timeout time t3 (t3 ≦ t) set based on the average time in the past predetermined number of times.
By applying 2), it is possible to determine in a shorter time whether or not the processing operation of each CPU is normally performed based on the optimum time based on the average time in the past predetermined number of times.

Embodiment 9 FIG. FIG. 15 is a block diagram of a dual electronic interlocking device according to Embodiment 9 of the present invention.
It is a figure which represents the communication content between between schematically. In the figure, C
The calculation result transmission request command 90, the calculation result 91, the standby command 92, and the collation processing end signal 93, which are the communication contents between the PU 1 and the CPU 2, include a generation number 95 and a processing number 96 as data indicating the current processing stage. Has been added.

The generation number 95 indicates the number of repetitions of S1 to S8 shown in FIG. 2. When a series of processing from S1 to S8 is completed, the numerical value increases by one. The processing number 96 indicates a unique number given to S1 to S8.

Such a generation number 95 and a processing number 9
When 6 is added to the communication contents between the CPU 1 and the CPU 2, for example, in S12 of the first to eighth embodiments, not only the operation contents of the operation result 92 but also the generation number 95 and the processing number 96 are collated. .

As described above, by comparing the generation number 95 and the processing number 96, the calculation results of the CPU 1 and the CPU 2 in the same processing stage can be compared. Can be effectively suppressed.
At the same time, the accuracy in each process can be made higher.

[0076]

According to the dual electronic interlocking device of the present invention, the first and second arithmetic processing means for performing the same arithmetic processing based on the same input information, and the arithmetic operation by each arithmetic processing means. Calculation result exchange means for mutually exchanging results based on a calculation result transmission request command; and a calculation result of each calculation processing means and a calculation result of the other calculation processing means received via the calculation result exchange means. And a collation result confirming means for confirming the collation result of the first and second means, when it is determined that a mismatch has occurred in the collation results of at least one of the arithmetic processing means among the arithmetic processing means. And a shutoff means for shutting off the external device, so that a collation process can be performed for each arithmetic process, and a different process can be performed without using a complicated and large-scale circuit. Can be detected within a short period of time even in the event of an occurrence, safety can be ensured when the electronic interlocking device is applied to operation control devices such as railways, and the synchronization function in the arithmetic processing can be ensured. Since it becomes unnecessary, the apparatus can be reduced in size and simplified, and the number of development steps can be reduced.

Each of the arithmetic processing means includes a first communication time for transmitting an operation result transmission request command via the operation result exchange means and then waiting for reception of the operation result; Setting a second communication time for transmitting the operation result to the other operation processing unit and then waiting for the other operation processing unit to receive the operation result when the operation result transmission request command is received. Because of the features, it is possible to improve the processing accuracy of the calculation result, and it is possible to secure high security in applying the device.

Further, each of the arithmetic processing means sets a third communication time for waiting for reception of a calculation result transmission request command after receiving a standby command during the first communication time. Therefore, by returning a standby command in response to the reception of the collation data request during the arithmetic processing, it is possible to improve the processing accuracy by notifying that the CPU is operating even during the processing. In addition, since high security can be ensured in the application of the device and the timeout period can be extended, it is possible to wait for the reception of the calculation result to be completed.

Further, the first communication time and the second communication time are based on an arithmetic processing time for performing arithmetic processing, a transmission time of an arithmetic result transmission request command, and a transmission time of an arithmetic result. It is characterized by being set
The processing accuracy of the calculation result can be further improved, and high security can be ensured in applying the device.

Further, the first communication time and the second communication time are set based on the required time for transmitting the calculation result and the required time for transmitting the calculation result transmission request command. The processing accuracy of the calculation result can be further improved, and high security can be ensured in applying the device.

Further, the first communication time and the second communication time are based on an average required time of a predetermined number of past times of a required transmission time of the calculation result and a required transmission time of the calculation result transmission request command. Since it is set, the processing accuracy of the calculation result can be further improved, and high security can be secured in applying the device.

The third communication time is set based on an arithmetic processing time for performing an arithmetic processing, a required transmission time of an arithmetic result, and a required transmission time of an arithmetic result transmission request command. Because of the feature, it is possible to further improve the processing accuracy of the calculation result, and it is possible to secure high security in applying the device.

Further, each of the arithmetic processing means transmits a collation processing end signal to the other arithmetic processing means when the collation results of the respective arithmetic results match each other. High security can be ensured.

If the first arithmetic processing means or the second arithmetic processing means does not establish communication with the other arithmetic processing means a predetermined number of times or more, the first arithmetic processing means or the second arithmetic processing means activates the interrupting means to activate the first and second arithmetic processing means. It is characterized by shutting off the arithmetic processing means and the external device, so by repeating the collation processing, it is possible to reduce the probability of system stoppage due to a temporary failure or the like, extend the continuous operation time, and The processing accuracy of the result can be further improved, and high security can be ensured in applying the device.

Further, the present invention is characterized in that data indicating the current processing stage is added to the communication contents exchanged between the first and second processing units via the processing result exchange unit. It is possible to detect an abnormality of the apparatus such as a deviation, and suppress collation of data in processing steps that are far apart from each other, thereby improving collation accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a main configuration of a dual electronic interlocking device according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart showing processing contents of the dual electronic interlocking device according to the first embodiment of the present invention.

FIG. 3 is a diagram schematically showing a state of communication between CPUs of the dual electronic interlocking device according to Embodiment 1 of the present invention;

FIG. 4 is a flowchart showing the content of a collation process of the dual electronic interlocking device according to the first embodiment of the present invention.

FIG. 5 is a diagram schematically showing a state of communication between CPUs of a dual electronic interlocking device according to Embodiment 2 of the present invention;

FIG. 6 is a flowchart illustrating the content of a collation process performed by the dual electronic interlocking device according to the second embodiment of the present invention.

FIG. 7 is a flowchart of a collation process of the dual electronic interlocking device according to Embodiment 3 of the present invention.

FIG. 8 is a flowchart of a collation process of the dual electronic interlocking device according to Embodiment 4 of the present invention.

FIG. 9 is a diagram schematically showing a state of communication between CPUs of a dual electronic interlocking device according to Embodiment 5 of the present invention.

FIG. 10 is a flowchart illustrating the content of a collation process performed by a dual electronic interlocking device according to Embodiment 5 of the present invention;

FIG. 11 is a diagram schematically showing a state of communication between CPUs of a dual electronic interlocking device according to Embodiment 6 of the present invention.

FIG. 12 is a flowchart illustrating the content of a collation process performed by the dual electronic interlocking device according to Embodiment 6 of the present invention;

FIG. 13 is a flowchart showing the content of the collation processing of the dual electronic interlocking device according to Embodiment 7 of the present invention.

FIG. 14 is a flowchart showing the content of the collation processing of the dual electronic interlocking device according to Embodiment 8 of the present invention.

FIG. 15 is a diagram schematically showing communication contents between CPUs of a dual electronic interlocking device according to Embodiment 9 of the present invention.

FIG. 16 is a configuration diagram of a conventional dual-system electronic interlocking device.

[Explanation of symbols]

1 CPU (first operation means), 2 CPU (second operation means), 3, 4 serial communication line (operation result exchange means), 5 mismatch detector (verification result confirmation means), 6 relay (interruption means) .

Claims (10)

[Claims] 1. A first arithmetic processing means and a second arithmetic processing means for performing the same arithmetic processing based on the same input information; and calculating the arithmetic results of the arithmetic processing means based on an arithmetic result transmission request command. Calculation result exchanging means for mutually exchanging, and a collation result for confirming a collation result of each of the arithmetic processing results in each of the arithmetic processing means and the operation result of the other arithmetic processing means received via the arithmetic result exchanging means Confirming means, when the collation result confirming means determines that a mismatch has occurred in the collation results of at least one of the arithmetic processing means, the first and second arithmetic processing means A double electronic interlocking device comprising: a shutoff unit for shutting off an external device. 2. The method according to claim 1, wherein each of the arithmetic processing units includes a first communication time for transmitting the operation result transmission request command via the operation result exchange unit and then waiting for reception of the operation result; When a calculation result transmission request command is received during the communication time, a second communication time for transmitting the calculation result to the other calculation processing means and then waiting for reception of the calculation result by the other calculation processing means is set. 2. The dual electronic interlocking device according to claim 1, wherein: 3. The method according to claim 1, wherein each of the arithmetic processing units sets a third communication time for waiting for reception of an operation result transmission request instruction after receiving a standby instruction during the first communication time. 3. The dual electronic interlocking measure according to claim 2. 4. The first communication time and the second communication time are based on an arithmetic processing time for performing an arithmetic processing, a transmission time of an arithmetic result transmission request command, and a transmission time of an arithmetic result. 4. The dual electronic interlocking device according to claim 2, wherein the dual electronic interlocking device is set. 5. The communication method according to claim 1, wherein the first communication time and the second communication time are set based on a required time for transmitting a calculation result and a required time for transmitting a calculation result transmission request command. The dual electronic interlocking device according to claim 2 or 3. 6. The first communication time and the second communication time are based on an average required time in a predetermined number of past times of a required transmission time of a calculation result and a required transmission time of a calculation result transmission request command. 3. The method according to claim 2, wherein the setting is performed.
Or the dual electronic interlocking device according to claim 3. 7. The method according to claim 1, wherein the third communication time is set based on a calculation processing time for performing a calculation process, a transmission time of a calculation result, and a transmission time of a calculation result transmission request command. The dual electronic interlocking device according to any one of claims 2 to 6, wherein: 8. The method according to claim 1, wherein each of the arithmetic processing means transmits a collation processing end signal to the other arithmetic processing means when the collation results of the respective arithmetic results match. The dual electronic interlocking device according to any one of the above. 9. When the first arithmetic processing means or the second arithmetic processing means does not establish communication with the other arithmetic processing means a predetermined number of times or more, the first arithmetic processing means or the second arithmetic processing means activates the cutoff means to activate the first and second arithmetic processing means. 9. The dual electronic interlocking device according to claim 2, wherein the arithmetic processing means is shut off from an external device. 10. The communication contents exchanged between the first and second arithmetic processing means via the arithmetic result exchanging means, and data indicating a current processing stage is added to the communication contents. Item 10. A dual-system electronic interlocking device according to any one of Items 9.