JPH114392A - Multi-channel display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a synchronizing signal whose phase is corrected for controlling a field memory by measuring and storing a synchronization period and a synchronization phase for each channel based on clock data from a standard clock section and predicting the synchronization phase of a newly selected channel based on the stored data. SOLUTION: A horizontal phase measurement section 11a measures a synchronization phase of a horizontal synchronizing signal for each channel based on clock data generated by a standard clock section 11h and measures and outputs horizontal phase data. A horizontal period measurement section 11b measures and outputs horizontal period data and a vertical phase measurement section 11c measures and outputs vertical phase data. The data are tentatively stored for each reception channel to memories 11d-11f. When a new channel is selected, a vertical correction arithmetic unit 12a adds a product between elapsed time data up to now and the horizontal period data to preceding vertical phase data to calculate and output the vertical correction data as a predicted vertical phase at a current point of time. A horizontal correction arithmetic unit 12e calculates and outputs the horizontal correction data at a current point of time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to generation of a sampling clock for image control and a synchronizing signal in a display device which receives a plurality of channels and performs multi-channel display.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional multi-channel display device includes a TV tuner 1 for receiving a large number of broadcast channels and demodulating an analog video signal.
A YC separation unit 5 for separating the analog video signal into a luminance signal and a chromaticity signal;
An RGB demodulation unit 6 for demodulating the B signal; an A / D 7 for converting the RGB signal into digital image data; a synchronization separation unit 2 for separating and outputting horizontal and vertical synchronization signals from the analog video signal; Synchronized horizontal pulse,
P for generating vertical pulse, sampling clock, etc.
An LL circuit 3, a field memory 8 for storing the digital image data in units of fields and dividing and storing image data of a plurality of channels, and controlling the field memory to display images of a plurality of reception channels on a multi-screen. It comprises an image control unit 4, a control unit for controlling the tuner, the image control unit and the like. The control unit 9 sequentially selects twenty or more broadcast channels, and issues a command to write image data for each channel into the field memory. The PLL circuit 3 generates a sampling clock, a horizontal pulse, and a vertical pulse synchronized with the synchronization signal synchronized and separated by the synchronization separation unit 2 each time a new channel is selected because the synchronization cycle and the synchronization phase are different for each channel. I do.
The image control unit 4 generates a write timing signal of an image to be written in the field memory 8 based on the generated horizontal pulse and vertical pulse, and inputs the signal to the field memory. The phase of the synchronization signal for each broadcast channel is shown in FIG.
As shown in (a), the phase difference is less than one vertical period, and the synchronization cycle is slightly different, and the synchronization phase difference of each channel is not constant but changes. The image control unit 4 controls to write image data during a period from the vertical pulse t2 immediately after the channel selection to the second vertical pulse t3.
Therefore, the image data during the period from t1 to t2 becomes invalid,
The invalid period reaches a maximum of about one vertical period. as a result,
It takes time to select and search many channels,
Slow the movement of the multi display screen. In order to solve this, there is a need for a means for hastening the phase synchronization of the image data acquisition synchronization signal when switching channels.

[0003]

In view of this problem, although there is a phase difference between the synchronization signals for each channel, attention is paid to the fact that the periodic error is on the order of 10 −5.
The synchronization period and synchronization phase of each channel are measured and stored as clock data of the standard clock section, and the stored data is used to predict and calculate the synchronization phase of the newly selected channel, and to correct the phase for field memory control. The purpose is to generate a synchronization signal.

[0004]

As shown in FIG. 1, a TV tuner that receives a plurality of broadcast channels and outputs an analog video signal, an A / D that converts the video signal into digital image data, A field memory that stores digital image data in units of fields and divides and stores a plurality of channels of image data; a synchronization separation unit that separates a synchronization signal from the analog video signal; a horizontal pulse and a vertical pulse synchronized with the synchronization signal , A PLL circuit that generates a sampling clock and the like, an image control unit that controls the field memory to display a plurality of reception channel images on a multi-screen, and a control unit that controls the TV tuner, the image control unit, and the like. In the multi-channel display device, the synchronization phase of the synchronization-separated synchronization signals of the plurality of channels is A synchronization phase measuring unit having means for measuring a period cycle and a means for storing the measurement result together with a reception channel; and a synchronization phase of a newly switched channel based on the stored synchronization phase data and synchronization cycle data for each reception channel. Predictive calculation, the vertical pulse,
A synchronous phase corrector for correcting the phase of a horizontal pulse or the like is added.

Further, the synchronization measuring section measures a cycle of a horizontal synchronization signal to generate horizontal cycle data, a horizontal cycle memory for temporarily storing the horizontal cycle data for each channel, and a vertical synchronization memory. A vertical phase measurement unit that measures the phase of a signal to generate vertical phase data, a vertical cycle memory that temporarily stores the vertical cycle data for each channel, the horizontal cycle measurement, a vertical synchronization phase, and a synchronization phase correction operation. And a standard clock section for generating reference time data.

Further, an order calculator for sequentially calculating the channel having the closest phase from the vertical synchronization phase data for each channel and storing the channel order data is additionally provided in the synchronization measuring section.

Further, the synchronous phase correction unit calculates vertical phase data, horizontal cycle data, and elapsed time data from the previous channel selection when selecting a new channel, and calculates and outputs vertical correction data. Arithmetic unit and PLL
A horizontal counter for counting the output horizontal pulses from the circuit,
A vertical pulse generator that generates a vertical pulse when the count number of the horizontal counter reaches a predetermined number and resets the horizontal counter.

Further, the synchronous phase measuring section measures a phase of a horizontal synchronous signal to generate horizontal phase data, a horizontal phase memory for temporarily storing horizontal phase data for each channel, and a synchronous phase memory. The correction unit calculates the horizontal correction data for correcting the horizontal phase from the horizontal phase data and the horizontal cycle data, and shifts the output phase of the M / N counter of the PLL circuit based on the horizontal correction data. Additional phase shifters to be installed.

Further, clock data generated by the standard clock section is used as a reference clock for reading image data from a field memory and a synchronization signal. Further, the clock data generated by the standard clock section is a reference clock and a synchronization signal synchronized with the received synchronization signal of the specific channel.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A synchronous phase measuring section measures and stores a synchronous cycle and a synchronous phase of a synchronous signal for each channel based on clock data generated by a standard clock section. The synchronization phase correction unit predicts and calculates the synchronization phase of the newly selected channel based on the stored data, and generates a phase-corrected field memory control synchronization signal.

Further, based on the vertical synchronization phase data for each channel, the channel having the closest phase is calculated in order, the channel order data is stored, and the receiving channel is selected in the order of the channel order data.

Further, the synchronization period and the synchronization phase of the horizontal synchronization signal for each channel are measured and stored, and the horizontal synchronization phase of the newly selected channel is predicted and calculated based on the stored data, and the horizontal correction data is calculated and output. Then, the phase of the phase shifter is corrected based on the horizontal correction data.

The clock data generated by the standard clock section is
A reference clock and a synchronization signal for reading image data from the field memory, or a reference clock and a synchronization signal synchronized with the received synchronization signal of the specific channel.

[0014]

FIG. 1 is a block diagram of a main part of an embodiment according to the present invention, and FIG. 2 is a block diagram of a main part of another embodiment. In FIG. 1, 1, 2, 3, 4, 5, 6, 7, 8, and 9 are:
The function is the same as that of the description of the related art, and the description is omitted.
Reference numeral 11 denotes a synchronization phase measurement unit having means for measuring the synchronization phase and synchronization cycle of the synchronization-separated synchronization signals of a plurality of channels, and means for storing the measurement result together with the reception channel. Reference numeral 12 denotes a synchronization phase for each stored reception channel. A synchronous phase corrector for predicting and calculating a synchronous phase of a newly switched channel based on data and cycle data, and correcting a phase of the vertical pulse, the horizontal pulse, and the like.

In FIG. 2, 3a compares the phase of a horizontal synchronization signal of a received image with the phase of a horizontal pulse generated inside the apparatus.
A phase comparator for outputting an error signal, a filter 3b for filtering the error signal, a frequency control for the error signal 3c, a VCO for oscillating and outputting a sampling clock for image data, and a VCO 3d for outputting a sampling clock for image data.
Is an M / N counter that divides the oscillation frequency of and generates a horizontal pulse. 11a measures the synchronization phase of the horizontal synchronization signal as the deviation time from the internal reference phase, and outputs a horizontal phase data. The horizontal phase measurement unit 11b measures the synchronization cycle of the horizontal synchronization signal and outputs horizontal cycle data. A period measurement unit, 11c measures a synchronization phase of a vertical synchronization signal as a deviation time from an internal reference phase, and outputs a vertical phase data. A vertical phase measurement unit measures, and 11d denotes a horizontal phase that temporarily stores horizontal phase data for each channel. A memory, 11e is a horizontal cycle memory for temporarily storing horizontal cycle data for each channel, 11f is a vertical phase memory for temporarily storing vertical data for each channel, and 11g is for calculating channel numbers in ascending order of the difference between the vertical phase data. An order calculator for calculating and outputting tuning data for selecting a receiving channel in the order; It is a standard clock unit to generate.

Reference numeral 12a denotes a vertical correction calculator for calculating vertical phase data, horizontal cycle data, and elapsed time data from the previous channel selection to calculate and output vertical correction data when a new channel is selected, and 12b denotes a PLL circuit. The horizontal counter 12c counts the output horizontal pulse, and a vertical pulse generator 12c generates a vertical pulse when the count number of the horizontal counter reaches a predetermined number, and resets the horizontal counter. The phase shifter 12e shifts the output phase of the M / N counter of the PLL circuit based on the horizontal phase data and the horizontal cycle data.
A horizontal correction calculator for calculating and outputting horizontal correction data.

The embodiment of the present invention is constituted as described above. The detailed operation will be described by adding the vertical synchronization of the image and the image writing timing chart of FIGS. In the prior art, the start of image data capture is counted from the write end timing t1 of one channel, as shown in FIG.
It is the first vertical synchronization position t2, and is in a standby state from t1 to t2. Hereinafter, from t3 to t4,..., Tn-1 to tn is in a standby state. The image writing timing in the vertical direction is controlled by the image controller 4 so that the horizontal pulse is counted from the vertical pulse as a starting point and the writing of the image data is started when the horizontal pulse reaches a certain value. Not generated. The embodiment of the present invention is configured as described above. The detailed operation will be described by adding the vertical synchronization of the image and the image writing timing chart of FIGS. In the prior art, as shown in FIG. 4A, the start of image data acquisition is the first vertical synchronization position t2 counted from the write end timing t1 of one channel, and the standby state is established from t1 to t2. , From t3 to t4,..., Tn-1 to tn are in the standby state. The vertical image writing timing is
The image control unit 4 counts horizontal pulses starting from a vertical pulse and starts writing image data when the count reaches a certain value.
Control, while no vertical pulse is generated during this time.

In the embodiment according to the present invention, the horizontal phase measuring unit 1
1a measures the synchronization phase of the horizontal synchronization signal for each channel based on the clock data generated by the standard clock unit 11h, and measures and outputs the horizontal phase data. The horizontal cycle measuring unit 11b similarly measures and outputs horizontal cycle data, and outputs the vertical phase measuring unit 11c.
Measures and outputs vertical phase data. The horizontal phase data, the horizontal cycle data and the vertical phase data are temporarily stored in the horizontal phase memory 11d, the horizontal cycle memory 11e and the vertical phase memory 11f for each receiving channel, and these stored data are updated as needed. Further, the order calculation unit 1
1g calculates the order of the channel having the closest synchronization phase from the vertical synchronization phase data of each channel, stores the channel order data, and
As shown in FIG. 4B, selection control of a new channel is performed in the order of the closest vertical synchronization phase. When a new channel is selected at t2, the vertical correction calculator 12a
Data obtained by multiplying the n-channel vertical phase data by the elapsed time data up to the current time and the horizontal cycle data is added, and the vertical correction data is calculated and output as the current predicted vertical phase. On the other hand, the horizontal counter 12b counts the horizontal pulses from the PLL circuit 3, and outputs a vertical pulse when the count reaches a certain value, and clears the horizontal counter. The signal is also cleared by the vertical synchronization signal from the synchronization separation unit 2. The vertical correction data is input from the data load terminal of the horizontal counter 12b, and replaces the current count value of the horizontal counter with the vertical correction data. As a result, the output of the horizontal counter is set to the vertical phase of the image data immediately after the switching.
As shown in (b), image data can be written immediately.

Further, in order to shorten the pull-in time of the PLL circuit 3, the horizontal correction calculator 12e calculates the horizontal position data, the horizontal cycle data and the elapsed time data and performs the current horizontal correction. Compute and output data. The PLL circuit 3 keeps a synchronized state on the periodic surface because the deviation of the horizontal period of each receiving channel is very small, and is in a state where only the phases do not match. Therefore, a phase shifter 12d is provided to input a horizontal pulse phase-shifted by the horizontal correction data to the phase comparison unit 3a and output the horizontal pulse as a horizontal pulse.

FIG. 5 shows the clock data of the standard clock section 11h as a reference clock and a synchronization signal for reading image data from a field memory or a reference clock and a synchronization signal synchronized with a received synchronization signal of a specific channel. It was done.

[0021]

The present invention is implemented as described above, and exhibits the following effects. The synchronization phase measurement unit measures and stores the synchronization cycle and synchronization phase of the synchronization signal for each channel based on clock data generated by the standard clock unit, and synchronizes the newly selected channel based on the stored data. The phase was predicted and calculated, and a phase-corrected synchronization signal for field memory control was generated. Further, it is possible to select a receiving channel in the order of closest phase from the vertical synchronization phase data for each channel. Further, the clock data generated by the standard clock section can be a reference clock and a synchronization signal for reading image data from the field memory, or a reference clock and a synchronization signal synchronized with the received synchronization signal of the specific channel. .

[Brief description of the drawings]

FIG. 1 is a main part block diagram of one embodiment according to the present invention.

FIG. 2 is a main part block diagram of another embodiment according to the present invention.

FIG. 3 is a main part block diagram according to a conventional technique.

FIG. 4 is a timing chart of vertical synchronization and image capture of an image according to the prior art and an embodiment of the present invention.

FIG. 5 is a timing chart of image vertical synchronization and image capture according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 TV tuner 2 Synchronization separation part 3 PLL circuit 3a Phase comparison part 3b Filter 3c VCO 3d M / N counter 4 Image control part 5 YC separation part 8 Field memory 9 Control part 11 Synchronization phase measurement part 11a Horizontal phase measurement part 11b Horizontal period Measurement unit 11c Vertical phase measurement unit 11d Horizontal phase memory 11e Horizontal cycle memory 11f Vertical phase memory 11g Permutation calculator 11h Standard clock unit 12 Synchronous phase correction unit 12a Vertical correction calculation unit 12b Horizontal counter 12c Vertical pulse generation unit 12d Phase shifter 12e Horizontal Correction calculator

Claims (7)

[Claims] 1. A TV tuner that receives a plurality of broadcast channels and outputs an analog video signal, an A / D (analog / digital converter) that converts the video signal into digital image data, and converts the digital image data into fields. And a field memory for dividing and storing image data of a plurality of channels, a synchronization separation unit for separating a synchronization signal from the analog video signal, and a horizontal pulse, a vertical pulse, a sampling clock, and the like synchronized with the synchronization signal. A multi-channel including a PLL circuit to generate, an image control unit for controlling the field memory to display images of a plurality of reception channels on a multi-screen, the TV tuner, and a control unit for controlling an image control unit and the like In the display device, the synchronization signals of the plurality of synchronization-separated channels are A synchronization phase measurement unit having means for measuring a synchronization phase and a synchronization cycle, and means for storing the measurement result together with a reception channel; and a newly switched channel based on the stored synchronization phase data and synchronization cycle data for each reception channel. A synchronous phase corrector for predicting and calculating the synchronous phase of the vertical pulse, the horizontal pulse, etc., and measuring and storing a synchronous cycle and a synchronous phase for each channel; and storing the stored synchronous cycle. A multi-channel display device comprising: predicting and calculating a synchronization phase of a newly selected channel from data and synchronization phase data to generate a phase-corrected synchronization signal for field memory control. 2. A horizontal cycle measuring section for measuring a synchronization cycle of a horizontal synchronization signal to generate horizontal cycle data; a horizontal cycle memory for temporarily storing the horizontal cycle data for each channel; A vertical phase measurement unit that measures a synchronization phase of a synchronization signal and generates vertical phase data; a vertical cycle memory that temporarily stores the vertical cycle data for each channel; and a horizontal cycle measurement, a vertical synchronization phase measurement, and a synchronization phase. 2. The multi-channel display device according to claim 1, wherein the multi-channel display device comprises a standard clock unit for generating reference time data such as a correction operation. 3. An order calculator for sequentially calculating a channel having the closest vertical synchronization phase from the vertical synchronization phase data for each channel and storing channel order data in the synchronization phase measuring section, 3. The multi-channel display device according to claim 2, wherein the reception channels are selected according to the order of the order data. 4. The synchronization phase correction section multiplies the vertical phase data, the horizontal cycle data, and the elapsed time data from the previous channel selection to calculate and output vertical correction data when selecting a new channel. A vertical correction calculator, a horizontal counter for counting horizontal pulses output from the PLL circuit, and a vertical pulse generator for generating a vertical pulse when the count of the horizontal counter reaches a predetermined number and resetting the horizontal counter. 2. The multi-channel display device according to claim 1, wherein the multi-channel display device comprises: 5. A horizontal phase measuring unit for measuring a phase of a horizontal synchronizing signal and generating horizontal phase data in the synchronous phase measuring unit, a horizontal phase memory for temporarily storing the horizontal phase data for each channel, A correction unit configured to calculate horizontal correction data for correcting a horizontal phase from the horizontal phase data and the horizontal cycle data; and an M / N (frequency division) of the PLL circuit based on the horizontal correction data. A phase shifter for shifting the output phase of the counter is additionally installed, the synchronization cycle and the synchronization phase of the horizontal synchronization signal for each channel are measured and stored, and a new selection is made based on the stored synchronization cycle data and synchronization phase data. Predicting and calculating the horizontal synchronization phase of the channel that was stationed, calculating and outputting the horizontal correction data,
2. The multi-channel display device according to claim 1, wherein the phase of the phase shifter is corrected by the horizontal correction data. 6. The clock data generated by the standard clock section is:
3. The multi-channel display device according to claim 2, wherein a reference clock and a synchronization signal for reading image data from the field memory are used. 7. Clock data generated by the standard clock unit is:
The multi-channel display device according to claim 2, wherein a reference clock and a synchronization signal synchronized with the received synchronization signal of the specific channel are used.