JPH1140676A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid causing defects due to residues of resist or etching at forming antifuses by planarizing an antifuse element between wiring layers which constitute a lower conductor layer having an insulator to form the insulator. SOLUTION: The manufacturing method comprises forming a first metal wiring layer 2 composed of a lower conductor layer 2a and connection wiring layer 2b on the entire insulation film 1, depositing an Si oxide film 3a, forming an SOG film 3b on the film 3a to fill up recesses of this film 3a, etching back to planarize and expose the wiring layer 2, depositing an Si oxide film 3c to cover the conductor layer 2a, wiring 2b and films 3a, 3b, forming openings through the oxide film 3c to expose the layer 2a of an antifuse element, and depositing an insulation film 4a and metal layer 4b on the entire surface to form an insulator 4 of the antifuse element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a technology effective when applied to a semiconductor device having an anti-fuse element.

[0002]

2. Description of the Related Art A logic circuit for controlling a system is different for each system to be used. Therefore, a new type of semiconductor device is required for each system. For this reason, it is necessary to increase the number of varieties to produce many varieties little by little. On the other hand, if the logic circuit is designed as a dedicated semiconductor device as it is, the semiconductor device itself will be developed in addition to developing a program to write. Will be developed,
It requires a lot of cost and time, and its development is a heavy burden.

[0003] In order to cope with the diversification of products in small quantities, an FPGA (Field Programmable Gate Arra) is used.
y) type semiconductor devices are used. In the FPGA, a large number of functional blocks are laid out on a chip, connection information of each block is written, a logic circuit is formed, and the connection information to be written is changed to support various types.

One of the methods of writing data in such an FPGA is to form wiring for connection between blocks in advance and change the connection between each block and the wiring after completion of a product, thereby forming a logic circuit. There is something to form.

[0005] As a method of writing connection information by connecting each block to a wiring, an insulator is interposed between conductors, and a voltage is applied between the conductors of a fuse element formed in a non-conductive state. There is an anti-fuse structure in which a dielectric breakdown is performed to make a conductive state.

In the anti-fuse structure, the on-resistance of the connection is low, the capacitance of the connection portion is low, the write voltage is low, and the program area can be spread over the functional blocks, so that the chip area can be reduced. There are advantages.
In the anti-fuse structure, a structure in which amorphous silicon is interposed as an insulator between a lower metal wiring layer and an upper metal wiring layer in order to reduce the on-resistance is mainly used.

An FPGA having such an antifuse structure
Are described, for example, in "Nikkei Micro Devices", published October 1, 1992, pages 37 to 44, published by Nikkei BP.

[0008]

In such an antifuse element, the lower conductor layer usually connects each element of the functional block formed on the main surface of the semiconductor substrate to form a connection wiring and a wiring inside the block. A wiring layer of the same layer as above, an interlayer insulating film provided with an opening formed on this wiring layer, and a metal layer serving as an antifuse insulator and a landing pad of an upper conductor layer deposited on the entire surface. Is patterned by photolithography and etching.

For this reason, a step occurs in the insulator and the metal layer due to the thickness of the wiring layer of the lower conductor layer, and the progress of the etching is different from that of the flat part at the step, so that the side surface is etched. The rest may occur.

Further, in a portion where the interval between the wiring layers of the lower conductor layer is narrowed to the limit, exposure failure or development failure is apt to occur in the recess formed by the step, thereby generating a residue due to the remaining resist. The resist residue or the residue of the insulator which has been poorly etched due to the residue may be peeled off in a later step to become a foreign substance and cause contamination, which may cause a failure of the semiconductor device.

An object of the present invention is to provide a technique capable of preventing the occurrence of a defect due to a remaining resist or remaining etching during the formation of the antifuse element.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

Means for Solving the Problems Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described.
It is as follows.

The insulator is interposed between the lower conductor layer and the upper conductor layer to be in a non-conductive state, and a voltage is applied between the lower conductor layer and the upper conductor layer to cause dielectric breakdown. The insulator is formed by flattening between the wiring layers constituting the lower conductor layer on which the insulator is formed, of the anti-fuse element that makes the layer and the upper conductor layer conductive.

According to the above-described means, since the base of the insulator of the anti-fuse element is flattened and the material of the insulator is formed flat, the etching proceeds uniformly, and the etching residue remains. Is prevented.

Also, even in a portion where the interval between the wiring layers of the lower conductor layer is narrowed to the limit, a concave portion is not formed in the base by flattening, and exposure failure or development failure is avoided. In addition, it is possible to prevent the generation of residues in the wiring layer due to poor etching. Therefore, it is possible to prevent the occurrence of a defect in the semiconductor device due to the contamination due to the generation of the foreign matter.

Hereinafter, embodiments of the present invention will be described. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0018]

FIG. 1 is a longitudinal sectional view showing an antifuse element of a semiconductor device according to an embodiment of the present invention.

Reference numeral 1 denotes an insulating layer for insulating and covering a functional block (not shown) constituted by a semiconductor element formed on the main surface of the semiconductor substrate. Reference numeral 2 denotes a first metal wiring layer. 2 is the lower conductor layer 2 of the antifuse element
a and the semiconductor element are connected to each other to form a functional block. The functional block is constituted by a connection wiring 2b connecting the functional block and the lower conductor layer 2a.

Reference numeral 3 denotes a first interlayer insulating film, which is a silicon oxide film 3a covering between the metal wiring layers 2, an SOG film 3b for flattening the silicon oxide film 3a, and an oxidation covering the entire surface including the metal wiring layer. It is composed of a silicon film 3c.

4 is an insulator of the anti-fuse element,
It is composed of an insulating layer 4a of amorphous silicon and a metal layer 4b.

Reference numeral 5 denotes a second interlayer insulating film, which is a silicon oxide film 5a for covering between the metal wiring layers 2, an SOG (Spin-On-Glass) film 5b for planarizing the silicon oxide film 5a, and a silicon oxide film. It is constituted by the film 5c.

Reference numeral 6 denotes a second metal wiring layer. The metal wiring layer 6 is connected to the upper conductor layer 6a and the upper conductor layer 6a of the anti-fuse element, and each of the above-mentioned functions is provided by selective conduction of the anti-fuse element. It is composed of connection wires 6b that connect the blocks to form a logic circuit.

In the anti-fuse element, the insulating layer 4a of the insulator 4 is connected to the lower conductor layer 2a by an opening provided in the silicon oxide film 3c, and the upper conductor layer 6a is connected to the lower conductor layer 2a by an opening provided in the interlayer insulating film 5. It is configured by being connected to the metal layer 4b of the insulator 4.

Next, a method of manufacturing the antifuse shown in FIG. 1 will be described with reference to FIGS.

First, as an insulating layer 1 for insulating and covering various semiconductor elements formed in an active region of a main surface of a semiconductor substrate such as single crystal silicon, for example, silicon oxide by CVD is deposited on the entire surface. For example, a laminated film is formed by sequentially laminating a titanium-tungsten alloy film, an aluminum alloy film to which copper and silicon are added, and a titanium-tungsten alloy film, and is patterned to form a lower conductor layer 2.
a, a first metal wiring layer 2 composed of connection wiring 2b is formed. This state is shown in FIG.

Next, a silicon oxide film 3a is deposited by plasma CVD using tetraethoxysilane (TEOS) gas (organosilane) as a main source gas, and an SOG film 3b is formed on the silicon oxide film 3a. The concave portion of the silicon oxide film 3a is buried and etched back to be flattened to expose the metal wiring layer 2 and to cover the lower conductor layer 2a, the connection wiring 2b, the silicon oxide film 3a and the SOG film 3b. Is deposited on the entire surface by plasma CVD using TEOS gas. This state is shown in FIG.

Next, the lower conductor layer 2 of the anti-fuse element
An opening exposing a is provided in the silicon oxide film 3c. This state is shown in FIG.

Next, an insulating film 4a made of amorphous silicon and a metal layer 4b made of titanium-tungsten
Is deposited on the entire surface and is patterned to form an insulator 4 of the anti-fuse element. This state is shown in FIG.

Next, a silicon oxide film 5a is deposited by plasma CVD using a TEOS gas, an SOG film 5b is formed on the silicon oxide film 5a, and the recesses of the silicon oxide film 5a are buried. And flatten the silicon oxide film 5c covering the silicon oxide film 5a and the SOG film 5b.
An interlayer insulating film 5 is formed by depositing the entire surface by plasma CVD using an EOS gas. This state is shown in FIG.

Next, an opening for exposing the insulator 4 of the anti-fuse element is provided in the interlayer insulating film 5. This state is shown in FIG.
Shown in

Next, for example, a titanium-tungsten alloy film, an aluminum alloy film added with copper and silicon, and a titanium-tungsten alloy film are formed on the entire surface of the interlayer insulating film 5 and the metal layer 4b of the insulator 4 exposed by the opening. Are sequentially deposited, and patterning is performed to form a second metal wiring layer 6 composed of the upper conductor layer 6a and the connection wiring 6b, and the state shown in FIG. 1 is obtained. Thereafter, a protective film (not shown) made of, for example, a silicon nitride film is formed on the entire surface.

In this embodiment, the SOG film 3b is used to planarize the interlayer insulating film 3. However, the planarization method may be replaced by CMP (Chemical Mechanical Polish).
ing), ECR (Electron Cyclotron Resona)
It is also possible to use plasma.

In the present invention, since the interlayer insulating film 3 is flattened, the only step affecting the second metal wiring layer 6 is the step caused by the insulator 4 of the anti-fuse element. SOG film 5b for flattening film 5
May be omitted to simplify the process.

FIG. 8 is a longitudinal sectional view showing a state after patterning of the insulator of the conventional anti-fuse element.

In such a conventional anti-fuse element, an opening is formed in the silicon oxide film 3a covering the metal wiring layer 2 composed of the lower conductor layer 2a and the connection wiring 2b, and the anti-fuse insulator 4 deposited on the entire surface is formed. Is patterned by etching using a resist mask 7 formed by photolithography.

For this reason, a step is generated due to the thickness of the metal wiring layer 2, and the progress of the etching is different from that of the flat portion at this step, so that an etching residue is left on the side surface thereof and the amorphous silicon residue 4 c or titanium -
Tungsten residue 4d may occur.

Further, in a portion where the distance between the metal wiring layers 2 is narrowed to the limit, exposure failure or development failure is apt to occur in the concave portion formed by the step, thereby causing a resist mask residue 7a due to the remaining resist. The residue 7a of the resist 7a or the residue 4c of the amorphous silicon or the residue 4d of the titanium-tungsten which is poorly etched due to the residue 7a is peeled off in a later step to become a foreign substance, thereby causing contamination and causing a defect in the semiconductor device. May cause occurrence.

According to the present invention, since the base for forming the insulator 4 of the anti-fuse element is flattened, the material of the insulator 4 is formed flat, and the etching for the insulator patterning is uniform. In the portion where the interval between the metal wiring layers 2 constituting the lower conductor layer is narrowed to the limit, no concave portion is formed in the base, so that exposure is not performed. Defective or defective development is avoided.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, in the above-described embodiment, amorphous silicon is used as the insulator 4a of the anti-fuse element. However, as the insulator 4a, a polycrystalline silicon film into which impurities for reducing the resistance value are not introduced, Plasma CV
A silicon nitride film or a silicon oxide film of D may be used.

[0042]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, there is an effect that a base for forming an insulator of an anti-fuse element is flattened.

(2) According to the present invention, the effect (1) has an effect that the material of the insulator is formed flat.

(3) According to the present invention, the effect (2) has an effect that the etching for the insulator patterning proceeds uniformly and the occurrence of an unetched residue is prevented.

(4) According to the present invention, due to the above-mentioned effect (2), even in a portion where the interval between the wiring layers of the lower conductor layer is reduced to the limit, no recess is formed in the base by flattening, and There is an effect that a defect or a development defect is avoided.

(5) According to the present invention, the above-mentioned effect (4) has an effect that it is possible to prevent the generation of a residue due to the remaining resist and a residue of the wiring layer due to poor etching.

(6) According to the present invention, the above effect (3)
According to (5), there is an effect that occurrence of a defect in the semiconductor device due to contamination due to generation of foreign matter can be prevented.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing an antifuse of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing an antifuse of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 3 is a longitudinal sectional view showing an antifuse of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 4 is a longitudinal sectional view showing an antifuse of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 5 is a longitudinal sectional view showing an antifuse of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 6 is a longitudinal sectional view showing an antifuse of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 7 is a longitudinal sectional view showing an antifuse of the semiconductor device according to one embodiment of the present invention for each manufacturing process.

FIG. 8 is a longitudinal sectional view showing an antifuse of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulating layer, 2, 6 ... Metal wiring layer, 2a ... Lower conductor layer,
2b, 6b: connection wiring, 3, 5: interlayer insulating film, 3a, 5
a: silicon oxide film, 3b, 5b: SOG film, 3c, 5c ...
Silicon oxide film, 4 ... insulator, 4a ... insulating layer, 4b ... metal layer, 4c, 4d ... residue of insulator, 6 ... metal wiring layer, 6a
... upper conductor layer, 6b ... connection wiring, 7 ... resist mask,
7a: Residue of resist mask.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kuniaki Tadakuma 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi RLS Engineering Co., Ltd. (72) Inventor Eri Iguchi Tokyo 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd.

Claims (9)

[Claims] An insulating material interposed between a lower conductor layer and an upper conductor layer to make a non-conductive state, and a voltage is applied between the lower conductor layer and the upper conductor layer to cause insulation breakdown; In a semiconductor device having an anti-fuse element that brings a conductive state between a lower conductor layer and an upper conductor layer, the insulator is formed by flattening between wiring layers constituting the lower conductor layer on which the insulator is formed. A semiconductor device characterized by forming: 2. The semiconductor device according to claim 1, wherein said insulator is amorphous silicon. 3. The semiconductor device according to claim 1, wherein an SOG film is formed for the planarization. 4. The semiconductor device according to claim 1, wherein an interlayer insulating film covering the insulator is not planarized. 5. A method of manufacturing a semiconductor device having an anti-fuse element which is brought into a non-conductive state by interposing an insulator between a lower conductor layer and an upper conductor layer and brought into a conductive state by applying a voltage between said conductor layers. A step of forming a wiring layer forming the lower conductor layer, a step of flattening between wiring layers forming the lower conductor layer, and a step of forming the insulator. Semiconductor device manufacturing method. 6. The method according to claim 5, wherein the insulator is amorphous silicon. 7. The method according to claim 5, wherein the planarization is performed by forming an SOG film and etching back. 8. The method according to claim 5, wherein the planarization is performed by CMP. 9. The method of manufacturing a semiconductor device according to claim 5, wherein the interlayer insulating film covering the insulator is not planarized.