JPH113908A - Semiconductor element and electrode configulation changing method and semiconductor device - Google Patents
Semiconductor element and electrode configulation changing method and semiconductor deviceInfo
- Publication number
- JPH113908A JPH113908A JP15528797A JP15528797A JPH113908A JP H113908 A JPH113908 A JP H113908A JP 15528797 A JP15528797 A JP 15528797A JP 15528797 A JP15528797 A JP 15528797A JP H113908 A JPH113908 A JP H113908A
- Authority
- JP
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- Prior art keywords
- electrode
- insulating member
- semiconductor device
- semiconductor
- element body
- Prior art date
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- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 127
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000126 substance Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims 1
- 229920005989 resin Polymers 0.000 description 17
- 239000011347 resin Substances 0.000 description 17
- 239000010410 layer Substances 0.000 description 15
- 239000003795 chemical substances by application Substances 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 150000001336 alkenes Chemical class 0.000 description 3
- 238000000354 decomposition reaction Methods 0.000 description 3
- 238000007726 management method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- JRZJOMJEPLMPRA-UHFFFAOYSA-N olefin Natural products CCCCCCCC=C JRZJOMJEPLMPRA-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920005672 polyolefin resin Polymers 0.000 description 2
- 230000003578 releasing effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- Condensed Matter Physics & Semiconductors (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体素子及びその
電極形態変更方法に係り、特に種々のパッケージに搭載
される半導体素子及びその電極形態変更方法に関する。
近年、半導体装置は種々の電子機器に搭載されるように
なってきており、これに伴いパッケージ構造も搭載され
る電子機器の装置搭載スペースに対応するよう種々のも
のが提供されている。よって、半導体装置に内設される
半導体素子も、パッケージ構造に適合した構成とする必
要がある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of changing an electrode configuration thereof, and more particularly to a semiconductor device mounted on various packages and a method of changing an electrode configuration thereof.
2. Description of the Related Art In recent years, semiconductor devices have been mounted on various electronic devices, and accordingly, various devices have been provided so as to correspond to a device mounting space of an electronic device in which a package structure is also mounted. Therefore, the semiconductor element provided in the semiconductor device also needs to have a configuration suitable for the package structure.
【０００２】[0002]
【従来の技術】上記のように、パッケージ構造が多様化
すると、パッケージ内に配設される半導体素子（半導体
チップ）が同一であっても、半導体パッケージの構造が
異なる場合が発生する。これは、特に汎用の半導体装置
においてよく発生することである。2. Description of the Related Art As described above, when the package structure is diversified, the semiconductor package (semiconductor chip) provided in the package may have the same structure even if the semiconductor element is the same. This often occurs particularly in general-purpose semiconductor devices.
【０００３】具体例を図６及び図７を用いて説明する。
図６に示す半導体装置１Ａは、リード６が矩形状とされ
た樹脂パッケージ４Ａの短辺側から延出するよう構成さ
れたパッケージ構造とされている（以下、この構造の樹
脂パッケージを横長パッケージ４Ａという）。これに対
し、図７に示す半導体装置１Ｂは、リード６が矩形状と
された樹脂パッケージ４Ｂの長辺側から延出するよう構
成されたパッケージ構造とされている（以下、この構造
の樹脂パッケージを縦長パッケージ４Ｂという）。しか
るに、各樹脂パッケージ４Ａ，４Ｂ内に搭載される半導
体素子２Ａ，２Ｂは機能的に同一の半導体素子である。A specific example will be described with reference to FIGS.
The semiconductor device 1A shown in FIG. 6 has a package structure in which the leads 6 extend from the shorter side of the rectangular resin package 4A (hereinafter, the resin package having this structure is referred to as a horizontally long package 4A). ). On the other hand, the semiconductor device 1B shown in FIG. 7 has a package structure in which the leads 6 extend from the long side of the rectangular resin package 4B (hereinafter, the resin package having this structure). Is referred to as a vertical package 4B). However, the semiconductor elements 2A and 2B mounted in each of the resin packages 4A and 4B are functionally identical semiconductor elements.
【０００４】続いて、上記した半導体装置１Ａ，１Ｂの
半導体素子２Ａ，２Ｂとリード６との接続構造について
図８及び図９を用いて説明する。図８は、横長パッケー
ジ４Ａにおける半導体素子２Ａとリード６との接続構造
を示している。同図に示すように、パッケージが横長形
状とされた横長パッケージ４Ａでは、内設する半導体素
子２Ａも横長となるよう配設する必要がある。Next, a connection structure between the semiconductor elements 2A and 2B of the semiconductor devices 1A and 1B and the leads 6 will be described with reference to FIGS. FIG. 8 shows a connection structure between the semiconductor element 2A and the lead 6 in the horizontally long package 4A. As shown in the figure, in the horizontally long package 4A in which the package is horizontally long, it is necessary to arrange the semiconductor element 2A provided therein so as to be horizontally long.
【０００５】また、半導体素子２Ａに形成された電極８
Ａとリード６とはワイヤ９により電気的に接続される
が、このワイヤ９の長さは損失低減を図る面からなるべ
く短くする必要がある。このため、従来の横長パッケー
ジ４Ａでは、半導体素子２Ａの短辺側に電極８Ａを配設
することが行なわれていた。一方、図９は、縦長パッケ
ージ４Ｂにおける半導体素子２Ｂとリード６との接続構
造を示している。同図に示すように、パッケージが縦長
形状とされた縦長パッケージ４Ｂでは、内設する半導体
素子２Ｂも横長となるよう配設する必要がある。また、
前記のようにワイヤ９の長さは損失低減を図る面からな
るべく短くする必要があるため、従来の縦長パッケージ
４Ｂでは半導体素子２Ｂの長辺側に電極８Ｂを配設する
ことが行なわれていた。The electrode 8 formed on the semiconductor element 2A
A and the lead 6 are electrically connected by a wire 9, but the length of the wire 9 needs to be as short as possible in order to reduce loss. For this reason, in the conventional horizontally long package 4A, the electrode 8A is arranged on the short side of the semiconductor element 2A. On the other hand, FIG. 9 shows a connection structure between the semiconductor element 2B and the lead 6 in the vertically long package 4B. As shown in the figure, in a vertically long package 4B in which the package has a vertically long shape, it is necessary to arrange the semiconductor element 2B provided inside so as to be horizontally long. Also,
As described above, since the length of the wire 9 needs to be as short as possible in order to reduce the loss, in the conventional vertically long package 4B, the electrode 8B is provided on the long side of the semiconductor element 2B. .
【０００６】[0006]
【発明が解決しようとする課題】上記したように、図６
及び図８に示す半導体素子２Ａと、図７及び図９に示す
半導体装置２Ｂは同一機能を有した半導体素子である。
しかるに、従来の構成では、パッケージ構造が異なる
と、これに伴い電極８Ａ，８Ｂの形成位置が異なってし
まい、よって別個の構成とされた半導体素子２Ａ，２Ｂ
を夫々製造する必要があった。このように、従来では電
極８Ａ，８Ｂ以外は同一の構成であるにも拘わらず、単
に電極８Ａ，８Ｂの形成位置の違いのみで夫々半導体素
子２Ａ，２Ｂを形成せねばならず製造効率が悪いという
問題点があった。As described above, FIG.
The semiconductor device 2A shown in FIG. 8 and the semiconductor device 2B shown in FIGS. 7 and 9 are semiconductor devices having the same function.
However, in the conventional configuration, if the package structure is different, the positions at which the electrodes 8A and 8B are formed are different accordingly, so that the semiconductor elements 2A and 2B having separate configurations are formed.
Had to be manufactured respectively. As described above, the semiconductor elements 2A and 2B must be formed only by the difference in the formation positions of the electrodes 8A and 8B, but the manufacturing efficiency is poor, although the structure is the same except for the electrodes 8A and 8B. There was a problem.
【０００７】また、製造された半導体装置の在庫管理上
では、次のような問題点があった。即ち、顧客からの受
注に対し、短納期で製品を出荷するためには需要を見込
んで半導体装置を工場に仕込んでおく必要があるが、パ
ッケージ構造によって異なる半導体素子を搭載する従来
構成では、見込みを間違えた場合には、不良在庫や、或
いは在庫不良が発生してしまう。よって、上記の見込み
の判断が非常に難しくなり、在庫管理の面からも従来構
成の半導体装置は望ましくなかった。Further, there are the following problems in inventory management of manufactured semiconductor devices. In other words, in order to ship products in a short delivery time in response to orders from customers, it is necessary to prepare semiconductor devices in factories in anticipation of demand, but with the conventional configuration mounting different semiconductor elements depending on the package structure, If a mistake is made, a defective inventory or a defective inventory occurs. Therefore, it is very difficult to judge the above-mentioned expectation, and the semiconductor device having the conventional configuration is not desirable from the viewpoint of inventory management.
【０００８】一方、上記の問題点を解決する手段とし
て、半導体素子上に、横長パッケージ用の電極（横長用
電極）と、縦長用パッケージ用の電極（縦長用電極）を
共に配設する構成とすることが考えられる。しるかに、
単に半導体素子の同一面上に横長用電極と縦長用電極と
を併せて形成した構成では、従来の半導体素子２Ａ，２
Ｂに対し電極数が２倍となってしまい、これに伴い電極
形成スペースが大きくなり半導体素子が大型化してしま
うという新たな問題点が生じてしまう。On the other hand, as means for solving the above-mentioned problems, there is provided a structure in which an electrode for a horizontally long package (a horizontally long electrode) and an electrode for a vertically long package (a vertically long electrode) are both provided on a semiconductor element. It is possible to do. Or maybe
In a configuration in which a horizontally long electrode and a vertically long electrode are formed together on the same surface of a semiconductor element, the conventional semiconductor elements 2A, 2
The number of electrodes is twice as large as that of B, which causes a new problem that the space for forming the electrodes becomes large and the semiconductor element becomes large.
【０００９】本発明は上記の点に鑑みてなされたもので
あり、各種パッケージ構造に容易に対応しうる半導体素
子及びその電極形態変更方法及び半導体装置を提供する
ことを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a semiconductor element, a method of changing an electrode form thereof, and a semiconductor device which can easily cope with various package structures.
【００１０】[0010]
【課題を解決するための手段】上記課題は、次に述べる
各種手段を講じることにより解決することができる。請
求項１記載の発明に係る半導体素子では、電子回路が形
成された素子本体と、該素子本体の表面上に第１の配置
形態で形成された第１の電極と、前記表面を覆うように
形成されると共に、前記素子本体に対し剥離可能な構成
で配設された絶縁部材と、該絶縁部材上に前記第１の配
置形態と異なる第２の配置形態で形成された第２の電極
と、前記絶縁部材が前記素子本体に配設された状態にお
いて前記第１の電極と第２の電極とを電気的に接続する
電極接続手段と、を具備することを特徴とするものであ
る。The above object can be attained by taking the following various means. In the semiconductor device according to the first aspect of the present invention, an element body on which an electronic circuit is formed, a first electrode formed on the surface of the element body in a first arrangement form, and the surface is covered. An insulating member that is formed and disposed in a configuration that can be peeled off from the element body, and a second electrode that is formed on the insulating member in a second arrangement different from the first arrangement. And an electrode connecting means for electrically connecting the first electrode and the second electrode in a state where the insulating member is provided in the element main body.
【００１１】また、請求項２記載の発明では、前記請求
項１記載の半導体素子において、前記電極接続手段が、
前記絶縁部材に形成されており、前記第１の電極と対向
する位置に形成されたスルーホール電極と、前記絶縁部
材に形成されており、一端が前記第２の電極に接続する
と共に、他端が前記スルーホール電極に接続された配線
と、により構成されることを特徴とするものである。Further, in the invention according to claim 2, in the semiconductor device according to claim 1, the electrode connecting means includes:
A through-hole electrode formed in the insulating member and formed at a position facing the first electrode; and a through-hole electrode formed in the insulating member and having one end connected to the second electrode and the other end And a wiring connected to the through-hole electrode.
【００１２】また、請求項３記載の発明では、前記請求
項１または２記載の半導体装置において、前記絶縁部材
を多層構造とし、各層間に内層配線を形成したことを特
徴とするものである。また、請求項４記載の発明では、
前記請求項１乃至３のいずれかに記載の半導体素子にお
いて、前記絶縁部材と前記素子本体との間に、剥離を容
易とするための剥離剤が配設されていることを特徴とす
るものである。According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the insulating member has a multilayer structure, and an inner layer wiring is formed between each layer. In the invention according to claim 4,
4. The semiconductor device according to claim 1, wherein a release agent for facilitating release is provided between the insulating member and the element body. is there.
【００１３】また、請求項５記載の発明では、前記請求
項１乃至４のいずれかに記載の半導体素子において、前
記絶縁部材の材質として、前記素子本体に対し接着性の
低い材質を選定したことを特徴とするものである。ま
た、請求項６記載の発明では、請求項１乃至５のいずれ
かに記載の半導体素子において、前記素子本体から前記
絶縁部材を剥離することにより電極形態を変更する半導
体素子の電極形態変更方法であって、前記絶縁部材を機
械的手段を用いて前記素子本体から剥離させることを特
徴とするものである。According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, a material having low adhesiveness to the element body is selected as a material of the insulating member. It is characterized by the following. According to a sixth aspect of the present invention, there is provided the semiconductor element according to any one of the first to fifth aspects, wherein the electrode configuration is changed by peeling the insulating member from the element body. In addition, the insulating member is separated from the element body by using a mechanical means.
【００１４】また、請求項７記載の発明では、前記請求
項１乃至５のいずれかに記載の半導体素子において、前
記素子本体から前記絶縁部材を剥離することにより電極
形態を変更する半導体素子の電極形態変更方法であっ
て、前記絶縁部材を化学的手段を用いて前記素子本体か
ら剥離させることを特徴とするものである。According to a seventh aspect of the present invention, in the semiconductor element according to any one of the first to fifth aspects, the electrode configuration of the semiconductor element is changed by peeling the insulating member from the element body. A method of changing the form, wherein the insulating member is separated from the element body by using a chemical means.
【００１５】また、請求項８記載の発明に係る半導体装
置では、前記請求項１乃至５のいずれかに記載の半導体
素子と、前記半導体素子と電気的に接続されたリード
と、前記半導体素子を封止するパッケージとを具備する
ことを特徴とするものである。In a semiconductor device according to an eighth aspect of the present invention, the semiconductor device according to any one of the first to fifth aspects, a lead electrically connected to the semiconductor element, and And a package to be sealed.
【００１６】上記した各手段は、次のように作用する。
請求項１記載の発明によれば、素子本体上には第１の電
極が形成され、またこの素子本体上に形成された絶縁部
材上には第２の電極が形成される。よって、第１の電極
と第２の電極は絶縁部材を介して積層された構成とな
り、第１及び第２の電極を設けても素子本体の面積が増
大することはなく小型化を図ることができる。Each of the above means operates as follows.
According to the first aspect of the present invention, the first electrode is formed on the element main body, and the second electrode is formed on the insulating member formed on the element main body. Therefore, the first electrode and the second electrode are stacked with an insulating member interposed therebetween, and even if the first and second electrodes are provided, the area of the element body does not increase and the size can be reduced. it can.
【００１７】また、絶縁部材が素子本体に配設された状
態において第１の電極と第２の電極とは電極接続手段に
より電気的に接続されている。よって、絶縁部材が素子
本体に配設された状態では、第２の電極に外部端子（例
えばリード）を接続することにより、電気的接続手段に
よりこの外部端子は半導体素子と接続された構成とな
る。Further, the first electrode and the second electrode are electrically connected by the electrode connecting means in a state where the insulating member is provided on the element body. Therefore, in a state in which the insulating member is provided in the element body, by connecting an external terminal (for example, a lead) to the second electrode, the external terminal is connected to the semiconductor element by the electric connection means. .
【００１８】一方、絶縁部材は素子本体に剥離可能な構
成で配設されており、また電気的接続手段は素子本体か
ら絶縁部材が剥離することにより、第１の電極と第２の
電極との電気的接続を解除する構成とされている。よっ
て、絶縁部材が素子本体から剥離した状態では、第１の
電極が素子本体上に露出して存在する構成となり、外部
端子を第１の電極に接続することにより、外部端子と半
導体素子とは電気的に接続された構成となる。On the other hand, the insulating member is disposed on the element main body in such a manner that it can be peeled off, and the electric connection means separates the first electrode from the second electrode by peeling off the insulating member from the element main body. The configuration is such that the electrical connection is released. Therefore, in a state where the insulating member is separated from the element body, the first electrode is exposed and present on the element body, and by connecting the external terminal to the first electrode, the external terminal and the semiconductor element are separated from each other. The configuration is electrically connected.
【００１９】即ち、絶縁部材が配設された状態と、絶縁
部材が素子本体から剥離された状態とで、電極の配設形
態を異ならせることができる。よって、パッケージ構造
に応じて電極の形成位置を変更する必要がある場合であ
っても、絶縁部材をそのまま配設した状態にするか、或
いは絶縁部材を素子本体から剥離するのみで容易にパッ
ケージ構造に対応した電極形態を実現することができ
る。That is, the arrangement of the electrodes can be made different between the state where the insulating member is provided and the state where the insulating member is separated from the element body. Therefore, even when it is necessary to change the formation positions of the electrodes in accordance with the package structure, the package structure can be easily formed by leaving the insulating member as it is or by simply peeling the insulating member from the element body. Can be realized.
【００２０】また、請求項２記載の発明によれば、第１
の電極と対向する位置に形成されたスルーホール電極
と、一端が第２の電極に接続すると共に他端がスルーホ
ール電極に接続された配線とにより電気的接続手段を構
成したことにより、簡単な構成で第１の電極と第２の電
極を電気的に接続することができる。According to the second aspect of the present invention, the first
And a wiring having one end connected to the second electrode and the other end connected to the through-hole electrode, thereby forming an electrical connection means. With the structure, the first electrode and the second electrode can be electrically connected.
【００２１】また、スルーホール電極及び配線は、いず
れも絶縁部材に配設されているため、絶縁部材を素子本
体から剥離し排除することにより、電気的接続手段も併
せて排除される。よって、絶縁部材を素子本体から剥離
した後に、電気的接続手段が第１の電極と外部端子との
接続に悪影響を及ぼすようなことはない。また、請求項
３記載の発明によれば、絶縁部材を多層構造とすると共
に各層間に内層配線を形成したことにより、各層毎に電
極の配設形態を設定できるため、複数のパッケージ形態
（即ち、電極の配設形態）に容易に対応することができ
る。具体的には、絶縁部材が５層構造であり、その３層
目に所望する配設形態で電極が形成されていた場合に
は、上部の２層のみを剥離させることにより、所望の電
極の配設形態を実現することができる。Further, since both the through-hole electrode and the wiring are provided on the insulating member, the insulating member is peeled off from the element body and eliminated, so that the electrical connection means is also eliminated. Therefore, after the insulating member is peeled off from the element body, the electric connection means does not adversely affect the connection between the first electrode and the external terminal. According to the third aspect of the invention, since the insulating member has a multilayer structure and the inner layer wiring is formed between the layers, the arrangement of the electrodes can be set for each layer. , The arrangement of the electrodes). Specifically, when the insulating member has a five-layer structure and an electrode is formed in a desired arrangement on the third layer, only the upper two layers are peeled off to form a desired electrode. An arrangement form can be realized.
【００２２】また、請求項４記載の発明によれば、絶縁
部材と素子本体との間に剥離剤を配設することにより、
絶縁部材を素子本体から剥離する処理を容易に行なうこ
とができる。また、請求項５記載の発明によれば、絶縁
部材の材質として素子本体に対し接着性の低い材質を選
定したことにより、絶縁部材を素子本体から剥離する処
理を容易に行なうことができる。According to the fourth aspect of the present invention, the release agent is provided between the insulating member and the element body,
The process of peeling the insulating member from the element body can be easily performed. According to the fifth aspect of the present invention, since a material having low adhesiveness to the element body is selected as a material of the insulating member, a process of peeling the insulating member from the element body can be easily performed.
【００２３】また、請求項６または請求項７記載の発明
によれば、絶縁部材を機械的手段或いは化学的手段を用
いて素子本体から剥離させる方法を採用したことによ
り、比較的簡単な設備で容易に絶縁部材を素子本体から
剥離させることができる。また、請求項８記載の発明に
係る半導体装置によれば、前記の請求項１乃至５のいず
れかに記載の半導体素子を用いているため、半導体素子
とリードとの離間距離を最小距離とすることができ、電
気的損失の発生を抑制することができる。また、電極の
配設形態がパッケージ構造に対応しているため、半導体
装置の小型化を図ることができる。Further, according to the invention of claim 6 or claim 7, the method of peeling off the insulating member from the element body by using a mechanical means or a chemical means is adopted, so that a relatively simple facility can be used. The insulating member can be easily separated from the element body. According to the semiconductor device of the present invention, since the semiconductor element according to any one of the first to fifth aspects is used, the separation distance between the semiconductor element and the lead is set to the minimum distance. And the occurrence of electrical loss can be suppressed. Further, since the arrangement of the electrodes corresponds to the package structure, the size of the semiconductor device can be reduced.
【００２４】[0024]
【発明の実施の形態】次に本発明の実施の形態について
図面と共に説明する。図１乃至図３は、本発明の一実施
例である半導体素子１０及び半導体装置１２Ａ，１２Ｂ
を説明するための図である。図１は、先に図６を用いて
説明した横長パッケージに半導体素子１０を適用した半
導体装置１２Ａを示しており、また図２は先に図７を用
いて説明した縦長パッケージに半導体素子１０を適用し
た半導体装置１２Ｂを示している。まず、図１及び図３
を用いて、半導体素子１０の構成について説明する。Embodiments of the present invention will now be described with reference to the drawings. 1 to 3 show a semiconductor element 10 and semiconductor devices 12A and 12B according to an embodiment of the present invention.
FIG. FIG. 1 shows a semiconductor device 12A in which the semiconductor element 10 is applied to the horizontally long package described above with reference to FIG. 6, and FIG. 2 shows the semiconductor element 10 in the vertically long package described above with reference to FIG. This shows a semiconductor device 12B to which the present invention is applied. First, FIGS. 1 and 3
The configuration of the semiconductor element 10 will be described with reference to FIG.
【００２５】半導体素子１０は、大略すると素子本体１
４，第１の電極１６，第２の電極１８，スルーホール電
極２０，配線２２，及び絶縁膜３０（図１では梨地で示
す）等により構成されている。素子本体１４は半導体装
置１０の基板となるものであり、例えばシリコン基板或
いはガリウム−砒素基板上に回路形成領域３２を有した
構成とされている。本実施例に係る素子本体１４は、短
辺と長辺を有した長方形状とされている。The semiconductor element 10 is roughly the element body 1
4, a first electrode 16, a second electrode 18, a through-hole electrode 20, a wiring 22, an insulating film 30 (indicated in FIG. 1 by a satin finish), and the like. The element body 14 serves as a substrate of the semiconductor device 10, and has a configuration having a circuit formation region 32 on a silicon substrate or a gallium-arsenic substrate, for example. The element body 14 according to the present embodiment has a rectangular shape having a short side and a long side.
【００２６】第１の電極１６は素子本体１４の上面に形
成されると共に、図示しない配線により回路形成領域３
２に形成された電子回路に接続されている。この第１の
電極１６は、図３に示されるように素子本体１４の上面
に直接形成されている。また、第１の電極１６は、図１
に示されるように、素子本体１４の長辺に沿って形成さ
れている。本実施例では、この素子本体１４の長辺に沿
って第１の電極１６が配設された形態を電極の第１の配
設形態というものとする。The first electrode 16 is formed on the upper surface of the element body 14 and is connected to the circuit forming region 3 by wiring (not shown).
2 is connected to the electronic circuit formed. The first electrode 16 is formed directly on the upper surface of the element body 14 as shown in FIG. In addition, the first electrode 16 corresponds to FIG.
Are formed along the long side of the element body 14. In the present embodiment, a form in which the first electrode 16 is provided along the long side of the element body 14 is referred to as a first arrangement form of the electrodes.
【００２７】第２の電極１８は、絶縁膜３０（絶縁部
材）に形成されている。この第２の電極１８は、図３に
示されるように絶縁膜３０の上面に形成されている。ま
た、第２の電極１８は、図１に示されるように、素子本
体１４の短辺に沿って形成されている。本実施例では、
この素子本体１４の短辺に沿って第２の電極１８が配設
された形態を電極の第２の配設形態というものとする。The second electrode 18 is formed on an insulating film 30 (insulating member). The second electrode 18 is formed on the upper surface of the insulating film 30, as shown in FIG. The second electrode 18 is formed along the short side of the element body 14, as shown in FIG. In this embodiment,
The configuration in which the second electrode 18 is provided along the short side of the element body 14 is referred to as a second configuration of electrodes.
【００２８】絶縁膜３０は、例えばオレフィン系樹脂を
主成分とし、エポキシ樹脂が所定の濃度に混入されてい
る組成の膜であり、素子本体１４の全面を覆うよう形成
されている。エポキシ含有のオレフィン系樹脂は、エポ
キシ樹脂の分解温度以上に加熱することで離型作用を発
揮する。よって、絶縁膜３０と素子本体１４との強力な
密着は阻害されており、従って絶縁膜３０は素子本体１
４に対し剥離可能な構成となっている。The insulating film 30 is a film containing, for example, an olefin-based resin as a main component and an epoxy resin mixed at a predetermined concentration, and is formed so as to cover the entire surface of the element body 14. The epoxy-containing olefin-based resin exerts a releasing effect when heated to a temperature higher than the decomposition temperature of the epoxy resin. Therefore, strong adhesion between the insulating film 30 and the element body 14 is hindered.
4 can be peeled off.
【００２９】また、絶縁膜３０の素子本体１４からの剥
離性をより高めるためには、例えば図３に示すように素
子本体１４と絶縁膜３０との界面に剥離剤３６を塗布し
ておいてもよい。この剥離剤３６としては、例えばエポ
キシ含有のオレフィン樹脂を用いることが考えられる。
但し、上記の絶縁膜３０と素子本体１４の接合力は、外
部から剥離力を加えなければ絶縁膜３０が素子本体１４
から剥離しない程度の強さを維持するよう構成されてい
る。しかるに、後述するように剥離力を加えて意図的に
剥離させようとした場合には、絶縁膜３０は素子本体１
４から剥離する構成とされている。尚、上記の絶縁膜３
０としては、エポキシ含有のオレフィン系樹脂に代えて
エポキシを含有したポリイミドを用いることも可能であ
る。Further, in order to further enhance the releasability of the insulating film 30 from the element main body 14, a release agent 36 is applied to the interface between the element main body 14 and the insulating film 30 as shown in FIG. Is also good. As the release agent 36, for example, it is conceivable to use an epoxy-containing olefin resin.
However, the bonding strength between the insulating film 30 and the element main body 14 is such that the insulating film 30 does not
It is configured to maintain a strength that does not cause peeling. However, in a case where the peeling force is intentionally applied by applying a peeling force as described later, the insulating film 30 is attached to the element body 1.
4 to be peeled off. Note that the above insulating film 3
As 0, it is also possible to use a polyimide containing epoxy instead of the olefin resin containing epoxy.
【００３０】スルーホール電極２０及び配線２２は、前
記した電極接続手段として機能するものであり、第１の
電極１６と第２の電極１８を電気的に接続する機能を奏
するものである。スルーホール電極２０は絶縁膜３０に
上下に貫通形成された孔の内部に導電膜を形成した構成
とされており、よって絶縁膜３０の上面と下面を電気的
に接続する機能を有している。このスルーホール電極２
０は、絶縁膜３０の第１の電極１６と対向する位置に夫
々形成されている。The through-hole electrode 20 and the wiring 22 function as the above-described electrode connection means, and have a function of electrically connecting the first electrode 16 and the second electrode 18. The through-hole electrode 20 has a structure in which a conductive film is formed inside a hole vertically formed through the insulating film 30, and thus has a function of electrically connecting the upper surface and the lower surface of the insulating film 30. . This through-hole electrode 2
Numerals 0 are formed on the insulating film 30 at positions facing the first electrodes 16 respectively.
【００３１】また、配線２２は、絶縁膜３０の上面に所
定のパターンで形成されている。この配線２２の一端は
第２の電極１８に接続されており、また他端は前記した
スルーホール電極２０の上端部に電気的に接続された構
成とされている。図１に示されるように、配線２２は第
１の電極１６と第２の電極１８とを接続する機能を奏し
ている。よって、第１の電極１６と第２の電極１８と
は、上記のスルーホール電極２０及び配線２２により、
一対一の対応で電気的に接続された構成となっている。
具体例としては、第１の電極１６ａはスルーホール電極
２０ａ及び配線２２ａにより第２の電極１８ａに接続さ
れた構成となっており、これにより第１の電極１６ａと
第２の電極１８ａとは対応して接続された構成となって
いる。The wiring 22 is formed on the upper surface of the insulating film 30 in a predetermined pattern. One end of the wiring 22 is connected to the second electrode 18, and the other end is electrically connected to the upper end of the through-hole electrode 20. As shown in FIG. 1, the wiring 22 has a function of connecting the first electrode 16 and the second electrode 18. Therefore, the first electrode 16 and the second electrode 18 are connected by the through-hole electrode 20 and the wiring 22 described above.
They are electrically connected in a one-to-one correspondence.
As a specific example, the first electrode 16a is configured to be connected to the second electrode 18a by the through-hole electrode 20a and the wiring 22a, so that the first electrode 16a corresponds to the second electrode 18a. And connected.
【００３２】上記したスルーホール電極２０及び配線２
２は、半導体製造技術として確立した周知の方法により
形成することができる。また、第１の電極１６と第２の
電極１８は、スルーホール電極２０と配線２２とよりな
る電気的接続手段により接続されるため、簡単な構成で
各電極１６，１８を電気的に接続することができる。こ
こで、図１に示される半導体装置１２Ａに注目する。The above-described through-hole electrode 20 and wiring 2
2 can be formed by a well-known method established as a semiconductor manufacturing technique. Further, since the first electrode 16 and the second electrode 18 are connected by the electrical connection means including the through-hole electrode 20 and the wiring 22, the electrodes 16 and 18 are electrically connected with a simple configuration. be able to. Here, attention is focused on the semiconductor device 12A shown in FIG.
【００３３】半導体装置１２Ａは、絶縁膜３０が配設さ
れた状態の半導体素子１０が搭載されたものである。こ
の半導体装置１２Ａは、図６に示されるような横長パッ
ケージ構造を有した半導体装置である。よって、樹脂パ
ッケージ２８Ａは横長なパッケージ構造とされており、
リード２４は樹脂パッケージ２８Ａの短辺側から外部に
延出する構成となっている。The semiconductor device 12A has the semiconductor element 10 on which the insulating film 30 is provided. This semiconductor device 12A is a semiconductor device having a horizontally long package structure as shown in FIG. Therefore, the resin package 28A has a horizontally long package structure.
The lead 24 is configured to extend outside from the short side of the resin package 28A.
【００３４】また、横長パッケージ構造に半導体素子１
０を搭載する場合、樹脂パッケージ２８Ａ内に無駄な空
間部の発生を抑制する面から、半導体素子１０も横長と
なる向きで搭載される。このように横長となるよう半導
体素子１０を樹脂パッケージ２８Ａに搭載した場合、各
リード２４は半導体素子１０の短辺側と対向した状態と
なる。Further, the semiconductor device 1 has a horizontally long package structure.
In the case where 0 is mounted, the semiconductor element 10 is also mounted in a horizontally long orientation in order to suppress the generation of useless spaces in the resin package 28A. When the semiconductor element 10 is mounted on the resin package 28A so as to be horizontally long, each lead 24 is in a state of facing the short side of the semiconductor element 10.
【００３５】本実施例に係る半導体素子１０は、絶縁膜
３０が配設された状態では、第２の電極１８が最上面に
位置した状態となっており、よって外部との電気的接続
が可能な状態となっている。また、本実施例では第２の
電極１８は、素子本体１４の短辺に沿った状態で形成さ
れた構成とされている。従って、第２の電極１８とリー
ド２４とをワイヤ２６で接続することにより、リード２
４は第２の電極１８，配線２２，スルーホール２０，及
び第１の電極１６を介して半導体素子１４に電気的に接
続された状態となる。この際、第２の電極１８とリード
２４とは対向した状態となっているため、第２の電極１
８とリード２４との離間距離は短くなる。このため、半
導体装置１２Ａの小型化を図ることができ、またワイヤ
長も短くすることができるため、ワイヤ２６で発生する
電気的損失を低減することができる。In the semiconductor device 10 according to the present embodiment, the second electrode 18 is located on the uppermost surface when the insulating film 30 is provided, so that the semiconductor device 10 can be electrically connected to the outside. It is in a state. In this embodiment, the second electrode 18 is formed along the short side of the element body 14. Therefore, by connecting the second electrode 18 and the lead 24 with the wire 26, the lead 2
4 is in a state of being electrically connected to the semiconductor element 14 via the second electrode 18, the wiring 22, the through hole 20, and the first electrode 16. At this time, since the second electrode 18 and the lead 24 face each other, the second electrode 1
The distance between the lead 8 and the lead 24 becomes shorter. Therefore, the semiconductor device 12A can be reduced in size and the wire length can be shortened, so that the electric loss generated in the wire 26 can be reduced.
【００３６】続いて、図２に示される半導体装置１２Ｂ
に注目する。半導体装置１２Ｂは、絶縁膜３０が剥離さ
れた状態の半導体素子１０が搭載されたものである。こ
こで、半導体装置１２Ｂの構成説明に先立ち、絶縁膜３
０を素子本体１４から剥離する方法について図４及び図
５を用いて説明する。図４は、機械的手段により絶縁膜
３０を素子本体１４から剥離する方法を示している。こ
こで、機械的手段とは、絶縁膜３０に剥離力を印加する
ことにより剥離を行なうことをいう。Subsequently, the semiconductor device 12B shown in FIG.
Pay attention to. The semiconductor device 12B has the semiconductor element 10 from which the insulating film 30 has been peeled off. Here, prior to the description of the configuration of the semiconductor device 12B, the insulating film 3
A method of peeling 0 from the element body 14 will be described with reference to FIGS. FIG. 4 shows a method of peeling the insulating film 30 from the element body 14 by mechanical means. Here, the mechanical means refers to performing separation by applying a separation force to the insulating film 30.
【００３７】具体的には、本実施例では絶縁膜３０の端
部（図示の例では右端部）を治具等を用いて把持し、こ
れを上方に持ち上げる処理を行なう。この際、前記した
ように絶縁膜３０はエポキシ含有のオレフィン系樹脂に
より形成されているため、エポキシ樹脂の分解温度以上
に加熱することで離型作用を発揮する。よって、剥離作
業はエポキシ樹脂の分解温度以上に加熱した環境下にお
いて実施され、これにより容易に絶縁膜３０を素子本体
１４から剥離することができる。また、素子本体１４と
絶縁膜３０との界面に剥離剤３６を塗布した構成では、
更に容易に絶縁膜３０を素子本体１４から剥離すること
ができる。More specifically, in this embodiment, a process is performed in which the end portion (the right end portion in the illustrated example) of the insulating film 30 is gripped using a jig or the like and lifted upward. At this time, since the insulating film 30 is formed of an epoxy-containing olefin-based resin as described above, the insulating film 30 exerts a mold releasing effect when heated to a temperature higher than the decomposition temperature of the epoxy resin. Therefore, the stripping operation is performed in an environment heated to a temperature equal to or higher than the decomposition temperature of the epoxy resin, whereby the insulating film 30 can be easily stripped from the element body 14. In the configuration in which the release agent 36 is applied to the interface between the element body 14 and the insulating film 30,
Further, the insulating film 30 can be easily peeled off from the element body 14.
【００３８】図５は、化学的手段により絶縁膜３０を素
子本体１４から剥離する方法を示している。ここで、化
学的手段とは、上記したような外力（剥離力）を絶縁膜
３０に直接印加することなく、化学反応を利用して絶縁
膜３０を素子本体１４から剥離する方法をいう。具体的
には、本実施例ではエッチング法を用いて絶縁膜３０を
除去する方法を採用している。即ち、エッチング液３４
として、第２の電極１８，配線２２，及び絶縁膜３０に
ついては溶解するが、素子本体１４及び第１の電極１６
については溶解作用を及ぼさないものを選定する。よっ
て、このエッチング液３４を用いてエッチングすること
により、絶縁膜３０を素子本体１４から剥離（除去）す
ることができる。FIG. 5 shows a method of peeling the insulating film 30 from the element body 14 by chemical means. Here, the chemical means refers to a method in which the insulating film 30 is separated from the element body 14 using a chemical reaction without directly applying the above-described external force (peeling force) to the insulating film 30. Specifically, in this embodiment, a method of removing the insulating film 30 by using an etching method is employed. That is, the etching solution 34
As a result, the second electrode 18, the wiring 22, and the insulating film 30 are dissolved, but the element body 14 and the first electrode 16 are dissolved.
Is selected that does not exert a dissolving effect. Therefore, the insulating film 30 can be peeled (removed) from the element body 14 by etching using the etching solution 34.
【００３９】上記のように、絶縁部材３０を機械的手段
或いは化学的手段を用いて素子本体１４から剥離させる
方法を採用したことにより、比較的簡単な設備で容易に
絶縁部材３０を素子本体１４から剥離させることができ
る。また、前記のようにスルーホール電極２０及び配線
２２は、いずれも絶縁部材３０に配設されているため、
絶縁部材３０を素子本体１４から剥離し排除することに
より、スルーホール電極２０及び配線２２も併せて排除
される。よって、絶縁部材３０を素子本体１４から剥離
した後に、これらが第１の電極１６とリード２４との接
続に悪影響を及ぼすようなことはない。As described above, by adopting a method in which the insulating member 30 is separated from the element main body 14 by using a mechanical means or a chemical means, the insulating member 30 can be easily removed with relatively simple equipment. Can be peeled off. Further, as described above, since both the through-hole electrode 20 and the wiring 22 are provided on the insulating member 30,
By peeling and removing the insulating member 30 from the element body 14, the through-hole electrode 20 and the wiring 22 are also removed. Therefore, after the insulating member 30 is peeled off from the element body 14, they do not adversely affect the connection between the first electrode 16 and the lead 24.
【００４０】ここで、再び図２に戻り、半導体装置１２
Ｂについて説明する。半導体装置１２Ｂは、図７に示さ
れるような縦長パッケージ構造を有した半導体装置であ
る。よって、樹脂パッケージ２８Ｂも縦長なパッケージ
構造とされており、リード２４は樹脂パッケージ２８Ｂ
の長辺側から外部に延出する構成となっている。Here, returning to FIG.
B will be described. The semiconductor device 12B is a semiconductor device having a vertically long package structure as shown in FIG. Accordingly, the resin package 28B also has a vertically long package structure, and the leads 24 are formed of the resin package 28B.
Is extended from the long side to the outside.
【００４１】また、縦長パッケージ構造に半導体素子１
０を搭載する場合、樹脂パッケージ２８Ｂ内に無駄な空
間部の発生を抑制する面から、半導体素子１０も縦長と
なる向きで搭載される。このように縦長となるよう半導
体素子１０を樹脂パッケージ２８Ａに搭載した場合、各
リード２４は半導体素子１０の長辺側と対向した状態と
なる。Further, the semiconductor element 1 has a vertical package structure.
In the case where 0 is mounted, the semiconductor element 10 is also mounted in a vertically elongated direction from the viewpoint of suppressing generation of useless spaces in the resin package 28B. When the semiconductor element 10 is mounted on the resin package 28A so as to be vertically elongated, each lead 24 is in a state of facing the long side of the semiconductor element 10.
【００４２】本実施例に係る半導体素子１０は、上記の
ように絶縁膜３０が剥離（除去）されているため、第１
の電極１６が素子本体１４上に露出した状態となってい
る。また、本実施例では第１の電極１６は、素子本体１
４の長辺に沿った状態で形成された構成とされている。
従って、第１の電極１６とリード２４とをワイヤ２６で
直接接続することが可能となり、ワイヤ２６を接続した
状態でリード２４と半導体素子１０は電気的に接続され
た状態となる。この際、半導体装置１２Ｂにおいても、
第１の電極１６とリード２４とは対向した状態となって
いるため、第１の電極１６とリード２４との離間距離は
短くなり、半導体装置１２Ｂの小型化を図ることができ
る。また、ワイヤ長も短くすることができるため、ワイ
ヤ２６で発生する電気的損失を低減することができる。In the semiconductor device 10 according to the present embodiment, since the insulating film 30 is peeled (removed) as described above, the first
The electrodes 16 are exposed on the element body 14. In this embodiment, the first electrode 16 is connected to the element body 1.
4 is formed along the long side.
Therefore, it is possible to directly connect the first electrode 16 and the lead 24 with the wire 26, and the lead 24 and the semiconductor element 10 are electrically connected with the wire 26 connected. At this time, also in the semiconductor device 12B,
Since the first electrode 16 and the lead 24 are opposed to each other, the distance between the first electrode 16 and the lead 24 is reduced, and the size of the semiconductor device 12B can be reduced. Further, since the wire length can be shortened, the electric loss generated in the wire 26 can be reduced.
【００４３】上記のように、本実施例に係る半導体素子
１０では、素子本体１４上には第１の電極１６が形成さ
れ、またこの素子本体１４上に形成された絶縁膜３０上
には第２の電極１８が形成される。よって、第１の電極
１６と第２の電極１８は絶縁膜３０を介して積層された
構成となり、第１及び第２の電極１６，１８を設けても
素子本体１４の面積が増大することはなく小型化を図る
ことができる。As described above, in the semiconductor element 10 according to the present embodiment, the first electrode 16 is formed on the element body 14, and the first electrode 16 is formed on the insulating film 30 formed on the element body 14. Two electrodes 18 are formed. Therefore, the first electrode 16 and the second electrode 18 are stacked with the insulating film 30 interposed therebetween, and even if the first and second electrodes 16 and 18 are provided, the area of the element main body 14 does not increase. Therefore, the size can be reduced.
【００４４】また、図１及び図３に示す例では、説明及
び図示の便宜上、第１の電極１６と第２の電極１８とが
上下方向に重ならない構成としたが、第１の電極１６と
第２の電極１８とを重ねて形成することも可能であり、
この場合には更に半導体素子１０の小型化を図ることが
できる。また、上記説明から明らかなように、本実施例
に係る半導体素子１０は、絶縁膜３０が配設された状態
と、絶縁膜３０が素子本体１４から剥離された状態と
で、電極１６，１８の配設形態を異ならせることができ
る。In the examples shown in FIGS. 1 and 3, the first electrode 16 and the second electrode 18 do not overlap in the vertical direction for convenience of explanation and illustration. The second electrode 18 can be formed so as to overlap with the second electrode 18.
In this case, the size of the semiconductor element 10 can be further reduced. Further, as is apparent from the above description, the semiconductor element 10 according to the present embodiment has the electrodes 16 and 18 in a state where the insulating film 30 is provided and in a state where the insulating film 30 is peeled off from the element body 14. Can be made different.
【００４５】よって、パッケージ構造に応じて電極１
６，１８の形成位置を変更する必要がある場合であって
も、絶縁膜３０をそのまま配設した状態にするか、或い
は絶縁膜３０を素子本体１４から剥離するのみで容易に
パッケージ構造に対応した電極形態を実現することがで
きる。これにより、従来のように顧客からの受注に対応
すべく見込み製造を行なう必要はなくなり、半導体装置
１２Ａ，１２Ｂの在庫管理を容易に行なうことができ
る。Therefore, depending on the package structure, the electrode 1
Even if it is necessary to change the formation positions of 6, 18, it is possible to easily adapt to the package structure by leaving the insulating film 30 as it is or simply peeling the insulating film 30 from the element body 14. Electrode configuration can be realized. As a result, unlike the conventional case, it is not necessary to perform prospective manufacturing in order to respond to an order from a customer, and inventory management of the semiconductor devices 12A and 12B can be easily performed.
【００４６】尚、上記した実施例では、絶縁膜３０を単
層した構成を例に挙げて説明したが、絶縁部材を多層構
造とすることも可能である。このように、絶縁部材を多
層構造とした場合、各層間に内層配線を形成することが
できる。この構成では、各層毎に電極の配設形態を設定
できるため、複数のパッケージ形態（即ち、電極の配設
形態）に容易に対応することが可能となる。具体的に
は、絶縁部材が５層構造であり、その３層目に所望する
配設形態で電極が形成されていた場合には、上部の２層
のみを剥離させることにより、所望の電極の配設形態を
実現することができる。In the above-described embodiment, the configuration in which the insulating film 30 has a single layer has been described as an example. However, the insulating member may have a multilayer structure. As described above, when the insulating member has a multilayer structure, an inner layer wiring can be formed between the respective layers. In this configuration, since the arrangement of the electrodes can be set for each layer, it is possible to easily cope with a plurality of package forms (that is, the arrangement of the electrodes). Specifically, when the insulating member has a five-layer structure and an electrode is formed in a desired arrangement on the third layer, only the upper two layers are peeled off to form a desired electrode. An arrangement form can be realized.
【００４７】[0047]
【発明の効果】上述の如く本発明によれば、次に述べる
種々の効果を実現することができる。請求項１記載の発
明によれば、第１の電極と第２の電極は絶縁部材を介し
て積層された構成となり、第１及び第２の電極を設けて
も素子本体の面積が増大することはなく小型化を図るこ
とができる。According to the present invention as described above, the following various effects can be realized. According to the first aspect of the present invention, the first electrode and the second electrode are laminated with an insulating member interposed therebetween, and the area of the element body increases even if the first and second electrodes are provided. And the size can be reduced.
【００４８】また、絶縁部材が配設された状態と絶縁部
材が素子本体から剥離された状態とで電極の配設形態を
異ならせることができるため、パッケージ構造に応じて
電極の形成位置を変更する必要がある場合であっても、
絶縁部材をそのまま配設した状態にするか、或いは絶縁
部材を素子本体から剥離するのみで容易にパッケージ構
造に対応した電極形態を実現することができる。Further, the arrangement of the electrodes can be made different between the state in which the insulating member is provided and the state in which the insulating member is peeled off from the element main body. Therefore, the electrode forming position is changed according to the package structure. Even if you need to
The electrode configuration corresponding to the package structure can be easily realized simply by keeping the insulating member as it is or by simply peeling the insulating member from the element body.
【００４９】また、請求項２記載の発明によれば、絶縁
部材が配設された状態においては、簡単な構成で第１の
電極と第２の電極を電気的に接続することができる。ま
た、絶縁部材を素子本体から剥離し排除することにより
電気的接続手段も併せて排除されるため、絶縁部材を素
子本体から剥離した後において、電気的接続手段が第１
の電極と外部端子との接続に悪影響を及ぼすようなこと
はない。According to the second aspect of the present invention, in a state where the insulating member is provided, the first electrode and the second electrode can be electrically connected with a simple configuration. Further, since the insulating member is peeled off from the element main body and the electrical connection means is also eliminated, the electric connection means is removed after the insulating member is peeled off from the element main body.
There is no adverse effect on the connection between the electrode and the external terminal.
【００５０】また、請求項３記載の発明によれば、各層
毎に電極の配設形態を設定できるため、複数のパッケー
ジ形態（即ち、電極の配設形態）に容易に対応すること
ができる。また、請求項４及び請求項５記載の発明によ
れば、絶縁部材を素子本体から剥離する処理を容易に行
なうことができる。According to the third aspect of the present invention, the arrangement of the electrodes can be set for each layer, so that it is possible to easily cope with a plurality of packages (that is, the arrangement of the electrodes). According to the fourth and fifth aspects of the present invention, the process of peeling the insulating member from the element body can be easily performed.
【００５１】また、請求項６または請求項７記載の発明
によれば、比較的簡単な設備で容易に絶縁部材を素子本
体から剥離させることができる。また、請求項８記載の
発明に係る半導体装置によれば、半導体素子とリードと
の離間距離を最小距離とすることができ、電気的損失の
発生を抑制することができると共に、電極の配設形態が
パッケージ構造に対応しているため半導体装置の小型化
を図ることができる。According to the invention described in claim 6 or claim 7, the insulating member can be easily separated from the element body by relatively simple equipment. Further, according to the semiconductor device of the present invention, the separation distance between the semiconductor element and the lead can be minimized, electric loss can be suppressed, and the arrangement of the electrodes can be suppressed. Since the mode corresponds to the package structure, the size of the semiconductor device can be reduced.
【図１】本発明の一実施例である半導体素子を搭載した
半導体装置を示す図であり、電極が第１の配設形態であ
る状態を示す図である。FIG. 1 is a view showing a semiconductor device on which a semiconductor element according to one embodiment of the present invention is mounted, and is a view showing a state where electrodes are in a first arrangement mode.
【図２】本発明の一実施例である半導体素子を搭載した
半導体装置を示す図であり、電極が第２の配設形態であ
る状態を示す図である。FIG. 2 is a diagram showing a semiconductor device on which a semiconductor element according to one embodiment of the present invention is mounted, and is a diagram showing a state where electrodes are in a second arrangement mode.
【図３】電極が第１の配設形態である状態の半導体素子
の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device in a state where electrodes are in a first arrangement mode.
【図４】絶縁膜を機械的手段により剥離する方法を説明
するための図である。FIG. 4 is a view for explaining a method of peeling an insulating film by mechanical means.
【図５】絶縁膜を化学的手段により剥離する方法を説明
するための図である。FIG. 5 is a view for explaining a method of removing an insulating film by a chemical means.
【図６】横長パッケージを説明するための図である。FIG. 6 is a diagram for explaining a horizontally long package.
【図７】縦長パッケージを説明するための図である。FIG. 7 is a view for explaining a vertically long package.
【図８】従来の半導体素子の一例を説明するための図で
ある。FIG. 8 is a diagram illustrating an example of a conventional semiconductor device.
【図９】従来の半導体素子の一例を説明するための図で
ある。FIG. 9 is a diagram illustrating an example of a conventional semiconductor device.
１０ 半導体素子 １２Ａ，１２Ｂ 半導体装置 １４， 素子本体 １６ 第１の電極 １８ 第２の電極 ２０ スルーホール ２２ 配線 ２４ リード ２６ ワイヤ ２８Ａ，２８Ｂ 樹脂パッケージ ３０ 絶縁膜 ３２ 回路形成領域 ３４ エッチング液 ３６ 剥離剤 DESCRIPTION OF SYMBOLS 10 Semiconductor element 12A, 12B Semiconductor device 14, Element main body 16 First electrode 18 Second electrode 20 Through hole 22 Wiring 24 Lead 26 Wire 28A, 28B Resin package 30 Insulating film 32 Circuit formation area 34 Etching solution 36 Release agent
フロントページの続き (72)発明者 藤井 康宏 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 鎌田 心之介 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 柳沢 誠 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 山田 豊修 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 松岡 正巳 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 富田 浩由 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内Continued on the front page (72) Inventor Yasuhiro Fujii 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shinnosuke Kamata 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (72) Inventor Makoto Yanagisawa 4-1-1 Kamiodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Limited (72) Inventor Toyoyoshi Yamada 4-1-1 Kamiodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Co., Ltd. (72) Inventor Masami Matsuoka 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture 1 Fujitsu Co., Ltd. No. 1 in Fujitsu Limited
Claims (8)
の電極と、 前記表面を覆うように形成されると共に、前記素子本体
に対し剥離可能な構成で配設された絶縁部材と、 該絶縁部材上に前記第１の配置形態と異なる第２の配置
形態で形成された第２の電極と、 前記絶縁部材が前記素子本体に配設された状態において
前記第１の電極と第２の電極とを電気的に接続する電極
接続手段と、を具備することを特徴とする半導体素子。An element body on which an electronic circuit is formed, and a first body formed in a first arrangement on a surface of the element body.
And an insulating member formed so as to cover the surface and arranged in a releasable manner with respect to the element body, and a second arrangement different from the first arrangement form on the insulating member A second electrode formed in a form, and electrode connection means for electrically connecting the first electrode and the second electrode in a state where the insulating member is provided in the element body. A semiconductor element characterized by the above-mentioned.
する位置に形成されたスルーホール電極と、 前記絶縁部材に形成されており、一端が前記第２の電極
に接続すると共に、他端が前記スルーホール電極に接続
された配線と、により構成されることを特徴とする半導
体素子。2. The semiconductor element according to claim 1, wherein the electrode connecting means is formed on the insulating member, and a through-hole electrode formed at a position facing the first electrode; And a wiring having one end connected to the second electrode and the other end connected to the through-hole electrode.
いて、 前記絶縁部材を多層構造とし、各層間に内層配線を形成
したことを特徴とする半導体素子。3. The semiconductor device according to claim 1, wherein said insulating member has a multilayer structure, and an inner layer wiring is formed between each layer.
体素子において、 前記絶縁部材と前記素子本体との間に、剥離を容易とす
るための剥離剤が配設されていることを特徴とする半導
体素子。4. The semiconductor element according to claim 1, wherein a release agent for facilitating release is provided between the insulating member and the element body. Semiconductor element.
体素子において、 前記絶縁部材の材質として、前記素子本体に対し接着性
の低い材質を選定したことを特徴とする半導体素子。5. The semiconductor element according to claim 1, wherein a material having low adhesiveness to the element body is selected as a material of the insulating member.
体素子において、前記素子本体から前記絶縁部材を剥離
することにより電極形態を変更する半導体素子の電極形
態変更方法であって、 前記絶縁部材を機械的手段を用いて前記素子本体から剥
離させることを特徴とする半導体素子の電極形態変更方
法。6. The method according to claim 1, wherein said insulating member is separated from said element body to change an electrode form of said semiconductor element. A method of changing an electrode configuration of a semiconductor device, comprising separating a member from the device body by using mechanical means.
体素子において、前記素子本体から前記絶縁部材を剥離
することにより電極形態を変更する半導体素子の電極形
態変更方法であって、 前記絶縁部材を化学的手段を用いて前記素子本体から剥
離させることを特徴とする半導体素子の電極形態変更方
法。7. The method according to claim 1, wherein said insulating member is separated from said element body to change an electrode form of said semiconductor element. A method for changing an electrode configuration of a semiconductor device, wherein the member is separated from the device main body using chemical means.
体素子と、 前記半導体素子と電気的に接続されたリードと、 前記半導体素子を封止するパッケージとを具備すること
を特徴とする半導体装置。8. A semiconductor device according to claim 1, comprising: a lead electrically connected to the semiconductor device; and a package for sealing the semiconductor device. Semiconductor device.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15528797A JP3705896B2 (en) | 1997-06-12 | 1997-06-12 | SEMICONDUCTOR ELEMENT, ELECTRODE FORM CHANGE METHOD, AND SEMICONDUCTOR DEVICE |
| US09/030,349 US6063640A (en) | 1997-03-18 | 1998-02-25 | Semiconductor wafer testing method with probe pin contact |
| TW087103831A TW393710B (en) | 1997-03-18 | 1998-03-16 | Semiconductor wafer testing method with improved probe pin contact |
| KR1019980009068A KR100294396B1 (en) | 1997-03-18 | 1998-03-17 | Semiconductor wafer inspection method with improved probe pin contact |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15528797A JP3705896B2 (en) | 1997-06-12 | 1997-06-12 | SEMICONDUCTOR ELEMENT, ELECTRODE FORM CHANGE METHOD, AND SEMICONDUCTOR DEVICE |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH113908A true JPH113908A (en) | 1999-01-06 |
| JP3705896B2 JP3705896B2 (en) | 2005-10-12 |
Family
ID=15602609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15528797A Expired - Lifetime JP3705896B2 (en) | 1997-03-18 | 1997-06-12 | SEMICONDUCTOR ELEMENT, ELECTRODE FORM CHANGE METHOD, AND SEMICONDUCTOR DEVICE |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3705896B2 (en) |
-
1997
- 1997-06-12 JP JP15528797A patent/JP3705896B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP3705896B2 (en) | 2005-10-12 |
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