JPH11355139A - Frequency synthesizer - Google Patents

Frequency synthesizer

Info

Publication number
JPH11355139A
JPH11355139A JP10162168A JP16216898A JPH11355139A JP H11355139 A JPH11355139 A JP H11355139A JP 10162168 A JP10162168 A JP 10162168A JP 16216898 A JP16216898 A JP 16216898A JP H11355139 A JPH11355139 A JP H11355139A
Authority
JP
Japan
Prior art keywords
signal
frequency
output
gain
outputting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10162168A
Other languages
Japanese (ja)
Inventor
Masaru Sakamoto
大 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP10162168A priority Critical patent/JPH11355139A/en
Publication of JPH11355139A publication Critical patent/JPH11355139A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To prevent the power level of an output signal from being fluctuated by a frequency because the gain of an amplifier is provided with a frequency characteristic. SOLUTION: A frequency synthesizer is provided with a voltage control oscillator 1 outputting a frequency signal corresponding to a control voltage signal, a gain control amplifier 6 outputting an output signal obtained by amplifying the frequency signal through the use of gain corresponding to a gain control signal, a variable frequency divider 2 outputting a frequency dividing signal obtained by frequency-dividing the frequency signal by a frequency dividing ratio corresponding to an output frequency control signal, a phase comparator 3 outputting a pulse signal corresponding to phase difference between the frequency dividing signal and a reference frequency signal, a loop filter 4 converting the pulse signal and outputting it as a control voltage signal and a gain control signal generating circuit 9 consisting of a memory 7 outputting a digital signal corresponding to the output frequency control signal and of a digital/analog converter 8 outputting an analog signal corresponding to the digital signal as the gain control signal. By the configuration, the power level of the output signal is not fluctuated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は携帯電話等の無線通
信装置に使用される周波数シンセサイザに関し、特に出
力信号の電力レベルの変動を改善した周波数シンセサイ
ザに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used for a wireless communication device such as a portable telephone, and more particularly to a frequency synthesizer in which the fluctuation of the power level of an output signal is improved.

【0002】[0002]

【従来の技術】携帯電話等の無線通信装置に使用される
周波数シンセサイザは、希望する任意の周波数の信号を
発生するために用いられ、従来より、入力される制御電
圧信号の電圧に応じてその出力である周波数信号の周波
数を制御可能なVCO(Voltage Controlled Oscillato
r :電圧制御発振器)と、VCOからの周波数信号の一
部が入力され、その信号を所定の分周比で分周した分周
信号を出力する可変分周器およびこの分周信号と外部回
路から入力される基準周波数信号との位相を比較してそ
の位相差に応じたパルス信号を出力する位相比較器より
なるPLL(Phase Locked Loop )回路と、このPLL
回路の位相比較器からのパルス信号が入力され、VCO
を制御する制御電圧信号を出力するループフィルタとか
ら構成されている。
2. Description of the Related Art A frequency synthesizer used in a radio communication device such as a cellular phone is used to generate a signal of a desired arbitrary frequency, and conventionally, the frequency synthesizer is used in accordance with a voltage of a control voltage signal inputted. VCO (Voltage Controlled Oscillato) that can control the frequency of the output frequency signal
r: a voltage controlled oscillator), a variable frequency divider to which a part of a frequency signal from the VCO is input, and to output a frequency-divided signal obtained by dividing the signal by a predetermined frequency-dividing ratio, and a frequency-divided signal and an external circuit (Phase Locked Loop) circuit comprising a phase comparator for comparing a phase with a reference frequency signal input from the phase comparator and outputting a pulse signal corresponding to the phase difference, and the PLL
The pulse signal from the phase comparator of the circuit is input and the VCO
And a loop filter that outputs a control voltage signal for controlling the voltage.

【0003】これにより、外部回路から周波数シンセサ
イザに入力される基準周波数信号の周波数に応じて希望
する周波数の周波数信号を合成して、VCOから出力信
号として出力される。
[0003] Thus, a frequency signal of a desired frequency is synthesized according to the frequency of a reference frequency signal input from an external circuit to a frequency synthesizer, and output as an output signal from the VCO.

【0004】また、周波数シンセサイザからの出力信号
についてその出力信号を受ける外部回路が要求する電力
レベルを確保するため、通常は周波数シンセサイザ外部
への出力部であるVCOには増幅器が接続されて、出力
信号の電力レベルの増幅が行なわれる。
In order to secure a power level required by an external circuit receiving the output signal from the frequency synthesizer, an amplifier is usually connected to the VCO which is an output unit to the outside of the frequency synthesizer. The power level of the signal is amplified.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記の
ような従来の周波数シンセサイザにおいては、VCOの
出力である周波数信号を増幅する増幅器の利得が周波数
特性を持っており、入力される信号の周波数が高くなる
につれて増幅度が低下してしまうため、周波数シンセサ
イザからの出力信号の電力レベルがその周波数によって
変動してしまうという問題点があった。
However, in the conventional frequency synthesizer as described above, the gain of the amplifier for amplifying the frequency signal output from the VCO has a frequency characteristic, and the frequency of the input signal is low. Since the amplification degree decreases as the frequency increases, the power level of the output signal from the frequency synthesizer fluctuates depending on the frequency.

【0006】このため、周波数が低い場合の周波数シン
セサイザの出力信号の電力レベルに合わせてその出力を
受ける外部回路を設計すると、出力信号の周波数が高く
なった場合に電力レベルの不足を引き起こし、設計通り
の性能を得ることができなくなるという問題点があっ
た。
For this reason, if an external circuit receiving the output is designed in accordance with the power level of the output signal of the frequency synthesizer when the frequency is low, the power level becomes insufficient when the frequency of the output signal increases, resulting in a design failure. There was a problem that it was not possible to obtain the same performance.

【0007】また、周波数シンセサイザの出力信号の周
波数が高い場合の電力レベルに合わせてその出力を受け
る外部回路を設計した場合には、出力信号の周波数が低
くなった場合にその外部回路に対して過大な電力レベル
の入力を行なうこととなり、入力信号のひずみや不要波
の発生を引き起こす結果となるという問題点もあった。
When an external circuit receiving the output is designed in accordance with the power level when the frequency of the output signal of the frequency synthesizer is high, when the frequency of the output signal becomes low, the external circuit is There is also a problem that the input of an excessive power level results in distortion of the input signal and generation of unnecessary waves.

【0008】本発明は上記従来技術における問題点に鑑
みて案出されたものであり、その目的は、周波数シンセ
サイザの出力信号について周波数による電力レベルの変
動をなくし、安定した所望の電力レベルの出力信号を得
ることができる周波数シンセサイザを提供することにあ
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the prior art, and has as its object to eliminate fluctuations in power level due to frequency of an output signal of a frequency synthesizer and to provide a stable output of a desired power level. An object of the present invention is to provide a frequency synthesizer capable of obtaining a signal.

【0009】[0009]

【課題を解決するための手段】本発明の周波数シンセサ
イザは、制御電圧信号が入力され、その電圧に応じて周
波数を制御した周波数信号を出力する電圧制御発振器
と、前記周波数信号と利得制御信号とが入力され、利得
制御信号に応じた利得で周波数信号を増幅した出力信号
を出力する利得制御増幅器と、前記周波数信号の一部と
出力周波数制御信号とが入力され、出力周波数制御信号
に応じた分周比で周波数信号を分周した分周信号を出力
する可変分周器と、前記分周信号と基準周波数信号とが
入力され、両信号の位相差に応じたパルス信号を出力す
る位相比較器と、前記パルス信号を直流電圧信号に変換
して前記制御電圧信号として出力するループフィルタ
と、前記出力周波数制御信号の一部が入力され、それに
対応したデジタル信号を出力するメモリおよび前記デジ
タル信号に応じた電圧のアナログ信号を前記利得制御信
号として出力するデジタル/アナログ変換器からなる利
得制御信号発生回路とを具備することを特徴とするもの
であり、周波数シンセサイザの出力信号の周波数に応じ
てその増幅器の利得すなわち増幅度を変化させることを
可能とすることにより上記課題を解決するものである。
According to the present invention, there is provided a frequency synthesizer, comprising: a voltage controlled oscillator to which a control voltage signal is input and which outputs a frequency signal whose frequency is controlled according to the voltage; Is input, a gain control amplifier that outputs an output signal obtained by amplifying a frequency signal with a gain according to the gain control signal, and a part of the frequency signal and an output frequency control signal are input, and the A variable frequency divider that outputs a frequency-divided signal obtained by dividing a frequency signal by a frequency division ratio; and a phase comparison that receives the frequency-divided signal and a reference frequency signal and outputs a pulse signal corresponding to a phase difference between the two signals. And a loop filter that converts the pulse signal into a DC voltage signal and outputs the DC voltage signal as the control voltage signal; And a gain control signal generating circuit comprising a digital / analog converter for outputting an analog signal having a voltage corresponding to the digital signal as the gain control signal. An object of the present invention is to solve the above problem by making it possible to change the gain of the amplifier, that is, the degree of amplification according to the frequency of the output signal.

【0010】[0010]

【発明の実施の形態】本発明の周波数シンセサイザによ
れば、外部回路からPLL回路の可変分周器に入力され
る出力周波数制御信号の一部をそれに対応したデジタル
信号を出力するメモリおよびそのデジタル信号に応じた
電圧のアナログ信号を利得制御増幅器への利得制御信号
として出力するデジタル/アナログ変換器からなる利得
制御信号発生回路を備え、その利得制御信号を電圧制御
発振器からの周波数信号を増幅する利得制御増幅器に入
力して利得制御を行なうようにしたことから、出力周波
数制御信号によって設定される周波数シンセサイザの出
力信号の周波数に応じてその増幅度を変化させることが
可能となり、出力信号の周波数が変わってもその電力レ
ベルの変動をなくすことができ、安定した所望の電力レ
ベルの出力信号を得ることができるものとなる。
According to the frequency synthesizer of the present invention, a memory for outputting a digital signal corresponding to a part of an output frequency control signal inputted from an external circuit to a variable frequency divider of a PLL circuit, and a digital synthesizer for the memory are provided. A gain control signal generating circuit comprising a digital / analog converter for outputting an analog signal having a voltage corresponding to the signal as a gain control signal to a gain control amplifier, and amplifying the gain control signal to a frequency signal from a voltage controlled oscillator Since the gain control is performed by inputting to the gain control amplifier, the amplification degree can be changed according to the frequency of the output signal of the frequency synthesizer set by the output frequency control signal, and the frequency of the output signal can be changed. Changes in the power level can be eliminated, and a stable output signal of the desired power level can be obtained. The ones that can Rukoto.

【0011】すなわち、本発明の周波数シンセサイザに
よれば、従来の増幅器を備えた周波数シンセサイザであ
れば出力信号の周波数が高くなるにつれて増幅度が低下
して出力信号の電力レベルが出力周波数により変動する
結果となってしまうのに対し、出力周波数制御信号に応
じて出力周波数が高くなった場合にその出力周波数制御
信号に対応して利得制御増幅器の利得すなわち出力信号
に対する増幅度を大きくすることができ、周波数シンセ
サイザの出力信号の電力レベルをその周波数によらず一
定に保つことができる。これにより、周波数シンセサイ
ザの出力周波数が高い場合にもその出力信号の電力レベ
ルの低下を防ぐことができ、出力信号を受ける外部回路
から要求される電力レベルを周波数によらず満足させる
ことができるため、周波数シンセサイザから外部回路へ
の過大な電力レベルの入力や入力電力レベルの不足等が
なくなり、ひいては無線通信装置全体に対する要求性能
を安定して満たすことができるものとなる。
That is, according to the frequency synthesizer of the present invention, in the case of a frequency synthesizer having a conventional amplifier, the amplification decreases as the frequency of the output signal increases, and the power level of the output signal varies with the output frequency. On the other hand, when the output frequency increases in response to the output frequency control signal, the gain of the gain control amplifier, that is, the amplification degree for the output signal can be increased in accordance with the output frequency control signal. The power level of the output signal of the frequency synthesizer can be kept constant regardless of the frequency. As a result, even when the output frequency of the frequency synthesizer is high, the power level of the output signal can be prevented from lowering, and the power level required from an external circuit receiving the output signal can be satisfied regardless of the frequency. In addition, the input of an excessive power level from the frequency synthesizer to the external circuit, the shortage of the input power level, and the like are eliminated, and the performance required for the entire wireless communication apparatus can be stably satisfied.

【0012】次に、本発明の周波数シンセサイザについ
て図面を参照しつつ説明する。
Next, a frequency synthesizer of the present invention will be described with reference to the drawings.

【0013】図1は本発明の周波数シンセサイザの実施
の形態の一例の概略構成を示すブロック図である。1は
制御電圧信号が入力され、その電圧に応じて周波数を制
御した周波数信号を出力する電圧制御発振器(VC
O)、2は電圧制御発振器1の出力を分周する周波数信
号の一部と外部回路である制御部10からの出力周波数制
御信号とが入力され、出力周波数制御信号に応じた分周
比で周波数信号を分周した分周信号を出力する可変分周
器、3は可変分周器2からの分周信号と外部回路からの
基準周波数信号fr とが入力され、両信号の位相差に応
じたパルス信号を出力する位相比較器、4は位相比較器
3からのパルス信号を直流電圧信号に変換して電圧制御
発振器1への制御電圧信号として出力するループフィル
タであり、これらのうち可変分周器2と位相比較器3と
によりPLL回路5が構成されている。
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a frequency synthesizer according to the present invention. Reference numeral 1 denotes a voltage controlled oscillator (VC) that receives a control voltage signal and outputs a frequency signal whose frequency is controlled in accordance with the voltage.
O), 2 receives a part of the frequency signal for dividing the output of the voltage controlled oscillator 1 and the output frequency control signal from the control unit 10 which is an external circuit, and has a dividing ratio according to the output frequency control signal. The variable frequency divider 3 outputs a frequency-divided signal obtained by dividing the frequency signal, and the frequency-divided signal 3 from the variable frequency divider 2 and the reference frequency signal fr from the external circuit are input to the variable frequency divider 3. The phase comparator 4 outputs a pulse signal from the phase comparator 3 and converts the pulse signal from the phase comparator 3 into a DC voltage signal and outputs the DC voltage signal as a control voltage signal to the voltage controlled oscillator 1. A PLL circuit 5 is configured by the frequency divider 2 and the phase comparator 3.

【0014】また、6は電圧制御発振器1からの周波数
信号と利得制御信号とが入力され、利得制御信号に応じ
た利得で周波数信号を増幅した出力信号を出力する利得
制御増幅器である。7は制御部10からの出力周波数制御
信号の一部が入力され、それに対応したデジタル信号を
出力するメモリ、8はこのデジタル信号に応じた電圧の
アナログ信号を利得制御増幅器6へ利得制御信号として
出力するデジタル/アナログ変換器(D/A)であり、
これらメモリ7とデジタル/アナログ変換器8とにより
利得制御信号発生回路9が構成されている。
Reference numeral 6 denotes a gain control amplifier to which a frequency signal and a gain control signal from the voltage controlled oscillator 1 are input, and which outputs an output signal obtained by amplifying the frequency signal with a gain corresponding to the gain control signal. Reference numeral 7 denotes a memory to which a part of the output frequency control signal from the control unit 10 is input and which outputs a digital signal corresponding to the input, and 8 denotes an analog signal of a voltage corresponding to the digital signal to the gain control amplifier 6 as a gain control signal. A digital / analog converter (D / A) for output,
The memory 7 and the digital / analog converter 8 constitute a gain control signal generation circuit 9.

【0015】メモリ7には出力周波数制御信号とデジタ
ル/アナログ変換器8に送るデジタル信号との間の変換
テーブルが記憶されており、このデジタル信号が入力さ
れたデジタル/アナログ変換器8がデジタル信号に応じ
たアナログ電圧信号を出力し、これを利得制御信号とし
て利得制御増幅器6へ入力することで、設定する周波数
に応じて利得制御増幅器6の利得を制御するものであ
る。
The memory 7 stores a conversion table between an output frequency control signal and a digital signal to be sent to the digital / analog converter 8, and the digital / analog converter 8 to which the digital signal is input is stored in the memory 7. Is output as the gain control signal to the gain control amplifier 6 to control the gain of the gain control amplifier 6 according to the set frequency.

【0016】なお、10はPLL回路5に対して周波数シ
ンセサイザの出力信号の周波数を設定するための出力周
波数設定信号を送る外部回路としての制御部であり、こ
の制御部10からの出力周波数設定信号は、同時に利得制
御信号発生回路9にも送られる。
Reference numeral 10 denotes a control unit as an external circuit for sending an output frequency setting signal for setting the frequency of the output signal of the frequency synthesizer to the PLL circuit 5, and an output frequency setting signal from the control unit 10. Is also sent to the gain control signal generation circuit 9 at the same time.

【0017】次に、このような本発明の周波数シンセサ
イザにおける動作の流れを説明する。
Next, an operation flow of the frequency synthesizer of the present invention will be described.

【0018】まず、電圧制御発振器1において制御電圧
信号に応じて発振され出力された周波数信号は、その一
部が制御部10からPLL回路5の可変分周器2へ送られ
る出力周波数制御信号に応じて分周比を設定される可変
分周器2によって分周され、その出力である分周信号と
外部回路から入力される基準周波数信号fr とは位相比
較器3によって比較される。この位相比較器3は両入力
信号の位相差に応じたパルス信号を出力し、このパルス
信号はループフィルタ4によって直流の電圧信号に変換
されて電圧制御発振器1に対する制御電圧信号となり、
電圧制御発振器1に入力される。これにより、電圧制御
発振器1における発振周波数が制御され、その出力であ
る周波数信号の周波数が制御部10からの出力周波数設定
信号によって設定しようとする周波数と一致することと
なる。
First, the frequency signal oscillated according to the control voltage signal in the voltage controlled oscillator 1 and output is partially converted into an output frequency control signal transmitted from the control unit 10 to the variable frequency divider 2 of the PLL circuit 5. The frequency is divided by the variable frequency divider 2 whose division ratio is set accordingly, and the output of the frequency-divided signal is compared with the reference frequency signal fr input from the external circuit by the phase comparator 3. The phase comparator 3 outputs a pulse signal corresponding to the phase difference between the two input signals, and this pulse signal is converted into a DC voltage signal by the loop filter 4 and becomes a control voltage signal for the voltage controlled oscillator 1,
It is input to the voltage controlled oscillator 1. As a result, the oscillation frequency of the voltage controlled oscillator 1 is controlled, and the frequency of the output frequency signal matches the frequency to be set by the output frequency setting signal from the control unit 10.

【0019】この電圧制御発振器1からの出力である周
波数信号は、利得制御増幅器6によって所望の利得で所
望の電力レベルに増幅されて、周波数シンセサイザから
の出力信号として出力される。この時、制御部10からP
LL回路5の可変分周器2に送られる出力周波数設定信
号の一部を利得制御信号発生回路9のメモリ7にも送ら
れる。メモリ7では前もって記憶されている変換テーブ
ルに従って出力周波数設定信号に応じたデジタル信号を
出力し、このデジタル信号はデジタル/アナログ変換器
8へと送られる。そして、デジタル/アナログ変換器8
では入力されるデジタル信号に対応する所定のアナログ
信号を出力し、このアナログ信号が利得制御増幅器6へ
利得制御信号として入力され、これにより周波数シンセ
サイザの出力信号の周波数に応じた利得制御増幅器6の
利得を得ることを可能とする。
The frequency signal output from the voltage controlled oscillator 1 is amplified by the gain control amplifier 6 to a desired power level with a desired gain, and output as an output signal from the frequency synthesizer. At this time, P
Part of the output frequency setting signal sent to the variable frequency divider 2 of the LL circuit 5 is also sent to the memory 7 of the gain control signal generating circuit 9. The memory 7 outputs a digital signal corresponding to the output frequency setting signal according to a conversion table stored in advance, and the digital signal is sent to the digital / analog converter 8. And a digital / analog converter 8
Outputs a predetermined analog signal corresponding to the input digital signal, and the analog signal is input to the gain control amplifier 6 as a gain control signal, whereby the gain control amplifier 6 according to the frequency of the output signal of the frequency synthesizer is output. It is possible to obtain a gain.

【0020】前述のように、従来の周波数シンセサイザ
における増幅器では、それに入力される電圧制御発振器
からの周波数信号の周波数が高くなるにつれてその利得
すなわち増幅度が減少する傾向がある。従って、本発明
の周波数シンセサイザにおいては、利得制御増幅器6に
おける利得が周波数信号の周波数が高い場合は大きくな
るように利得制御信号を制御し、周波数の上昇に伴う利
得の減少分を補うようにすることによって、周波数に関
わらず一定の電力レベルの出力信号を得ることができ
る。
As described above, in the amplifier of the conventional frequency synthesizer, the gain, that is, the amplification degree tends to decrease as the frequency of the frequency signal input from the voltage controlled oscillator increases. Therefore, in the frequency synthesizer of the present invention, the gain control signal is controlled so that the gain in the gain control amplifier 6 increases when the frequency of the frequency signal is high, so as to compensate for the decrease in gain due to the increase in frequency. Thus, an output signal having a constant power level can be obtained regardless of the frequency.

【0021】また、これにより周波数の上昇に伴う増幅
器の利得の減少分を見込んで出力電力を高めに設定する
必要もないため、出力信号に対する不要波の発生も防ぐ
ことができる。
In addition, since it is not necessary to set the output power higher in anticipation of a decrease in the gain of the amplifier accompanying an increase in the frequency, it is possible to prevent unnecessary waves from being generated in the output signal.

【0022】さらに、本発明の周波数シンセサイザによ
れば、その出力信号の電力レベルを単に一定に保つのみ
に留まらず、出力信号の周波数に応じて個別に電力レベ
ルを設定することもできるため、例えばこの出力信号を
受ける外部回路が周波数逓倍器のように使用する周波数
帯によって必要な入力電力レベルが異なるものである場
合にも、利得制御信号発生回路9における設定を調整す
ることによって容易に対応することができる。
Further, according to the frequency synthesizer of the present invention, not only the power level of the output signal is not merely kept constant but also the power level can be set individually according to the frequency of the output signal. Even when the required input power level differs depending on the frequency band used, such as a frequency multiplier, in an external circuit receiving the output signal, the setting in the gain control signal generating circuit 9 is easily adjusted. be able to.

【0023】なお、以上はあくまで本発明の実施の形態
の例示であって、本発明はこれに限定されるものではな
く、本発明の要旨を逸脱しない範囲で種々の変更や改良
を加えることは何ら差し支えない。
It should be noted that the above is only an example of the embodiment of the present invention, and the present invention is not limited to this. Various changes and improvements may be made without departing from the gist of the present invention. No problem.

【0024】例えば、図1においては電圧制御発振器1
や可変分周器2・位相比較器3・ループフィルタ4・利
得制御増幅器6・メモリ7・デジタル/アナログ変換器
8をそれぞれ個別の回路素子として説明したが、これら
をそれぞれ同様の機能を果たす回路によって構成しても
よいことは言うまでもない。
For example, in FIG.
And the variable frequency divider 2, the phase comparator 3, the loop filter 4, the gain control amplifier 6, the memory 7, and the digital / analog converter 8 have been described as individual circuit elements. Needless to say, it may be constituted by

【0025】[0025]

【発明の効果】本発明の周波数シンセサイザによれば、
電圧制御発振器から外部への出力部に通常挿入される周
波数信号を増幅する増幅器を利得制御可能なものとし、
この利得の制御に利得制御信号発生回路を用い、PLL
回路に入力される出力周波数制御信号を利用して出力信
号の周波数に応じてその利得すなわち増幅度の制御を可
能としたことによって、出力信号の電力レベルがその周
波数によって変動してしまうことがなくなって、所望の
一定の出力電力レベルを保つことができた。
According to the frequency synthesizer of the present invention,
An amplifier that amplifies a frequency signal that is normally inserted from a voltage controlled oscillator to an output unit to the outside can be gain controlled,
A gain control signal generation circuit is used to control this gain, and the PLL
By using the output frequency control signal input to the circuit to control the gain, that is, the amplification degree according to the frequency of the output signal, the power level of the output signal does not fluctuate depending on the frequency. Thus, a desired constant output power level could be maintained.

【0026】その結果、周波数シンセサイザの出力信号
を受ける外部回路の性能が電力レベル不足により劣化す
ることや、過大な電力レベルの入力によって信号のひず
みや不要波の発生を引き起こすことを防ぐことができ、
周波数シンセサイザの出力信号について周波数による電
力レベルの変動をなくし、安定した所望の電力レベルの
出力信号を得ることができる周波数シンセサイザを提供
することができた。
As a result, it is possible to prevent the performance of the external circuit receiving the output signal of the frequency synthesizer from deteriorating due to insufficient power level, and prevent input of an excessive power level from causing signal distortion and unnecessary waves. ,
The output signal of the frequency synthesizer can be provided with a frequency synthesizer capable of obtaining a stable output signal of a desired power level without fluctuation of the power level due to the frequency.

【0027】また、本発明の周波数シンセサイザによれ
ば、出力信号の電力レベルを周波数が変化しても一定に
保つのみに留まらず、出力信号の周波数に応じた電力レ
ベルを個別に設定することもできる。
Further, according to the frequency synthesizer of the present invention, the power level of the output signal is not only kept constant even if the frequency changes, but the power level according to the frequency of the output signal can be set individually. it can.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の周波数シンセサイザの実施の形態の一
例の概略構成を示すブロック図である。
FIG. 1 is a block diagram showing a schematic configuration of an example of a frequency synthesizer according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1・・・電圧制御発振器(VCO) 2・・・可変分周器 3・・・位相比較器 4・・・ループフィルタ 6・・・利得制御増幅器 7・・・メモリ 8・・・デジタル/アナログ変換器(D/A) 9・・・利得制御信号発生回路 DESCRIPTION OF SYMBOLS 1 ... Voltage controlled oscillator (VCO) 2 ... Variable frequency divider 3 ... Phase comparator 4 ... Loop filter 6 ... Gain control amplifier 7 ... Memory 8 ... Digital / Analog Converter (D / A) 9 ... Gain control signal generation circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 制御電圧信号が入力され、その電圧に応
じて周波数を制御した周波数信号を出力する電圧制御発
振器と、 前記周波数信号と利得制御信号とが入力され、利得制御
信号に応じた利得で周波数信号を増幅した出力信号を出
力する利得制御増幅器と、 前記周波数信号の一部と出力周波数制御信号とが入力さ
れ、出力周波数制御信号に応じた分周比で周波数信号を
分周した分周信号を出力する可変分周器と、 前記分周信号と基準周波数信号とが入力され、両信号の
位相差に応じたパルス信号を出力する位相比較器と、 前記パルス信号を直流電圧信号に変換して前記制御電圧
信号として出力するループフィルタと、 前記出力周波数制御信号の一部が入力され、それに対応
したデジタル信号を出力するメモリおよび前記デジタル
信号に応じた電圧のアナログ信号を前記利得制御信号と
して出力するデジタル/アナログ変換器からなる利得制
御信号発生回路とを具備することを特徴とする周波数シ
ンセサイザ。
A voltage-controlled oscillator that receives a control voltage signal and outputs a frequency signal whose frequency is controlled in accordance with the voltage; a gain that receives the frequency signal and a gain control signal; A gain control amplifier that outputs an output signal obtained by amplifying the frequency signal, and a part obtained by inputting a part of the frequency signal and an output frequency control signal and dividing the frequency signal by a division ratio according to the output frequency control signal. A variable frequency divider that outputs a frequency-divided signal, a phase comparator that receives the frequency-divided signal and a reference frequency signal, and outputs a pulse signal according to a phase difference between the two signals, and converts the pulse signal into a DC voltage signal. A loop filter for converting and outputting the control voltage signal, a memory for receiving a part of the output frequency control signal and outputting a digital signal corresponding thereto, Frequency synthesizer characterized by comprising a a gain control signal generating circuit for an analog signal comprises a digital / analog converter for outputting as the gain control signal voltage.
JP10162168A 1998-06-10 1998-06-10 Frequency synthesizer Pending JPH11355139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10162168A JPH11355139A (en) 1998-06-10 1998-06-10 Frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10162168A JPH11355139A (en) 1998-06-10 1998-06-10 Frequency synthesizer

Publications (1)

Publication Number Publication Date
JPH11355139A true JPH11355139A (en) 1999-12-24

Family

ID=15749325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10162168A Pending JPH11355139A (en) 1998-06-10 1998-06-10 Frequency synthesizer

Country Status (1)

Country Link
JP (1) JPH11355139A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2389251A (en) * 2002-05-31 2003-12-03 Hitachi Ltd A polar-loop wireless communication apparatus, a semiconductor integrated circuit and a loop gain calibration method
US7085544B2 (en) 2002-05-31 2006-08-01 Renesas Technology Corp. Transmitter having a phase control loop whose frequency bandwidth is varied in accordance with modulation modes
US7209717B2 (en) 2002-05-31 2007-04-24 Renesas Technology Corporation Apparatus for radio telecommunication system and method of building up output power
US7230997B2 (en) 2002-05-31 2007-06-12 Hitachi, Ltd. Semiconductor integrated circuit for communication, radio-communications apparatus, and transmission starting method
WO2013065846A1 (en) * 2011-11-04 2013-05-10 ヤマハ株式会社 Self-oscillating class-d amplifier and self-oscillating frequency control method for self-oscillating class-d amplifier
JP2014131117A (en) * 2012-12-28 2014-07-10 Yamaha Corp Self-oscillating class d amplifier

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7248842B2 (en) 2002-05-31 2007-07-24 Renesas Technology Corp. Wireless communication apparatus having a phase control loop shared by first and second modulation modes and an amplitude control loop
GB2389251B (en) * 2002-05-31 2005-09-07 Hitachi Ltd A communication semiconductor integrated circuit, a wireless communication apparatus, and a loop gain calibration method
US7082290B2 (en) 2002-05-31 2006-07-25 Renesas Technology Corp. Communication semiconductor integrated circuit, a wireless communication apparatus, and a loop gain calibration method
US7085544B2 (en) 2002-05-31 2006-08-01 Renesas Technology Corp. Transmitter having a phase control loop whose frequency bandwidth is varied in accordance with modulation modes
US7209717B2 (en) 2002-05-31 2007-04-24 Renesas Technology Corporation Apparatus for radio telecommunication system and method of building up output power
US7230997B2 (en) 2002-05-31 2007-06-12 Hitachi, Ltd. Semiconductor integrated circuit for communication, radio-communications apparatus, and transmission starting method
GB2389251A (en) * 2002-05-31 2003-12-03 Hitachi Ltd A polar-loop wireless communication apparatus, a semiconductor integrated circuit and a loop gain calibration method
US7366481B2 (en) 2002-05-31 2008-04-29 Renesas Technology Corporation Apparatus for radio telecommunication system and method of building up output power
US7433653B2 (en) 2002-05-31 2008-10-07 Renesas Technology Corp. Transmitter and semiconductor integrated circuit for communication
US7480345B2 (en) 2002-05-31 2009-01-20 Renesas Technology Corp. Semiconductor integrated circuit for communication, radio-communication apparatus, and transmission starting method
WO2013065846A1 (en) * 2011-11-04 2013-05-10 ヤマハ株式会社 Self-oscillating class-d amplifier and self-oscillating frequency control method for self-oscillating class-d amplifier
US9379679B2 (en) 2011-11-04 2016-06-28 Yamaha Corporation Self-oscillating class-D amplifier and self-oscillating frequency control method for self-oscillating class-D amplifier
JP2014131117A (en) * 2012-12-28 2014-07-10 Yamaha Corp Self-oscillating class d amplifier

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