JPH11353050A - Clock signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock signal generating circuit capable of supplying a stable clock signal to a connection circuit composed of a CPU or peripheral circuit to be connected when a power source is turned on. SOLUTION: This circuit has a clock signal generating part 11 for generating the clock signal and a reset signal generating part 14 for generating a reset signal and the clock signal and the reset signal synchronized with the clock signal are supplied to a connection circuit 13. This case, the circuit has a stable signal supplying means 12 for generating a stable clock signal (c) without being affected by the fluctuation of a power supply voltage based on an inputted clock signal (a) and supplying it to the connection circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generation circuit, and more particularly to a clock signal generation circuit for generating a clock signal to be output to a connection circuit connected when power is turned on.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a clock signal generating circuit in a calculation unit of a conventional numerical controller. As shown in FIG. 3, the clock signal a generated by the clock signal generation unit 1
The power is supplied to a connection circuit 2 including a CPU and peripheral circuits connected when the power is turned on. Further, the clock signal “a” is also supplied to the reset synchronization unit 3. The reset synchronizer 3 is supplied with the reset signal generated by the reset signal generator 4 and resets the reset signal b synchronized with the clock signal a.
Is supplied to the connection circuit 2.

FIG. 4 is a waveform diagram of an unstable clock signal generated by the clock signal generator of FIG. As shown in FIG. 4, when the power is turned on, the clock signal generation section 1 outputs an unstable clock signal a. That is, the clock signal generator 1 is an MPU (not shown) of the numerical controller.
When the stabilized power supply is stable, a stable predetermined clock signal is output, but when the stabilized power supply is unstable, such as when the power is turned on, the oscillation depends on the characteristics of the components used. A clock signal a having a frequency, a duty ratio, and an amplitude voltage is output and supplied.

Examples of such a clock signal generation and supply circuit include a microcomputer power-on reset circuit disclosed in Japanese Utility Model Laid-Open Publication No. Sho 57-11837 and an electronic circuit disclosed in Japanese Patent Laid-Open Publication No. Hei 3-123920. Devices and the like are known.

A power-on reset circuit of the microcomputer detects a power supply voltage and outputs an oscillation enable signal, a clock generator for supplying a clock pulse to an external clock input, and receives a clock pulse. A reset pulse generating circuit for supplying a reset pulse generated by the microcomputer to a reset input of the microcomputer, so that oscillation of the clock pulse is started after a power supply voltage of a predetermined level or more at which the microcomputer operates normally. ing.

[0006] The electronic apparatus includes means for generating a reset signal asynchronous with the CPU clock in accordance with the output voltage of the main power supply of the apparatus, means for forming a reset signal synchronized with the CPU clock from the reset signal, and a reset input. Means for interrupting the bus connection between the CPU and the RAM in accordance with the condition of the main power supply, selecting an asynchronous reset signal in the process of turning on the main power, and selecting a synchronous reset signal in the process of shutting off the main power in accordance with the operation state of the main power supply. Means for inputting to the bus connection interrupting means.

[0007]

However, in the clock signal generating circuit, the power-on reset circuit of the microcomputer and the electronic equipment in the arithmetic unit of the conventional numerical controller, the stabilized power supply at the time of turning on the power is unstable. The clock signal a supplied to the state has an oscillation frequency, a duty ratio, and a voltage amplitude that depend on the characteristics of the components used. For this reason, it is impossible to determine a signal waveform that satisfies each operation in the connection circuit 2 including the CPU and the peripheral circuit and the reset synchronizing unit 3, and each unit of the connection circuit 2 and the reset synchronizing unit 3 operates correctly. And the operation becomes unstable or does not work at all.

Particularly, in an environment where the numerical controller is used, the above-mentioned situation is remarkable because the power supply to the stabilized power supply fluctuates greatly and instantaneous power outages occur frequently.

An object of the present invention is to provide a clock signal generating circuit capable of supplying a stable clock signal to a connection circuit including a CPU and peripheral circuits connected when power is turned on.

[0010]

In order to achieve the above object, a clock signal generating circuit according to the present invention comprises a clock signal generating means for generating a clock signal and a reset signal generating means for generating a reset signal. In a clock signal generation circuit that supplies a clock signal and a reset signal synchronized with the clock signal to a connection circuit, based on the input clock signal, generates a stable clock signal that is not affected by fluctuations in power supply voltage. It is characterized by having stable signal supply means for supplying.

With the above configuration, the stable signal supply means generates a stable clock signal which is not affected by the fluctuation of the power supply voltage based on the input clock signal and supplies the stable clock signal to the connection circuit. As a result, C connected when power is turned on
A stable clock signal can be supplied to the connection circuit including the PU and the peripheral circuit regardless of the state of the stabilized power supply.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration block diagram of a clock signal generation circuit according to an embodiment of the present invention. As shown in FIG. 1, a clock signal generation circuit 10 is provided in an arithmetic unit (not shown) of, for example, a numerical controller having a CPU and performing a digital operation, and a clock signal generation unit 11 which generates and outputs a clock signal. And a stable signal supply unit 12 for generating and supplying a stable clock signal c based on the input clock signal, a connection circuit 13 including a CPU and peripheral circuits connected when the power is turned on, and a reset signal for generating and outputting a reset signal It has a generation unit 14 and a reset synchronization unit 15 that supplies a reset signal d synchronized with a stable clock signal c based on the input reset signal.

The stable signal supply section 12 has a voltage detection section 16 for detecting the power supply voltage of the operation section and a logic section 17 comprising an AND gate. The voltage detection section 16 is formed by a combination of a resistor and an operational amplifier, for example. The logic unit 17 is formed using, for example, a CMOS device that can operate at a low voltage.

The voltage detecting section 16 monitors the power supply voltage and generates a normal operation signal when the power supply voltage exceeds a predetermined voltage value. The logic section 17 generates the normal operation signal and the clock signal output from the clock signal generating section 11. The logical AND with the normal operation signal from the voltage detector 16 is calculated. The stable clock signal c obtained by the logical product is supplied from the logic unit 17 to the connection circuit 13 including the CPU and its peripheral circuits and the reset synchronization unit 15.

That is, the clock signal a output from the clock signal generator 11 when the stabilized power supply is unstable, such as when the power is turned on, has an oscillation frequency, a duty ratio, and an amplitude voltage depending on the characteristics of the components used. Have. The clock signal a is stable below a predetermined voltage value, but does not satisfy the operating conditions of each unit to which the clock signal a is supplied. On the other hand, since the stable clock signal c output from the logic unit 17 is a clock signal based on the normal operation signal, each unit to which the signal is supplied can operate normally.

FIG. 2 is a timing chart of each output signal in the lock signal generation circuit of FIG. As shown in FIG. 2, the clock signal a output from the clock signal generation unit 11 is a signal output in a state where the stabilized power supply is unstable when the power is turned on or the like, and depends on the characteristics of the components used. It has an oscillation frequency, a duty ratio, and an amplitude voltage (see (a)).

When the voltage detector 16 detects that the power supply voltage has exceeded a predetermined value, the voltage detector 16 outputs a normal operation signal e.
(See (b)), the normal operation signal e and the clock signal a are ANDed by the logic unit 17, and the stable clock signal c based on the normal operation signal e by the stable signal supply unit 12.
Is output (see (c)).

When the clock signal a is output by the clock signal generating circuit having the above configuration in a state where the stabilized power supply is unstable, such as when the power is turned on, the stable signal supply unit 12 which has detected the clock signal a outputs a normal operation signal. e, a stable clock signal c is output, and this stable clock signal c
It is supplied to the connection circuit 13 composed of U and peripheral circuits and the reset synchronization unit 15.

For this reason, the CPU connected at power-on
A stable clock signal can be supplied to the connection circuit 13 including the peripheral circuit and the peripheral circuit irrespective of the state of the stabilized power supply when the power is turned on. Since the stable clock signal c can be supplied, the supply destination does not operate correctly, the operation does not become unstable or does not operate at all, and the supply destination of the stable clock signal c is based on the predetermined operation condition. Stable operation is ensured.

Therefore, since the power supply to the stabilized power supply fluctuates greatly and instantaneous power failures are likely to occur frequently, even in an environment where a numerical control device in which unstable operation or inoperable state is remarkably generated is used, A stable operation based on a predetermined operation condition can be secured.

In the above embodiment, the normal operation signal is obtained by detecting the voltage, but a stable clock signal may be obtained by inputting an external timer instead of detecting the voltage.

[0023]

As described above, according to the present invention,
The stable signal supply unit generates a stable clock signal that is not affected by the fluctuation of the power supply voltage based on the input clock signal and supplies the stable clock signal to the connection circuit. A stable clock signal can be supplied regardless of the state of the stabilized power supply.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a clock signal generation circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of each output signal in the clock signal generation circuit of FIG.

FIG. 3 is a block diagram illustrating an example of a clock signal generation circuit in a calculation unit of a conventional numerical control device.

FIG. 4 is a waveform diagram of an unstable clock signal generated by a clock signal generation unit of FIG. 3;

[Explanation of symbols]

 Reference Signs List 10 clock signal generation circuit 11 clock signal generation unit 12 stable signal supply unit 13 connection circuit 14 reset signal generation unit 15 reset synchronization unit 16 voltage detection unit 17 logic unit a clock signal c stable clock signal d reset signal e normal operation signal

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuo Koike 1-25-1, Shinurashima-cho, Kanagawa-ku, Yokohama-shi, Kanagawa-ken Inside NEC Robotics Engineering Co., Ltd.

Claims (6)

[Claims] A clock signal generating means for generating a clock signal and a reset signal generating means for generating a reset signal, wherein the clock signal and a reset signal synchronized with the clock signal are supplied to a connection circuit. A clock signal generation circuit, comprising: a stable signal supply unit that generates a stable clock signal that is not affected by fluctuations in power supply voltage based on the input clock signal and supplies the stable clock signal to the connection circuit. 2. A stable signal supply means comprising: a voltage detection means for detecting a power supply voltage and outputting a normal operation signal based on a detection result; and a logic means for calculating a logical product of the normal operation signal and the clock signal. 2. The clock signal generation circuit according to claim 1, comprising: 3. The clock signal generating circuit according to claim 2, wherein said voltage detecting means outputs said normal operation signal when said power supply voltage exceeds a predetermined voltage value. 4. The CM according to claim 1, wherein said logic means is a CM capable of operating at a low voltage.
4. The clock signal generation circuit according to claim 2, wherein the clock signal generation circuit is made of an OS device. 5. The connection circuit according to claim 1, wherein said connection circuit comprises a CPU and peripheral circuits connected when power is turned on.
The clock signal generation circuit according to any one of claims 1 to 4. 6. The clock signal generation circuit according to claim 5, wherein the clock signal generation circuit is provided in a calculation unit of the numerical control device.