JP2003256070A - Clock switching circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate unstable external clocks not conforming to a standard and to securely input external clocks which conform to the standard into inside an IC. <P>SOLUTION: In a structure of a clock switch circuit, the external clocks are counted by a counter and if there is an omission in wave form of the external clocks, the counter is reset by an external clock continuous detection part. Only in the case that input of a normal clock wave form is confirmed by using an output signal of the counter, the signal to supply to inside the IC is switched from inner clocks to external clocks. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit (hereinafter referred to as I
The present invention relates to a clock switching circuit for switching between an internal clock and an external clock as a clock supplied to C).

[0002]

2. Description of the Related Art Conventionally, when the power is turned on, an internal clock generated inside the IC operates immediately, and then the system clock is switched to a highly accurate system clock supplied from the outside to synchronize the operation with other circuits. There is an IC that continues. Such an IC that uses the internal clock and the external clock by switching has a function of determining the presence or absence of the external clock by the IC itself.

FIG. 3 is a circuit diagram showing a configuration example of a conventional clock switching circuit. The clock changeover circuit includes a clock input section 1 outside the IC, an external clock average voltage detection circuit 2 formed inside the IC, a clock input changeover switch 3 formed inside the IC, and an internal clock generation circuit formed inside the IC. It is composed of four.

Here, the external clock average voltage detection circuit 2
Is a constant current source 21, N-type transistors Q3 and Q5 constituting a current mirror, and a waveform-shaped clock 102.
It is composed of a P-type transistor Q4 which is turned on and off by P1, a P-type and N-type transistors Q6 and Q7 which form an output circuit, and a capacitor C1 which determines the gate voltage of the output circuit.

When the external clock 101 is not input to the external clock average voltage detection circuit 2 such as when the power is turned on,
Since the input is low level, P-type transistor Q1
Is turned on and the N-type transistor Q2 is turned off. As a result, the gate of the P-type transistor Q4 of the external clock average voltage detection circuit 2 becomes high level, and the transistor Q4 is turned off. Therefore, a current determined by the current mirror ratio flows to the transistor Q5 with respect to the transistor Q3 to which a constant current is supplied from the constant current source 21, so that the charge of the capacitor C1 disappears and the capacitor C1 loses its charge.
The terminal voltage of 1 becomes low level. Therefore, the P-type transistor Q6 is turned on, the N-type transistor Q7 is turned off, the control signal 200 becomes high level, and the clock input changeover switch 3 is switched to the terminal b side.

On the other hand, the internal clock generating circuit 4 operates when the power is turned on to generate the internal clock 103. As a result, immediately after the power is turned on, the internal clock 103 is supplied to the inside of the IC (not shown) through the clock input changeover switch 3.

After that, the external clock 101 is input to the input terminal 5
From the external clock 1
The P-type and N-type transistors Q1 and Q2 are alternately turned on and off in synchronism with 01, the external clock 101 is waveform-shaped, and the external clock 102 is input to the external clock average voltage detection circuit 2 and P Type transistor Q4 switches.

Therefore, the power source B is supplied through the transistor Q4.
Is supplied to the transistor Q5 and the capacitor C1, and the terminal voltage of the capacitor C1 rises to a high level. Therefore, the P-type transistor Q6 is turned off, the N-type transistor Q7 is turned on, and the control signal 200
Becomes low level. As a result, the clock input selector switch 3 is switched to the terminal a side, and the waveform-shaped external clock 102 is supplied to the inside of the IC.

[0009]

There is no problem as long as the external clock 101 as described above is always supplied in the regular standard, but the oscillator circuit of the external clock 101 (not shown) in a transient state such as when the set is started. Until is stable
The external clock 101 that is different from the original voltage / frequency is I
The state of being supplied to C may occur.

That is, when the gate voltage of the transistor Q2 or more is supplied as the external clock 101, for example, the high-level waveform of the external clock 101 is less than a specified value, or a part of the clock waveform is missing. Also, when a high level is continuously input to some extent, charging of the capacitor C1 is started, the transistor Q7 is turned on, the clock input selector switch 3 is switched to the terminal a side, and the nonstandard clock 102 is input inside the IC.

As a result, in a transient state such as when the set is activated, the high level of the external clock 101 is less than the specified value, or the external clock 102 having a waveform lacking in a regular frequency is supplied to the inside of the IC. There is a possibility that a malfunction may occur such that the IC malfunctions or the IC does not work at all.

The present invention has been made in order to solve the above-mentioned conventional problems, and its purpose is to eliminate the input of an unstable external clock which is out of the standard and to provide a stable external clock which satisfies the standard. It is an object of the present invention to provide a clock switching circuit that can be surely input into the IC.

[0013]

In order to achieve the above object, means for solving the problems are as follows: an input section for waveform-shaping and inputting an external clock; and a counter for counting the external clock input from the input section. And a clock continuity detection unit that resets the counting operation of the counter when a discontinuity of the external clock input from the input unit is detected, and whether the external clock that has passed through the input unit depends on the output signal of the counter. , Or a clock input switching circuit for selecting one of the separately generated internal clocks and inputting it into the integrated circuit.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration according to an embodiment of a clock switching circuit of the present invention. The clock switching circuit includes a clock input unit 11 for inputting an external clock 101, a counter 12 for counting the waveform-shaped external clock 102, and an external clock continuation detecting unit 13 for detecting whether or not the external clock 102 is continuously input. A clock input changeover switch 14 for switching the external clock 102 and the internal clock 103 to be supplied to the IC internal 8 and an internal clock generation circuit 15 for generating the internal clock 103.

Here, the counter 12 uses the external clock 10
Although 2 is counted up to the set value, this set value is preset to a necessary value due to instability of the external clock 101 and the like. Also, the IC internal 8 is any circuit that needs to operate immediately by the internal clock 103 when the power is turned on, and then operate in synchronization with another device by the highly accurate external system clock (external clock 101). However, there is a driver circuit for a DC motor, for example.

Further, the circuit configuration of the external clock continuity detecting section 13 is almost the same as that of the conventional external clock average voltage detecting circuit shown in FIG. 3, for example, and the external clock is adjusted by adjusting the time constant of the capacitor C1. Even if one waveform of 102 is missing, the terminal voltage of the capacitor C1 is set to the low level so that the discontinuity of the external clock can be detected, which can be easily configured by a known technique.

Next, the operation of this embodiment will be described.
Since the external clock 101 is not input from the input terminal 16 when the power is turned on, the input of the clock input unit 11 is at a low level, the N-type transistor Q1 is turned off, and the P-type transistor Q2 is turned on. As a result, the input of the counter 12 is at the low level and does not perform the counting operation, and the output of the control signal 200 is at the high level. As a result, the clock input selector switch 14 is switched to the terminal b side.

On the other hand, since the internal clock generation circuit 15 generates the internal clock 103 when the power is turned on, the internal clock 103 is supplied to the IC internal 8 through the clock input changeover switch 14 immediately after the power is turned on.

After that, when an external clock 101 such as a highly accurate system clock supplied from the outside is input from the input terminal 16 to the clock input section 11, the transistors Q1 and Q2 of the clock input section 11 are alternately turned on, When turned off, the waveform-shaped external clock 102 is input to the external clock continuation detecting unit 13, the counter 12, and the terminal a of the clock input changeover switch 14.

As a result, the counter 12 counts the external clock 102, and when the counter 12 counts up to a preset set value, sets its output to the low level. Further, the external clock continuity detecting unit 13 detects whether or not the high-level waveform of the input external clock 102 is continuous, and the high-level waveform is lost as shown in FIG. 2 (L portion in FIG. 2).
If there is, the counter reset signal 300 is detected.
Is output to the counter 12 to reset the counting operation of the counter 12.

Here, the counter 12 counts the waveform-shaped external clock 102. At this time, if the high level of the waveform does not reach the specified value, the counter 12
By the comparison circuit (not shown) in the input stage, the counting operation is not performed because the reference value is not reached. Therefore, in such a case, the control signal 200, which is the output of the counter 12, remains at the high level, the clock input selector switch 14 remains switched to the terminal b, and the input of the external clock 102 to the IC internal 8 is blocked. To be done.

Further, although the high level of the waveform of the external clock 102 has reached the specified value, the counter 12 performs the counting operation, but before the counted value does not reach the set value, the low level period of the external clock 102 (see FIG. It is detected by the external clock continuous detection unit 13 that the L period of 2) is long, that is,
When it is detected that the waveform of the external clock 102 is missing, it is reset. As a result, the count value of the counter 12 does not reach the set value, and even in such a case, the counter 1
The control signal 200 which is the output of 2 remains high level,
The clock input selector switch 14 remains switched to the terminal b, and the input of the external clock 102 to the IC internal 8 is blocked.

Therefore, the counter 12 has the external clock 10
Only when the high level value of the waveform of 2 is the specified value or more and the frequency is normal without omission, count up to the set value,
The output of the control signal 200 is set to low level, the clock input selector switch 14 is switched to the terminal a, and the external clock 102 is supplied to the IC internal 8.

When the input of the external clock 101 is lost, the external clock continuity detecting section 13 detects the discontinuity of the external clock 102 and resets the counter 12, so that the clock input changeover switch 14 is connected to the terminal. It is switched to the b side, and the initial state is set.

According to this embodiment, the external clock 102
Are counted by the counter 12, and if the waveform of the external clock 102 is missing, the external clock continuity detection unit 13
Since the counter 12 is reset by the above, the high level of the waveform of the external clock 102 has a specified value, and only the external clock 102 having a specified frequency can be input to the IC internal 8 and is out of the standard such as when the power is turned on. It is possible to prevent the external clock 102 from being input into the IC. Therefore, it is possible to avoid a malfunction of the internal IC 8 due to the input of the nonstandard external clock 102 or a situation where the internal IC 8 does not operate at all, and the internal IC 8 can always be normally operated.

In the above embodiment, the internal clock generation circuit 15 may be formed integrally with the clock switching circuit or may be formed externally, but the clock switching circuit of this example is an indispensable component. Is a part excluding the internal clock generation circuit 15.

Further, the clock switching circuit of this example may be formed integrally with the IC inside 8 for supplying the clock.

The present invention is not limited to the above-described embodiment, and can be implemented in various other modes in specific configurations, functions, actions, and effects without departing from the scope of the invention. .

[0029]

As described in detail above, according to the clock switching circuit of the present invention, the input of an unstable external clock outside the standard is eliminated, and a stable external clock satisfying the standard is surely provided inside the IC. Can be input to, and malfunction of the IC with a nonstandard clock or a state where it does not operate at all can be avoided, and the IC can always operate normally.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration according to an embodiment of a clock switching circuit of the present invention.

FIG. 2 is a waveform diagram showing an example of a nonstandard external clock input to the input terminal of FIG.

FIG. 3 is a circuit diagram showing a configuration example of a conventional clock switching circuit.

[Explanation of symbols]

11 Clock input section 12 counter 13 External clock continuous detector 14 Clock input selector switch 15 Internal clock generation circuit 16 input terminals

Claims (3)

[Claims] 1. An input unit that shapes and inputs an external clock, a counter that counts the external clock input from the input unit, and a discontinuity of the external clock input from the input unit is detected. A clock continuity detecting section for resetting the counting operation of the counter; and an internal clock of the integrated circuit by selecting either an external clock passing through the input section or an internally generated clock depending on the output signal of the counter. And a clock input switching circuit for inputting to the clock input circuit. 2. The counter, when counting the external clock to a set value, outputs a signal for switching the clock input to the clock input switching circuit from the internal clock to the external clock, and the set value is preset. The clock switching circuit according to claim 1, wherein the clock switching circuit is set to a required value. 3. The clock switching circuit according to claim 1, wherein the internal clock is generated by an internal clock generating circuit formed integrally with the clock switching circuit.