JPH113484A - Signal transmitter having communication function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate communication trouble that occurs at the time of inspection at a job site by identifying a 1st communication signal which is sent from a 1st communication terminal that is connected to a transmission line to a signal transmitter and a 2nd communication signal which is sent from a 2nd communication terminal that is directly connected to the signal transmitter. SOLUTION: A digital communication signal SM1 that is sent from a sending port TR2 of a microprocessor μP3 and a digital communication signal SL1 which is transmitted from an output terminal TI are inputted to an input end of a NOR gate Q3 that functions as a 1st theoretical element. On the other hand, a communication signal SH1 that is outputted from a hand-held terminal 15 through a terminal T4 and a communication signal which is acquired at an output end of the gate Q3 are inputted to an input end of a NOR gate Q4 . And they are outputted to a receiving port R1 of the microprocessor μP3 . Such an interface circuit IFC3 is provided and either of them is transmitted to the microprocessor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention detects a physical quantity such as a flow rate, performs signal processing, transmits the current signal to a load side as a current signal via a transmission line, and superimposes a digital signal on the current signal to communicate with each other. The present invention relates to a signal transmitter having a communication function, and in particular, communication improved in such a manner that noise other than the communication signal transmitted from the transmission line or the communication signal mixed in the transmission line does not compete with the communication signal transmitted directly from the signal converter. The present invention relates to a signal transmitter having a function.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a conventional signal transmitter having a communication function. As an example of the signal transmitter in this case, a three-wire signal transmitter that outputs a flow pulse is shown. Reference numeral 10 denotes a signal transmitter for converting a physical quantity such as a flow rate into an electric signal and transmitting the signal. The signal transmitter 10 is connected to output terminals T ₁ and T ₂ from a DC power supply 11 via a load 12, and transmits a signal therefrom. Power is supplied to the vessel 10.
The DC power supply 11 and the load 12 are located on the receiving instrument side located far away.

An electric signal is transmitted as an analog current signal _IL to a load 12 via transmission lines L ₁ and L ₂ connected to output terminals T ₁ and T ₂ of a signal transmitter 10. It is obtained by detecting an analog voltage change occurring at both ends.

[0004] 4~20m by the current signal I _L, the signal transmitter 10 which is set in the range corresponding to, for example, the flow rate range
The current is converted to a unified current of A and transmitted to the load 12 side, and is displayed on a built-in monitor in, for example, a 4-digit digital form.

In this case, for example, when it is desired to change the flow rate range, change various parameters, or monitor, it is convenient if the signal transmitter 10 can be operated from outside.

For this reason, the handheld terminal 14 functioning as the first communication terminal is connected to the transmission line L ₁₁ , if necessary.
L ₂₁ , and the signal transmitter 10 has a dedicated data communication function with the handheld terminal 14, and transmits digital data such as parameter changes from the handheld terminal 14 to the signal transmitter 10.

[0007] The signal transmitter 10
Is configured as follows. The SNR is a detector (sensor) that detects a flow rate or the like and converts it into a measurement signal, and the converted measurement signal is converted into an analog / digital converter A
/ D is converted to a digital signal by the microprocessor μ
Via P ₁ is stored in the random access memory portion in the memory MEM _1.

The microprocessor μP ₁ uses the stored digital signals to execute a predetermined operation such as linearization according to an operation procedure written in, for example, a read-only memory portion of the memory MEM ₁ , and converts the result into a digital signal. / Output circuit OPC via analog converter D / A
Output to

The output circuit OPC converts the voltage signal converted into an analog signal by the digital / analog converter D / A into 4 to 2
Transmission line L ₁ is converted into a unified current signal I _L of 0 mA,
Transmitted via the L _2. Further, the output circuit OPC make power of the internal circuit of the signal transmitter 10 with a portion of the current signal I _L that is transmitted from the DC power supply 10 side.

The IFC ₁ is an interface for performing data communication with the handheld terminal 14 and is connected between the transmission lines L ₁ and L ₂ and the microprocessor μP ₁ .

The digital signals transmitted to the transmission lines L ₁ and L ₂ connected to the output terminals T ₁ and T ₂ are connected to the common potential point CO.
M and is applied to one end of the input terminal of the summing amplifier Q _1, it is transmitted as parallel signals via the terminals T ₃ through the serial / parallel converter (not shown) in the microprocessor .mu.P _1.

Conversely, the microprocessor μP₁De from
Digital data is transmitted to the output circuit OPC as a serial signal.
The output circuit OPC is an analog 4 to 20 mA current signal.
Issue I _LTo the transmission line L₁, L_TwoTo the load 12 side via
Sent out.

Further, in the event that a failure or the like occurs in the signal transmitter 10, the interface IFC ₁ includes:
The terminal T ₄ connected to the other end of the input terminal of the summing amplifier Q ₁ provided which a common potential point handheld terminal 14 similar to that of the second for maintenance between the connected terminal T _C to COM
A handheld terminal 15 functioning as a communication terminal is connected so that operations such as parameter changes can be performed on site.

The digital flow signal calculated by the microprocessor μP ₁ is provided by the interface IFC ₁
It is in parallel via a terminal T ₅ / serial converter P / S conversion into a serial signal and is applied to the gate of the field effect transistor Q _2.

The field effect transistor Q ₂ is connected to the DC power source 1
1 and the pull-up resistor 16, is connected to the drain of the field effect transistor Q ₂ through a terminal T ₆ is constructed as open collector, the flow rate pulse signals Q _P corresponding to a signal applied to the gate of the field effect transistor Q ₂ Is output between the terminals T ₇ and T ₈ arranged on the load side.

Next, the internal configuration of the handheld terminal 14 will be described. SER is a setting device operated by an operator, has a built-in monitor, and changes the mode of switching the signal transmitter 10 between zero adjustment and span adjustment, requests a model,
Can change the display resolution, change of range, abnormality detection, or display various settings or requests, such as the value of the current signal I _L.

ΜP ₂ is a microprocessor, for example, to which data from a setter SER is inputted and which is stored in a memory MEM
₂ according to the processing procedure stored in
It sends a digital signal to the signal transmitter 10 through the C _2.

The microprocessor μP ₂ converts the response data from the signal transmitter 10 into an interface IFC ₂
To the memory MEM ₂ via the
It decrypts it according to the processing procedure stored in M _2, is displayed on the monitor of the setter SER.

[0019]

However, the signal transmitter 10 as described above is provided with a handheld terminal 14.
Other than the communication signal transmitted from the communication side or the communication signal mixed into the transmission line, and the terminal T inside the signal transmitter 10.
_If a communication signal transmitted from the hand-held terminal 15 connected to the terminal ₄ and a communication signal are simultaneously output, a problem arises in that normal communication cannot be performed.

As a result, even if it is attempted to adjust the parameters of the signal transmitter 10 on site, a problem arises that the parameter adjustment and the like cannot be performed unless transmission stop is instructed to the handheld terminal 14 in some form.

[0021]

According to the present invention, as a main configuration for solving the above-mentioned problems, a physical quantity is detected, a current signal related to the physical quantity is transmitted to a load via a transmission line, and the load is controlled. In a signal transmitter having a communication function equipped with a microprocessor which superimposes a digital signal on a current signal and communicates with a communication terminal, a signal is transmitted from the first communication terminal connected to the previous transmission line to the previous signal transmitter. An interface circuit for identifying the first communication signal and the second communication signal transmitted from the second communication terminal directly connected to the previous signal transmitter, and transmitting one of them to the preceding microprocessor. It is like that.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention. Portions having the same functions as those of the conventional signal transmitter shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The present invention will also be described by taking a three-wire signal transmitter as an example of the signal transmitter.

The signal transmitter 17 is the same as the signal transmitter 10 in that it has a detector SNR, an analog / digital converter A / D, a digital / analog converter D / A, an output circuit OPC, and the like. However, the memory MEM ₁ is the memory M
In EM _3, the microprocessor .mu.P ₁ is a microprocessor .mu.P _3, interferons chair circuit IFC ₁ is to Interferon chair circuit IFC _3, are changed respectively.

The memory MEM ₃ stores an operation program having a different content from that of the memory MEM ₁ and the interface circuit IFC ₃ is also different, so that the operation by the microprocessor μP ₃ is different from the conventional one. This is the operation content.

[0025] First, describes the internal structure of the interferons chair circuit IFC _3. Digital communication signal S _M1 transmitted from transmission port TR ₂ of microprocessor μP ₃
And a digital communication signal S _L1 transmitted from the output terminal T ₁
It is input to the input terminal of the NOR gate Q ₃ which functions as a first logic element and.

On the other hand, the communication signal S _H1 output via a terminal T ₄ from the handheld terminal 15, the communication signal obtained at the output terminal of the NOR gate Q _3, input NOR gate Q ₄ which acts as a second logic element The output terminal of the microprocessor μP ₃ outputs the signal to the receiving port R ₁ of the microprocessor μP ₃ .

The data terminal D of the flip-flop FF is
Source + V_DIs held at high level H by
The lock terminal CK has an end from the handheld terminal 15
Child T _FourCommunication signal S output through_H1Mark
Has been added.

The logical data obtained at the output terminal Q corresponding to the logical level of the data terminal D in synchronization with the rise of the communication signal S _H1 is output to the receiving port R ₂ of the microprocessor μP ₃ .

Furthermore, the clear terminal of the flip-flop FF <CLR> (meaning inverted by <>), the clear signal from the transmission port T _R1 of the microprocessor .mu.P ₃ CR
Is sent as needed.

[0030] Note that the digital signal S _D1 output from the transmission port T _R3 of the microprocessor .mu.P ₃ to the output circuit OPC handheld terminal 15 is connected is impedance converted by the terminal T _9, amplifier Q ₅ is branched It is sent to the terminal T _4.

Next, the communication function executed by the microprocessor μP ₃ of the signal transmitter 17 configured as described above will be described with reference to the flowcharts of FIGS. 2, 3, 4, 5, and 6.

FIG. 2 is a flowchart showing a task selection procedure for controlling the flow of task selection, FIG. 3 is a flowchart showing an interrupt procedure for performing a software soft interrupt, and FIG. 4 is a conflict determination for determining a communication conflict. FIG. 5 is a flowchart showing the procedure, FIG. 5 is a flowchart showing a one-second task for performing a hard interrupt for holding a state, and FIG. 6 is a flowchart showing a 250 ms task for performing a hard interrupt for releasing communication lock.

[0033] It like task selection procedure, the interruption procedure, contention determination procedure, one second task, and the procedure of 250mS task is prestored in a predetermined area of the memory MEM _3, the microprocessor in accordance with a system clock (not shown) Each program is executed under the control of μP ₃ .

First, the task selection procedure shown in FIG.
The execution is started from the in-program. In step 1
Initial processing is performed, but here the microprocessor
μP _ThreeIs the transmission port T_R1From the clear signal CR (low
Level L) is set to the clear terminal <CL of the flip-flop FF.
R> to set its output terminal Q to low level L,
After that, the state is set to the high level H and the communication standby state is set.

Next, the microprocessor μP ₃ sets the transmission port T _R2 to the low level L, sets one end of the input terminal of the NOR gate Q ₃ to the low level L, and ends the initial processing of Step 1.

Thereafter, the process proceeds to step 2. In step 2, task bit determination for switching a plurality of tasks according to their weights is performed. Here, a communication task, a 250 mS task, and a one-second task will be described as tasks related to communication processing.

[0037] Some memory MEM _3, for example, provided a 16-bit task selection area, where the communication task you stand example bits 1, you stand the bit 2 to 250mS task, one second task you stand bit 4 Move to.

Of these, the communication task is a soft interrupt due to the arrival of a communication signal, and the 250 ms task and the one second task are each executed by a hard interrupt due to the elapse of a predetermined time by counting of a built-in counter.

Communication task, 250 ms task, or 1
Every time the second task is executed, the process returns to step 2 via the return path, where the task is selected again in the task selection area, and the selected task is executed. Thereafter, this is repeated.

Next, the operation when the communication task is selected will be described. First, communication is the its software interrupt is generated (Step 1 in FIG. 3), but receives and stores communication data in a predetermined area of the memory MEM _3, whether this case, whether the received communication data is completed Is determined in step 3.

If the reception of the communication data has been completed in step 3, the process proceeds to step 4 and sets the bit 1 for selecting the communication task in the task selection area, or sets the bit to 1 if it has been set previously. Step 5
, That is, the return path shown in FIG.

If the reception of the communication data has not been completed in step 3, the return in step 5, that is, as shown in FIG.
After returning to the return path, the communication task shown in FIG. 2 is executed again and executed until the reception of communication data is completed in step 3 of FIG. Therefore, if the reception of the communication data has been completed, bit 1 as the task bit, that is, the communication task is selected.

Next, processing when a communication task is selected will be described with reference to FIG. In step 1 of FIG. 4, it is determined whether the communication data is normal. Specifically, whether there are start bits and stop bits,
Alternatively, the determination is made based on whether the parity check is normal.

When there is an error (Y), Re shown in FIG.
The process moves to a turn route, and further receives communication data in accordance with the flow shown in steps 1 to 5 shown in FIG. 3 and returns to the communication task in FIG.

If there is no error (N), the flow shifts to step 2 in FIG. Do In step 2 digital signal is sent via a terminal T ₄ from the handheld terminal 15, or to perform the determination of whether the sent through the transmission line L _1, L _2.

Since the data terminal D of the flip-flop FF is held at the high level H, if there is digital communication from the handheld terminal 15, the logical level of the output terminal Q becomes high level H by the rising edge thereof. .

The microprocessor μP ₃ checks the logical level of the receiving port R ₂ and, when detecting that the logical level is at the high level H, knows that the digital communication has been performed from the handheld terminal 15 side. , And the microprocessor μP ₃ holds the digital signal S _M1 output from the transmission port T _R2 at the high level H.

[0048] Thus, since one end of the input terminal of the NOR gate Q ₃ are held at the high level H, NOR gate Q
The output terminal ₃ is fixed at the low level L, and the communication signal S _L1 input from the handheld terminal 14 via the transmission lines L ₁ and L ₂ is cut off.

Thus, the NOR gate Q_FourOf the input end of
One end is fixed at low level L, so
Communication signal S output from the terminal 15_H1Is Noah
Q _FourThrough the microprocessor μP_ThreeReceiving port
R₁Received at.

Next, in step 2, the microprocessor .mu.P ₃ is the logic level of the reception port R ₂ is at low level L, as the communication signal S _L1 is transmitted from the transmission line L _1, L ₂ side leads to step 4, the clear signal CR from the transmission port T _R1 of the microprocessor .mu.P ₃
(Low level L) is output to the clear terminal <CLR> of the flip-flop FF, and the logic level of the output terminal Q is fixed at Low level L.

In this state, the microprocessor μP ₃
Sets the digital signal S _M1 output from the transmission port T _R2 to low level L, so that the communication signal S _L1 from the transmission lines L ₁ and L ₂ passes through the NOR gate Q ₃ and the input terminal of the NOR gate Q ₄ Is output to one end of

Further, since there is no communication signal S _H1 from the handheld terminal 15, it is at the low level L,
Therefore, the communication signal S from the handheld terminal 15
_L1 is received by the reception port R ₁ through the NOR gate Q _4.

After the above processing, the process proceeds to step S5.
In step 5, the timer set time for the one-second task described later
Set the variable tim. After this setting, step 6
To the microprocessor μP_ThreeIs the received communication
No. S_H1, S_L1Decrypts and executes the contents of transmission port T_R3To
Communication signal S via_D1Output circuit OPC and terminal T _Four
Output to

Next, the one-second task shown in step 5 of FIG. 4 will be described with reference to FIG. This one-second task is for performing a hardware interrupt irrespective of communication in order to manage state maintenance, and specifically, sets a time for maintaining the logic level in steps 3 and 4 in FIG.

In step 1 of FIG. 5, step 5 of FIG.
Assuming that the counter is initialized at, for example, 100 seconds as a variable tim, a determination is made every second as to whether or not this content is zero.
If it is not zero, the process proceeds to step 2 where 1 second is subtracted. If the result is zero, the flow shifts to step 3; if not, the flow shifts to Return and repeats again.

In step 3, since the set time set in the counter has elapsed, the process of returning to the initial state shown in step 1 of FIG. 2 is executed, and the process returns to Return and is repeated again. In this case, _TR1 is once set to low level L,
After that, change to high level H to cancel the locked state,
In standby mode.

Next, the 250 second task shown in FIG. 6 will be described. In the 250-second task, when the input terminals of the NAND gate Q ₃ are both at the low level L and the output of the NAND gate Q ₃ is at the high level H in the initial state, the output of the NAND gate Q ₄ is fixed at the low level L, and performs processing for avoiding the communication signals S _H1 from the terminal 15 is not input to the receive port R _1.

Specifically, the microprocessor μP
_3, performs hard interrupts at fixed cycle unit, for example, 250ms examine the state of the reception port R _2, if this is the high level H, the communication by the communication signals S _H1 from the handheld terminal 15 is being carried out since the NOR gates Q ₃ communication signals S _L1 from the transmission line L _1, L ₂ the transmission port T _R2 a high level H (step 2)
And if it is at low level L, it means that communication by the communication signal S _H1 is not being performed.
Perform processing to shift to. Thereafter, this is repeated and executed again.

Further, in FIG. 1, the microprocessor μP ₃ detects the flow rate by the detector SNR, takes in the flow rate, executes the flow rate calculation, and converts the flow rate signal into a load signal as a current signal of 4 to 20 mA as analog data. To the terminals T ₈ and T ₈ as a flow pulse signal P _f.
Sometimes you want to output to ₇ .

In such a case, the microprocessor μ
P ₃ is parallel flow signal through a terminal T ₅ / serial converter P
/ ON / OFF the field effect transistor Q ₂ through the S outputs a flow rate pulse signals Q _f to the terminal T _8, T _7.

Even in this case, when the transmission distance between the transmission lines L ₁ and L ₂ is short and the line resistance R _LL is small, the pulse voltage generated at both ends is small, so that the hand-held terminal is connected to the transmission lines L ₁ and L _2. The communication signal S _L1 sent from 14 is less affected by the pulse voltage and operates without any problem.

[0062]

As described above, according to the present invention, the first communication signal transmitted from the first communication terminal connected to the transmission line to the signal transmitter and the signal transmitter are transmitted. Since the second communication signal transmitted from the directly connected second communication terminal is distinguished from the second communication signal and one of the signals is transmitted to the microprocessor to avoid a communication conflict, a maintenance and inspection at the site is performed. There is an advantage that communication troubles occurring in the system can be effectively removed. In addition, when the second communication terminal is used, on-site maintenance and inspection can be performed while removing noise other than communication signals mixed on the transmission line, so that quick and accurate on-site adjustment is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 2 is a flowchart illustrating a task selection procedure for controlling the flow of task selection.

FIG. 3 is a flowchart illustrating an interrupt procedure for performing a software soft interrupt.

FIG. 4 is a flowchart illustrating a conflict determination procedure for determining a communication conflict.

FIG. 5 is a flowchart showing a one-second task for performing a hard interrupt for holding a state.

FIG. 6 shows a case where a hardware interrupt for communication lock release is performed.
It is a flowchart figure which shows a 50mS task.

FIG. 7 is a block diagram showing a configuration of a conventional signal transmitter.

[Description of Reference Numerals] 10, 17 signal transmitter 11 DC power supply 12 load 15 handheld terminal SNR detector MEM _1, MEM _2, MEM ₃ memory μP _1, μP _2, μP ₃ microprocessor IFC _1, IFC _2, IFC ₃ interface circuit FF flip-flop

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masami Wada 2-9-132 Nakamachi, Musashino-shi, Tokyo Inside Yokogawa Electric Corporation (72) Inventor Hirohide Tsutsui 2-9-132 Nakamachi, Musashino-shi, Tokyo Yokogawa Electric Corporation

Claims (2)

[Claims] A communication system comprising a microprocessor for detecting a physical quantity, transmitting a current signal related to the physical quantity to a load via a transmission line, and superimposing a digital signal on the current signal to communicate with a communication terminal. In a signal transmitter having a function, a first communication signal transmitted from the first communication terminal connected to the transmission line to the signal transmitter and a first communication signal transmitted from the second communication terminal directly connected to the signal transmitter. A signal transmitter having a communication function, comprising: an interface circuit that identifies a second communication signal and transmits one of the signals to the microprocessor. 2. A flip-flop which is initialized by the microprocessor and detects whether or not the second digital signal is received, and the microprocessor detects a reception state of the second digital signal and sets the state to cut off the first communication signal. 2. The device according to claim 1, further comprising: a first logic element that allows the signal to pass therethrough; and a second logic element that controls passage of the second communication signal or the first communication signal based on an output of the first logic element. A signal transmitter having a communication function.