JPH11341358A - Solid-state image-pickup device and camera using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable processing such as addition/subtraction through optional combination without the need for externally providing a delay circuit, etc., a solid-state image-pickup device or lowering a resolution frequency. SOLUTION: In a solid-state image-pickup device which has an image picking up part which converts incident light into signal charge in a pixel unit and an outputting part 15 which outputs the signal charge converted by the image- pickup part as a voltage signal, the part 15 consists of signal outputting means a1 and a2 of plural independent systems, and also the signal outputting means a1 and a2 output voltage signals to be outputted in such a manner that they are mutually delayed or that their phases are different.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device for obtaining a voltage signal from incident light by photoelectric conversion and a camera using the same.

[0002]

2. Description of the Related Art Recently, a CCD (Charge Coupled Device) has been developed.
Cameras (for example, video cameras and electronic still cameras) using a solid-state imaging device such as the above as an imaging device have become widespread. In a camera using such a solid-state imaging device, it is known to perform processing such as addition or subtraction on an output signal in order to improve photographing sensitivity or perform complementary color filter processing. Specifically, in the case of addition processing, a signal charge is added inside the solid-state imaging device, or a voltage signal output from the solid-state imaging device is added by providing a delay circuit separate from the solid-state imaging device. There are things to do.

[0003]

Incidentally, a solid-state imaging device normally outputs signal charges obtained for each pixel as voltage signals in a predetermined order. Therefore, in the conventional solid-state imaging device, when signal charges are added internally, processing is performed only in a predetermined combination along the output order. That is, for example, only a predetermined combination such as the first signal charge and the second signal charge, the third signal charge and the fourth signal charge, and the like can be performed. Any combination, such as a combination of the first and third signals, and a combination of the same signals (for example, the first signal charges) cannot be supported. Therefore, in a conventional solid-state imaging device, when signal charges are added internally,
There is a possibility that the resolution frequency will be reduced by half.

On the other hand, addition / addition outside the solid-state imaging device is performed using a delay circuit or the like provided separately from the solid-state imaging device.
If processing such as subtraction is performed, processing using any combination can be performed. However, in this case, since it is necessary to provide a delay circuit and the like separately from the solid-state imaging device, the configuration of the camera may be complicated and large.

Therefore, the present invention makes it possible to perform addition / subtraction processing in any combination without requiring a delay circuit or the like outside the solid-state imaging device and without reducing the resolution frequency. It is an object of the present invention to provide a solid-state imaging device capable of outputting a different output signal.
Further, the present invention does not require the provision of a delay circuit or the like outside the solid-state imaging device, and can perform processing such as addition / subtraction in any combination without reducing the resolution frequency. An object of the present invention is to provide a camera using the device.

[0006]

According to the present invention, there is provided a solid-state imaging device devised to achieve the above object. The imaging unit converts incident light into signal charges on a pixel-by-pixel basis. An output unit for outputting signal charges as a voltage signal, wherein the output unit comprises a plurality of independent signal output means, and the voltage signals to be output by each signal output means are delayed with respect to each other or the phase is It is configured to output in different states.

[0007] According to the solid-state imaging device having the above configuration, the voltage signal from the output section is output from the signal output means of a plurality of systems in a state where they are delayed from each other or in a state where the phases are different. Therefore, if processing such as addition or subtraction is performed on the voltage signal from each signal output unit via, for example, a sample-and-hold circuit, the same voltage can be obtained without providing a delay circuit or the like separately from the solid-state imaging device. It becomes possible to process voltage signals by signals or by an arbitrary combination.

Further, the present invention is a camera devised to achieve the above object, wherein the camera uses a solid-state imaging device for obtaining a voltage signal from incident light. A plurality of signal output means for outputting signals delayed or mutually out of phase with each other; a sample-hold circuit individually corresponding to each signal output means; And a processing circuit for performing a predetermined process on each voltage signal output through the circuit.

According to the camera having the above configuration, the voltage signals output from the solid-state imaging device are output in a state of being delayed or different in phase from each other by a plurality of signal output means. Then, these voltage signals pass through sample-and-hold circuits individually corresponding to the respective signal output units, and then are subjected to predetermined processing such as addition or subtraction by a subsequent processing circuit. Therefore, in this camera, predetermined processing can be performed on the same voltage signal or a voltage signal obtained by an arbitrary combination without providing a delay circuit or the like separately from the solid-state imaging device.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A solid-state imaging device according to the present invention and a camera using the same will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
FIG. 2 is an explanatory diagram illustrating an outline of a solid-state imaging device according to the embodiment, FIG. 2 is a block diagram illustrating a main part of a camera using the solid-state imaging device, and FIG. 3 is a schematic configuration diagram of the solid-state imaging device. is there.

First, a camera according to the present embodiment, that is, a camera using the solid-state imaging device according to the present embodiment will be described with reference to the drawings. As shown in FIG. 2, the camera according to the present embodiment is a solid-state imaging device 1.
0 is used as an imaging device. This solid-state imaging device 10 has an independent 2
It has a system output, and a voltage signal (hereinafter, referred to as
"Output 1" and "Output 2" are output.

In this camera, two sample-and-hold circuits (hereinafter abbreviated as S / H circuits) 2 are provided in the subsequent stage of the solid-state imaging device 10 so as to individually correspond to the outputs of the respective systems.
1 and 22 are connected. Each S / H circuit 21, 22
Performs sample hold for "output 1" and "output 2". In the S / H circuits 21 and 22,
Sample hold pulses (hereinafter, “SH1”, “S1”) given from an upper circuit (not shown) (camera control circuit, etc.)
H2) controls the timing of execution of the sample hold and its output (hereinafter abbreviated as S / H output).

Further, a processing circuit 23 for performing a predetermined process such as an addition process or a subtraction process on the S / H output from each of the S / H circuits 21 and 22 is connected to the subsequent stage. . The output after the predetermined processing by the processing circuit 23 is sent to an unillustrated signal processing circuit (such as an image processing circuit) after passing through an S / H circuit 24 that performs a sample and hold operation. . It is assumed that the S / H circuit 24 is controlled by a sample and hold pulse (hereinafter, referred to as “SH3”) from a higher-level circuit.

Next, the solid-state imaging device 10 used in the camera having such a configuration, that is, the solid-state imaging device 10 of the present embodiment will be described with reference to FIG.

In the solid-state imaging device 10, a plurality of photosensors 11 two-dimensionally arranged in pixel units to form a light receiving unit that converts incident light into signal charges in pixel units and stores the signal charges.
A vertical CCD (vertical transfer unit) 12 for vertically transferring signal charges read out from the photosensors 11 for each vertical column forms an imaging area 13.
The vertical CCD 12 performs an operation corresponding to vertical scanning, and is driven in four phases by vertical transfer clocks φV1 to φV4.

On the output side of the vertical CCD 12, a vertical CCD
A horizontal CCD (horizontal transfer unit) 14 for transferring the signal charges transferred from the horizontal direction 12 in the horizontal direction is provided. The horizontal CCD 14 performs an operation corresponding to the horizontal direction, and is driven in two phases by horizontal transfer clocks φH1 and φH2.

On the output side of the horizontal CCD 14, an output unit 15 composed of, for example, a floating diffusion amplifier for detecting the transferred signal charge and converting it into a voltage signal.
Are provided, and two outputs “output 1” and “output 2” are derived from the output unit 15. Note that the output unit 15 may have a charge / voltage conversion structure using a floating gate structure instead of the floating diffusion structure.

Here, the output section 15 will be described in detail with reference to FIG. In addition, FIG.
It is a figure which shows the example at the time of arrange | positioning the charge detection part for obtaining "output 1" and "output 2" of a system in series with a cross-sectional image.

As shown in FIG. 1A, the output section 15 includes diffusion layers (hereinafter, referred to as charge detection sections) a1 and a2 of a charge detection section for obtaining "output 1" and "output 2".
, A diffusion layer b for resetting a signal, and a plurality of electrodes c1 to c5 are provided in series. Among them, the electrodes c1 to c5 are electrodes for transferring / resetting signals, and are for transferring signals from the electrode c5 toward the electrode c1. The electrode c5 is horizontal C
It corresponds to the last-stage electrode of CD14. The electrode c4 is for causing the charge detection unit a2 to output “output 2”, the electrode c3 is for transferring a signal from the charge detection unit a2 to the charge detection unit a1, and the electrode c2 is for transferring the signal to the charge detection unit a1. The electrode c1 is for outputting electric charges, and is for resetting the electric charges.

Next, a description will be given of an example of driving in the case where "output 1" and "output 2" are output from the output unit 15 of the solid-state imaging device 10 configured as described above. FIG. 1 (b)
Is a clock signal applied to the electrodes c5, c3, c1,
It shows the relationship between the states of “output 1” and “output 2”. In the drawing, the portions indicated by solid lines indicating “output 1” and “output 2” are the charge detection units a1, a
2 indicates a period during which “output 1” or “output 2” is generated.
It is assumed that 22 indicates a period during which “output 1” or “output 2” is held.

As shown in FIG. 1B, in the period t1,
The (N−1) th (N is an integer) signal is output as “output 1” from the charge detection unit a1, and the (N−1) th signal is output as “output 2” by the S / H circuit 22 in the S / H circuit 22. Have been. Hereinafter, similarly, as “output 1” / “output 2”, the (N−1) th / Nth period and the period t
3, the Nth / Nth signal is output in the period t4, the Nth / N + 1th signal is output in the period t5, and the N + 1th / N + 2th signal is output in the period t6.

Therefore, if the camera is constituted by using the solid-state imaging device 10 which outputs the output 1 after delaying the output 1 to the output 2 as described above, this camera has the output 1 and the output 2 S / H circuits 21 and 22 and a processing circuit 23 are provided at a subsequent stage, and after passing through these, the S / H circuit 2
By performing the sample-and-hold operation in step S4, the S / H circuit 24 performs processing such as addition / subtraction using two adjacent signals in an arbitrary combination or a combination of the same signals in addition to a predetermined combination as in the related art. This can be selectively performed by the phase of the resample and hold.

On the other hand, as compared with the case where processing such as addition is performed inside the solid-state imaging device, in this embodiment, since each element signal is output as independent information, the S / H circuit 2
4 can be freely added /
It becomes possible to select a signal to be subjected to processing such as subtraction and the like. Conventionally, for example, the first and second,
When adding in a predetermined combination such as the third and fourth, a different combination (for example, the second and third)
Could not be handled, but in this embodiment,
Arbitrary combination processing of the same signal or adjacent signals which could not be added internally in the conventional solid-state imaging device can be realized.

[Second Embodiment] Next, a second embodiment of a solid-state imaging device and a camera using the same according to the present invention will be described. However, here, only the differences from the above-described first embodiment will be described.

The camera according to the present embodiment is different from the first embodiment in the solid-state imaging device 10a. In this solid-state imaging device 10a, as shown in FIG.
The imaging area 13 is constituted by a plurality of photosensors 11 and the vertical CCD 12, and the vertical CCD 1
Two horizontal CCDs 16 and 17 for transferring the signal charges from the vertical CCDs 12 in the horizontal direction are arranged side by side on the output side.

Here, the horizontal CCDs 16 and 17 will be described in detail with reference to FIG. FIG. 5A is a plan image showing an example in which charge detection portions for obtaining two systems of “output 1” and “output 2” are arranged in parallel.

As shown in FIG. 5A, each horizontal CCD 1
In the output sides of the charge detection units f1 and f2, diffusion layers for obtaining “output 1” and “output 2” are provided.
Diffusion layers d1 and d2 for resetting signals, electrodes g1 and g2 for causing each of the charge detection units f1 and f2 to output "output 1" or "output 2", and "output 1" or "output". Electrodes e1 and e2 for resetting "2"
Each is provided. That is, the solid-state imaging device 1
0a is characterized in that the final transfer stages of the horizontal CCDs 16 and 17 are different from each other. Each horizontal CCD
16 and 17 are alternately arranged horizontal transfer electrodes h1 and h2.
Thus, the signal charges are transferred in the horizontal direction.

Next, a description will be given of a driving example in which "output 1" and "output 2" are output from each of the horizontal CCDs 16 and 17 of the solid-state imaging device 10a thus configured. FIG. 5B shows the relationship between the clock signals applied to the electrodes e1, e2, h1, and h2 and the states of “output 1” and “output 2”. In the figure,
The portions indicated by solid lines indicating “output 1” and “output 2” represent periods during which “output 1” or “output 2” is occurring in the charge detection units f1 and f2, and are followed by broken line portions. Represents a period during which “output 1” or “output 2” is held in the S / H circuits 21 and 22.

As shown in FIG. 5B, in the period t1,
The Nth (N is an integer) signal is output from the charge detection unit f1 as “output 1”, and the (N−1) th signal is output as S / H by the S / H circuit 22 as “output 2”. I have. Hereinafter, similarly, “output 1” / “output 2”
In the period t2, the Nth / N + 1th period, in the period t3, the (N + 2nd / N + 1) th period, and in the period t4, the (N + 2) th / Nth
The (N + 3) th / N + 3rd signal is output during the (N + 3) th period t5, and the (N + 4th / N + 5th) signal is output during the period t6.

Therefore, if the camera is constituted by using the solid-state imaging device 10a that outputs the "output 1" and the "output 2" in a state where the phases of the "output 1" and the "output 2" are different from each other by 180.degree. As in the case of the embodiment, it is possible to selectively perform processing such as addition / subtraction based on the phase of the re-S / H using an arbitrary combination of two adjacent signals.

In this embodiment, the processing of the same signal cannot be performed as in the first embodiment, but the time of the adjacent signal coincides with the outside of the solid-state imaging device 10a. This is similar to the first embodiment in that a delay circuit or the like is not required, and processing can be performed by an arbitrary combination unlike the case where addition is performed inside the solid-state imaging device.

As described above, in the solid-state imaging devices 10 and 10a according to the first and second embodiments described above,
The "output 1" and the "output 2" are output in a state where they are delayed from each other or in a state where the phases are different. Therefore, if a camera is configured using the solid-state imaging devices 10 and 10a, “output 1” and “output 2” are set to S
By performing processing such as addition or subtraction after passing through the / H circuits 21 and 22, processing by any combination can be performed without providing a delay circuit or the like separately from the solid-state imaging devices 10 and 10a. Become.

Moreover, the combination is based on the S / H circuit 2
By controlling the phases of “SH1”, “SH2” and “SH3” given to 1, 22, and 24, it becomes possible to select arbitrarily. That is, the output signal to be processed can be changed according to the phase of the sample hold pulse.

Therefore, in this case, processing such as addition / subtraction can be performed by an arbitrary combination, so that sensitivity can be improved by signal addition or the like without lowering the spatial resolution frequency. Moreover, the solid-state imaging devices 10 and 1
Since it is not necessary to provide a delay circuit or the like outside of the camera 0a, the configuration of the camera does not become complicated or large.

Further, if the solid-state imaging devices 10 and 10a according to the first and second embodiments described above are applied to the solid-state imaging device having the vertical / horizontal double-density structure, even when complementary color signal processing is performed. , So delay the output signal 1
There is no need to provide an H delay circuit or the like.

Further, if a comparison circuit is provided in the camera and "output 1" and "output 2" from the solid-state imaging devices 10 and 10a are input to the comparison circuit, high-frequency image defects can be detected. .

In the first and second embodiments described above, the case where the solid-state imaging devices 10 and 10a have outputs of two systems has been described as an example. However, the present invention is not limited to this. However, the present invention is also applicable to a case where three or more outputs are provided.

[0039]

As described above, in the solid-state imaging device of the present invention and the camera using the same, the voltage signals to be output by the signal output means of each system are delayed with respect to each other or output in different phases. So that
If processing such as addition or subtraction is performed after each output passes through, for example, a sample-and-hold circuit, processing by any combination can be performed without providing a delay circuit or the like separately from the solid-state imaging device. become.
Therefore, processing such as addition / subtraction using an arbitrary combination becomes possible, and the sensitivity can be improved by signal addition or the like without lowering the spatial resolution frequency. Moreover, since it is not necessary to provide a delay circuit or the like separately from the solid-state imaging device, the configuration of the camera does not become complicated or large.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating an outline of a first embodiment of a solid-state imaging device according to the present invention; FIG. 1A is a cross-sectional image diagram illustrating a schematic configuration of an output unit of the solid-state imaging device;
(B) is a conceptual diagram showing an example of driving output by the solid-state imaging device.

FIG. 2 is a block diagram showing a main part of an example of a camera using the solid-state imaging device according to the present invention.

FIG. 3 is a schematic configuration diagram of a solid-state imaging device according to the first embodiment.

FIG. 4 is a schematic configuration diagram of a solid-state imaging device according to a second embodiment of the present invention.

5A and 5B are explanatory diagrams illustrating an outline of a solid-state imaging device according to a second embodiment, in which FIG. 5A is a plan image diagram illustrating a schematic configuration of an output unit of the solid-state imaging device, and FIG. FIG. 5 is a conceptual diagram illustrating an example of driving output by an imaging device.

[Explanation of symbols]

10: solid-state imaging device, 13: imaging area, 14, 16, 1
7 horizontal CCD, 15 output unit, 21, 22 S / H circuit, 23 processing circuit, a1, a2, f1, f2 charge detection unit

Claims (2)

[Claims] 1. A solid-state imaging device comprising: an imaging unit that converts incident light into signal charges on a pixel basis; and an output unit that outputs the signal charges converted by the imaging unit as a voltage signal. A solid-state imaging device, comprising: a plurality of signal output units; and each of the signal output units outputs voltage signals to be output with a delay or a phase difference. 2. A camera using a solid-state imaging device that obtains a voltage signal from incident light, wherein the solid-state imaging device outputs a plurality of systems of signal signals that output voltage signals to be output with a delay or different phases. A sample-and-hold circuit individually corresponding to each signal output unit, and a process of performing a predetermined process on each of the voltage signals output through the sample-and-hold circuit, at a stage subsequent to the solid-state imaging device. A camera using a solid-state imaging device, wherein the camera is provided with a circuit.