JPH11340439A - Non-volatile ferroelectric memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile ferroelectric memory device and a method of manufacturing thereof, in which cell plate lines are dispensed with and thereby manufacturing process is simplified with the efficient layout by connecting the gate of a transistor to a split word line while a capacitor is connected to other split word line. SOLUTION: A metallic layer for bit lines is formed on a whole surface including contact holes. A first and a second bit line, 104a and 104b, are formed normal to a first and a second split word line, 93a and 93b, by selective patterning. In each block, a first and a second transistor, T1 and T2, are positioned inversely with respect to upper and lower directions. A capacitor is formed on block A and block B that are placed on split word lines, 93a and 93b, respectively, wherein the first transistor T1 is connected to block A and the second transistor T2 is connected to block B. Namely, the circuit is composed of laterally positioned block A and block B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a ferroelectric memory device using a ferroelectric material as a capacitor of a memory cell, and more particularly to a cell plate line conventionally required separately from a word line. , The layout design can be performed efficiently, and the manufacturing process can be simplified.

[0002]

2. Description of the Related Art A ferroelectric memory device which stores data even when the power is turned off at a data processing speed of a DRAM generally used as a semiconductor memory device, that is, an FRA.
M is in the spotlight as a next-generation storage device. FRAM
Is a storage device comprising a transistor and a capacitor which are almost the same as a DRAM, and uses a ferroelectric as a material of a dielectric layer of the capacitor. This is a storage device in which data is not erased even when an electric field is removed by using a high remanent polarization, which is a characteristic of a ferroelectric substance. Ferroelectrics, when placed in an electric field, have the characteristics shown in the hysteresis loop of FIG. The polarization induced by the electric field does not disappear due to the spontaneous polarization even when the electric field is removed, and maintains a certain amount (d, a state). The d and a states correspond to 1, 0, respectively, and are applied as storage elements.

A conventional ferroelectric memory device will be described below with reference to the accompanying drawings. FIG. 2 is a configuration diagram of a unit cell of a conventional ferroelectric memory, FIG. 3 is a configuration diagram of a cell array of a conventional ferroelectric memory, and FIG. 4 is an operation waveform of a conventional ferroelectric memory device. FIG. The most ideal structure of FRAM using a ferroelectric thin film is DR
It is similar to the structure of AM, but has the problem of integration that is difficult to solve unless new electrode materials and barrier materials are presented. A problem in terms of integration is that capacitors cannot be formed directly on a silicon substrate or polysilicon, and DRAMs of the same capacity
This is because the area becomes wider. Further, when the electric field is repeatedly applied to the ferroelectric material to repeat the polarization inversion, a fatigue phenomenon of the thin film in which the amount of remanent polarization is reduced occurs, and there is a problem in reliability. An FRAM having a structure as shown in FIG. 2 has been proposed in consideration of all such realistic circumstances (development of an alternative electrode material, integration degree, stability of a ferroelectric thin film, operation reliability, etc.). It is.

The conventional FRAM shown in FIG. 2 has an NM in which each gate is commonly connected to a word line (WL) 5.
A first ferroelectric capacitor (C1) 2 and a second ferroelectric capacitor (C2) each including an OS first transistor (T1) 1 and a second transistor (T2) 3 using a ferroelectric material.
4 is a structure connected to each transistor. The source of the first transistor 1 is connected to the bit line (Bi
t_n) 6, and the drain is connected to the first capacitor 2. On the other hand, the source of the second transistor is /
The bit line (BitB_n) 7 is connected, and the drain is connected to the second capacitor 4. In addition, "/" means that it is in an inverted state. One of the electrodes of the first ferroelectric capacitor 2 is connected to the drain of the first transistor 1 at a node (N1), and the other is connected to a cell plate line (CPL) 8 arranged in parallel with the word line. . Similarly, one electrode of the second ferroelectric capacitor 4 has a node 2 (N2) connected to the drain of the second transistor 3.
And the other electrode is connected to the cell plate line (CP
L) Connected to 8.

[0005] In the conventional FRAM having the above structure, a cell array is formed in the form shown in FIG. That is, word lines and plate lines are arranged in parallel in the row direction, and bit lines and / bit lines are arranged in parallel in the column direction. Each memory cell is located at the intersection of a row and a column. Each memory cell can be accessed by selecting both the row and the column.

The reading operation of the FRAM having the above circuit structure will be briefly described below. As shown in FIG.
Is enabled from “high” to “low” and WEBpa
d transitions from "low" to "high" and the read mode begins. Then, before the corresponding word line is selected, all bit lines and / bit lines are equalized to low (Vss) by the equalizer signal. After completing the equalization to a low voltage, the address is decoded. The signal applied to the corresponding word line is changed from "low" to "high" according to the decoded address, and the corresponding cell is selected. A "high" signal is applied to the plate line of the selected cell to destroy data on the bit line or / bit line. That is, when the logic value “1” is recorded, the data of the capacitor connected to the bit line is destroyed, and when the logic value “0” is recorded, the data of the capacitor connected to the bit line is lost. Data is destroyed. As described above, depending on which data of the bit line and / or the bit line is destroyed, different values are output according to the above-described hysteresis loop principle. Therefore, the sense amplifier senses the data output through the bit line and / or the bit line, and senses the logic value “1” or “0”. As described above, since the sense amplifier must amplify and output the data of the memory cell and restore the original data, the plate line is changed from “high” to “high” with “high” applied to the corresponding word line. Inactivate low. Thereby, the data is restored.

[0007]

Such a conventional FRAM requires a plate line in addition to a word line, so that the structure of a memory cell becomes complicated and occupies a large area. There is a point. further,
Since the word line and the plate line receive different control signals, it is difficult to control the signals in the data input / output operation. The present invention relates to such a prior art FRAM.
The purpose of the present invention is to solve the above problem, and the purpose is to eliminate the need for the cell plate line required in addition to the word line, thereby providing an efficient layout of the ferroelectric memory device. In order to simplify the manufacturing process.

[0008]

SUMMARY OF THE INVENTION A nonvolatile ferroelectric memory device according to the present invention, which relates to an efficient layout design and manufacturing process of a ferroelectric memory in which a cell plate line is not separately formed, comprises two word lines. A split word line configuration that can be selected by one address, and the gates of transistors are connected to the split word lines, respectively.
A capacitor connected to the transistor is connected to the other split word line. More specifically, the first and second active regions having portions arranged in parallel and separated from each other and formed on a semiconductor substrate are formed in parallel across a first direction orthogonal to the parallel direction. A source / drain formed on both sides of the first and second split word lines in the first active region, on both sides of the first split word line in the second active region, and a first and second split word line, respectively. A barrier conductive material layer stacked on each of the lines, a first electrode layer of the capacitor, a ferroelectric layer, and one of a source / drain of the second active region;
A second electrode layer of a first capacitor formed on a first split word line, connected to one of a source / drain of the first active region, and a second capacitor layer formed on a second split word line. A second electrode layer, connected to the other of the source / drain of the first active region,
A first bit line formed perpendicular to the first and second split word lines in the second direction and the other of the source / drain of the second active region are connected to the first and second split word lines. And a second bit line formed perpendicularly to the direction.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile ferroelectric memory device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 5 is a unit cell configuration diagram of the ferroelectric memory device according to the embodiment of the present invention, FIG. 6 is a cell array configuration diagram of a ferroelectric memory device using the cell, and FIG.
FIG. 7 is an operation waveform diagram of the ferroelectric memory device having the array of FIG. As shown in FIG. 5, the word line has a split word line structure, the gate of the first transistor is connected to the first split word line SWL1, and the switch SW
Second split word line SW paired with L1
The gate of the second transistor T2 is connected to L2. In this embodiment, the paired first and second split word lines SWL1 and SWL2 correspond to one row and are accessed by one address.

The gate is connected to the first split word line SW
The first transistor T1 connected to L1 has one electrode connected to the bit line Bit_n and the other electrode connected to the first ferroelectric capacitor FC1. The other electrode of the ferroelectric capacitor is connected to the second split word line SWL2. Symmetrically to the first transistor T1, the gate is connected to the second split word line SWL2, the second transistor T2 has one electrode connected to the other bit line Bit_n, and the other electrode connected to the first split word line SWL1. One electrode of the connected second ferroelectric capacitor FC2 is connected to the other electrode.

The operation of the FRAM according to the present embodiment having the above structure is as follows. As shown in the operation waveform diagram of FIG. 7, in the case of the write mode, when the bit lines B_n and B_n + 1 are applied with high and low or vice versa, FIG.
As shown in the first and second split word lines SWL
Drive signals SWLS1 and SWLS2 of the first split word line SWL1
By dropping W1 to low and then driving SWL1 and SWL2 in reverse, data corresponding to the signal of the bit line can be stored in each capacitor. In the case of reading, as shown in FIG. 7, a drive pulse is given to each of the split word lines SW1 and SW2, and the data stored from the capacitors FC1 and FC2 are sent out to the bit lines B_n and B_n + 1, respectively. SAN and SAP for driving the
Read each data with. Upon reading, the polarization of the capacitor in which the logic "1" was stored is destroyed, and the data must be stored again in the dielectric capacitor.

In order to store the destroyed logic "1" in the first and second ferroelectric capacitors FC1 and FC2, the following additional timing pulse is required. Logic "1" is applied to the first ferroelectric capacitor FC1.
However, when the state of logic "0" is stored in the second ferroelectric capacitor FC2, in order to store the logic "1" again in the first ferroelectric capacitor FC1, the first split word line SWL1 must be connected. A high signal may be applied, and a low signal may be applied to the second split word line SWL2.

The high voltage of the bit line Bit_n is applied to one electrode of the first ferroelectric capacitor FC1 through the first transistor T1 turned on by the SWLS1, and the low voltage is applied to the other electrode by the SWLS2. Therefore, the first ferroelectric capacitor FC
One can store the logic "1" again. And
When the state of logic "0" is stored in the first ferroelectric capacitor FC1 and the state of logic "1" is stored in the second ferroelectric capacitor FC2, the logic "1" is again stored in the second ferroelectric capacitor FC2. To store data, a low signal may be applied to the first split word line SWL1 and a high signal may be applied to the second split word line SWL2.
This is because the high data of the bit line Bit_n is SWLS
2, a high voltage is applied to one electrode of the second ferroelectric capacitor FC2 through the second transistor T2 turned on by the second transistor T2, and a low voltage is applied to the opposite reference electrode by SWLS1 to apply a logic voltage to the second ferroelectric capacitor FC2. "1" is stored again. This SWL cell array structure cannot enable only one word line, but always enables a pair of SWL1 and SWL2 simultaneously.

Hereinafter, the SW of the present invention having such a structure will be described.
The layout design and manufacturing process of the L cell array will be described. FIG. 8 is a configuration diagram showing block divisions at the time of layout design according to the first embodiment of the present invention. In the first embodiment of the present invention, two adjacent blocks A and B constitute a unit cell. The A block includes a first transistor T1, first and second ferroelectric capacitors FC1, FC2,
A bit line B_n and a node N1 are formed, and a second transistor T2, first and second ferroelectric capacitors FC1 and FC2, a bit line B_n + 1, and a node N2 are formed in the B block. That is, the capacitors in this embodiment are each formed over each part lock, and each block is formed by half.

The sectional structure according to the first embodiment of the present invention will be described with reference to the drawing shown in the lower part of FIG. The upper part of the figure is a layout diagram, which will be referred to. The lower cross section is A
It is a cross section of a block, and a B block is formed symmetrically to this. An element isolation layer 91 is formed in an element isolation region of a semiconductor substrate 90 to define an active region, and the active region is insulated from the substrate by a gate oxide film 92, and crosses the active region in a first direction to form first and second splits. Word lines 93a and 93b are formed. Needless to say, these are the parts that become the gates of the transistors. Source / drain regions 96 are formed on both sides of these gates of the semiconductor substrate 90. A barrier conductive material layer 94 of the same size is laminated on the first and second split word lines 93a and 93b, and a first electrode layer 9 of a capacitor is formed thereon.
5 are formed. Therefore, the first and second word lines 93a and 93b, that is, the gate electrode and the first electrode layer 95 of the capacitor are the same. Of course, different materials are used, but they are electrically the same.
A first oxide film 97a is formed on the side surfaces of the first and second split word lines 93a and 93b and the barrier conductive material layer 94 thereon and a part of the side surface of the first electrode layer 95 of the capacitor, and is in contact with the oxide film 97a. The SOG layer 98 is formed at the same height as the film 97a. This SOG layer 9
Reference numeral 8 is formed so as to fill the space between the first and second split word lines 93a and 93b. The first of capacitors
A ferroelectric layer 99 surrounding the electrode layer 95 and on the SOG layer
Is formed, and a second electrode layer 100a of the capacitor is formed to face the first electrode layer 95 on the dielectric layer. The contact plug layer 102 is connected to the source / drain region 96 so as to connect any one of the source / drain regions 96 and the second electrode 100a of the capacitor.
It is formed to stand up from. In addition, the second
The three oxide films 97b and 97c are formed so as to be insulated from the peripheral layer, and are brought into contact with another region of the source / drain region 96 in a second direction substantially orthogonal to the first and second split word lines. , 2 bit lines 104a,
104b are formed.

FIGS. 9 to 24 are views showing a manufacturing process of the ferroelectric memory according to the first embodiment of the present invention, wherein the upper side is a layout configuration diagram and the lower side is a sectional view. First, as shown in FIG. 9, an element isolation layer 91 is formed in a predetermined region of a semiconductor substrate 90 by a field oxidation process to partition an active region where a cell transistor, a ferroelectric capacitor, and the like are formed. Here, a rectangular block having a major axis and a minor axis is repeated in the semiconductor substrate 91 as shown in the figure, and a certain block is defined as A, and a block on the right thereof is defined as B block,
The lower side of the B block is the A block, the left side thereof, that is, the lower side of the first A block is the B block again, and four blocks adjacent at one point are arranged in the clockwise direction as the A block, the B block, the A block, and the B block. However, these are repeated a plurality of times. Then, the active area of the A block is
It is formed so as to extend from one corner of the rectangle toward the center of the short side of the rectangle so as to extend to a role of 45 °, and to extend from the front end thereof at the substantially center of the rectangle along the long side.
The tip of the vertically descending portion of the active region does not reach the short side of the rectangle, and the tip has an angle of approximately 45 ° and is cut off obliquely to the upper right in the drawing. A triangular active region is also formed at the corner of the rectangle opposite to the diagonally cut end of the A block. The shape of the active region of the B block is a shape obtained by turning the shape of the A block upside down by 180 ° around the boundary between the A block and the B block, and turning it upside down. The other A block rotates the previous A block by 180 ° and arranges it below the B block, and the other B block similarly positions the previous B block by 18 °.
Rotated by 0 ° and placed below the first A block. Therefore, the active areas of both B books are connected, the two ends are displaced in parallel at a constant width, and the two areas are connected obliquely, and the active areas of the A block are separated from each other. is there. The active areas of the A block and the adjacent B block have portions parallel to each other. One of the active regions of the A and B blocks arranged in parallel may be referred to as a first active region, and the other may be referred to as a second active region. Word lines are formed in a direction substantially orthogonal to these active regions.

Next, as shown in FIG.
A gate oxide film 92, a polysilicon layer 93 for gate formation, and a gate oxide film 92 are formed on the entire surface of the semiconductor substrate 90 where the active regions are partitioned to form the two split word lines SWL1 and SWL2.
Barrier conductive material layer 94, first electrode layer 95 of capacitor
Are sequentially formed. Then, the stacked structure is selectively etched by a photolithography process to form the first and second split word lines 93a and 93b in parallel in a certain direction. As shown in the figure, the shape is not a perfect straight line but a bumpy shape. This is a problem of the gate formation location, and the position of the transistor can be adjusted so as to be aligned on a straight line. The barrier conductive material layer 94 may be oxidized into a high-resistance material layer in a subsequent heat treatment process. In order to prevent a problem due to the oxidation, the barrier conductive material layer 94 is patterned with the first electrode layer 95 of the capacitor in the peripheral circuit region. The gate forming material layers 93 are brought into contact with each other.
Then, the first electrode layer 95 of the capacitor is formed using a metal such as Pt.

Next, as shown in FIG. 11, the patterned first and second split word lines 93a and 93b
Is used as a mask, an N ⁺ impurity is implanted into the exposed active region, and a source / drain region 96 is formed through a heat treatment process. As shown in FIG. 12, a thin first oxide film 97a is deposited on the entire surface on which the first and second split word lines 93a and 93b are formed. As shown in FIG.
A planarizing insulating layer 98 is formed thick on the oxide film 97a. At this time, the flattening insulating layer 98 fills the space between the first and second split word lines 93a and 93b using SOG or BPSG. Next, as shown in FIG. 14, when SOG is used, the planarization insulating layer 98 is heat-treated at 800 to 900 ° C. to reduce the volume by 20 to 30%. This prevents flow in a subsequent heat treatment step and prevents problems such as deterioration of device characteristics from occurring. After the viscosity of the flattening insulating layer 98 is thus increased, the flat over-insulating layer 98 is removed by a constant thickness in an etch-back process as shown in FIG. At this time, the first on the capacitor first electrode layer 95
The oxide film 97a is also removed to remove the first electrode layer 95 of the capacitor.
Expose part of

Next, as shown in FIG. 16, a ferroelectric layer 99 is formed on the entire surface including the exposed first electrode layer 95 of the capacitor. As shown in FIG. 17, Pt metal is deposited on the entire surface of the ferroelectric layer 99 to form the second electrode layer 100 of the capacitor. Next, as shown in FIG. 18, the second electrode layer 100 of the capacitor is selectively patterned to form a second electrode 100a of the capacitor used as a plate electrode of the capacitor. As shown in FIG. 19, a second oxide film 97b is formed on the entire surface including the second electrode 100a of the patterned capacitor. As shown in FIG. 20, the second oxide film 97b on one of the source / drain impurity regions formed on both sides of the first and second split word lines 93a and 93b, the ferroelectric layer 99, and the planarization insulation The layer 98 and the first oxide film 97a are selectively removed to form a contact hole 101 for bringing one electrode of the capacitor into contact with one electrode of the cell transistor. Then, as shown in FIG. 21, a contact plug layer 102 filling the contact hole 101 is formed. As shown in FIG. 22, a third oxide film 97c is deposited on the entire surface including the contact plug layer 102. As shown in FIG. 23, a third oxide film 97c, a second oxide film 97b, and a ferroelectric layer on the other source / drain impurity regions formed on both sides of the first and second split word lines 93c and 93b. 9
9. A contact hole 103 for selectively contacting the bit line with the other electrode of the cell transistor is formed by selectively removing the planarizing insulating layer 98 and the first oxide film 97a.

Next, as shown in FIG. 24, a metal material layer for forming a bit line is formed on the entire surface including the contact hole 103, and is selectively patterned to be perpendicular to the first and second split word lines 93a and 93b. The first and second bit lines 104a and 104b are formed in different directions. Instead of using the planarizing film SOG, the third oxide film 97c may be thickened to fill the gap between the split word lines.

As shown in FIG. 24, the first transistor T1 and the second transistor T
2, a capacitor is formed over the A block and the B block on each split word line, and the first transistor T1 is connected by the A block, and the second transistor T2 is connected by the B block. I have. That is, the circuit of FIG. 8 is constituted by two blocks A and B arranged side by side.

The layout and process sequence of the second embodiment will be described below with reference to FIGS. First, FIG.
As shown in FIG. 7, an element isolation layer 91 is formed in a predetermined region of a semiconductor substrate 90 by a field oxidation process to partition an active region where a cell transistor, a ferroelectric capacitor, and the like are formed. Its shape is the same as that of the first embodiment. Next, as shown in FIG. 26, to form the first and second split word lines SWL1 and SWL2, a gate oxide film 92 is formed on the entire surface of the semiconductor substrate 90 in which the active region is partitioned.
A gate forming material layer 93, a barrier conductive material layer 94, and a first electrode layer 95 of the capacitor are sequentially formed. Then, the laminated structure is selectively etched by a photolithography process to form first and second split word lines 93a, 93a.
3b is formed. The barrier conductive material layer 94 may be oxidized into a high-resistance material layer in a subsequent heat treatment process. To prevent a problem from occurring, the barrier conductive material layer 94 and the first electrode layer 95 of the capacitor patterned in the peripheral circuit region are formed. The forming material layers 93 are brought into contact with each other. The first electrode layer 95 of the capacitor is formed using a metal such as Pt.

Next, as shown in FIG. 27, the patterned first and second split word lines 93a and 93b
Is used as a mask, an N ⁺ impurity is implanted into the exposed active region, and a source / drain region 96 is formed through a heat treatment process. As shown in FIG. 28, a thin first oxide film 97a is deposited on the entire surface on which the first and second split word lines 93a and 93b are formed. Next, as shown in FIG.
A photoresist layer 98a is formed on oxide film 97a.
At this time, the photoresist layer 98a fills the space between the first and second split word lines 93a and 93b. And
As shown in FIGS. 30 and 31, a photoresist layer 98 is formed.
is removed by a constant thickness in an etch-back process, and the first oxide film 97a on the first electrode layer 95 of the capacitor is etched back to expose the first electrode layer 95 of the capacitor.

Next, as shown in FIG. 32, the photoresist layer 98a is removed with the first oxide film 97a on the first electrode layer 95 of the capacitor removed. As shown in FIG. 33, a ferroelectric layer 99 is formed on the entire surface including the exposed first electrode layer 95 of the capacitor. Then, as shown in FIG. 34, Pt metal is deposited on the entire surface of the ferroelectric layer 99 to form the capacitor second electrode layer 100. Next, as shown in FIG. 35, the second electrode layer 100 of the capacitor is selectively patterned to form a second electrode 100a of the capacitor used as a plate electrode of the capacitor. Then, as shown in FIG. 36, a second oxide film 97b is formed on the entire surface including the second electrode 100a of the patterned capacitor. Next, as shown in FIG. 37, the second oxide film 97b and the ferroelectric layer 99 on one of the source / drain impurity regions formed on both sides of the first and second split word lines 93a and 93b. A contact hole 1 for selectively removing the first oxide film 97a and bringing one electrode of the capacitor into contact with one electrode of the cell transistor.
01 is formed. Then, as shown in FIG. 38, the lower bottom surface and side surfaces of the contact hole 101, the second oxide film 97b
Is formed over a part of the upper surface of the substrate.

Next, as shown in FIG.
A third oxide film 97c is deposited on the entire surface including the second word line 02a to a sufficient thickness so as to fill the space between the first and second split word lines 93a and 93b. Then, as shown in FIG.
A third oxide film 97c, a second oxide film 97b, a ferroelectric layer 99, and a first oxide film 97a on another source / drain impurity region formed on both sides of the first and second split word lines 93a and 93b. Are sequentially removed to form a contact hole 103 for bringing the bit line into contact with the other electrode of the cell transistor. Next, as shown in FIG. 41, a metal material layer for forming a bit line is formed on the entire surface including the contact hole 103, and selectively patterned to form a metal layer for the bit line in a direction perpendicular to the first and second split word lines 93a and 93b. 1 and 2 bit lines 104a and 104b are formed.

Further, a description will be given of a ferroelectric memory according to a third embodiment of the present invention, in which block divisions are different at the time of layout design. FIG. 42 is a configuration diagram showing block divisions at the time of layout design according to the third embodiment of the present invention. The SWL ferroelectric memory according to the third embodiment of the present invention includes shunt split word lines (SSWL1, SSWL1) connected to one electrode of each ferroelectric capacitor in addition to the split word lines SWL1, SWL2.
WL2). As shown in FIG.
A pair of SWL1 and SWL2 including SSWL1 and SSWL2 respectively corresponds to one row, and a pair of Bit_n and Bit_n + 1 forms two columns. There is no difference from the previous example except that SSWL1 and SSWL2 are formed as described above and one electrode of the ferroelectric capacitor is connected thereto. In the third embodiment of the present invention configured as described above, each transistor and capacitor are designed to be formed separately in two blocks A and B.

An A block having an active region isolated by an element isolation layer and a B block having another active region adjacent thereto are formed. The A block includes a first transistor T1, a first ferroelectric capacitor FC1, A bit line Bit_n, a node 1 (N1), a first shunt split word line SSWL1 are formed, and a second transistor T2 and a second ferroelectric capacitor FC are provided in the B block.
2, bit line Bit_n + 1, node 2 (N2),
A second shunt split word line SSWL2 was formed. Hereinafter, the cross-sectional structure is shown together with the manufacturing process.

FIGS. 43 to 51 are a layout configuration and a process sectional view of the ferroelectric memory according to the third embodiment of the present invention. First, as shown in FIG. 43, an element isolation layer 91 is formed in a predetermined region of a semiconductor substrate 90 by a field oxidation process to partition an active region in which a cell transistor, a ferroelectric capacitor, and the like are formed. The block shape is the same as the previous embodiment. Next, as shown in FIG. 44, the semiconductor substrate 9 is formed to form the first and second split word lines SWL1 and SWL2 which constitute one SWL unit cell.
A gate oxide film 92 and a polysilicon layer for gate formation are formed on the entire surface of the gate electrode 0. Then, the first and second split word lines 93a and 93b are formed by selective etching in a photolithography process. Next, as shown in FIG. 45, using the patterned first and second split word lines 93a and 93b as a mask, N ⁺ impurities are implanted into the exposed active region, and a source / drain region 96 is formed through a heat treatment process. I do.

Then, as shown in FIG. 46, a first interlayer insulating layer 105a is formed on the entire surface where the first and second split word lines 93a and 93b are formed, and any one of the impurity regions of the source / drain region 96 is formed. The bit line contact hole 106 is formed by selectively removing the upper first interlayer insulating layer 105a. As shown in FIG. 47, first interlayer insulating layer 1 including bit line contact hole 106
A metal material layer for forming a bit line is formed on the entire surface of 05a so that the bit line contact hole 106 is completely buried. The first and second split word lines 93 are selectively formed by selectively patterning the bit line forming metal material layer.
a, the first and second bit lines 104 in a direction perpendicular to 93b.
a, 104b are formed. Then, as shown in FIG. 48, a second interlayer insulating layer 105b is formed on the entire surface including the first and second bit lines 104a and 104b. afterwards,
The capacitor contact hole 107 is formed by selectively removing the second interlayer insulating layer 105b and the first interlayer insulating layer 105a on another source / drain impurity region.

Next, as shown in FIG. 49, a conductive material layer is formed on the entire surface including the capacitor contact hole 107.
An interlayer insulating layer (not shown) is formed, and the interlayer insulating layer and the conductive material layer are patterned so as to remain only in the capacitor formation region. Then, a conductive material layer is formed again on the entire surface including the patterned interlayer insulating layer, and an etch back process is performed so that the second conductive material layer formed on the side surface of the interlayer insulating layer remains in the form of a sidewall. To form a first electrode layer 95 of the capacitor. Next, a not-shown interlayer insulating layer is removed, and a ferroelectric layer 99 is formed on the entire surface on which the first electrode layer 95 of the rectangular tube or other bottomed cylindrical capacitor whose edge is raised is formed. , The second electrode layer 10 of the capacitor is buried in the recessed portion of the first capacitor electrode layer 95.
0 is formed. Then, the second electrode layer 10 of the capacitor
0, a part of the ferroelectric layer 99 and a part of the first electrode layer 95 of the capacitor are removed to a certain thickness by a process such as CMP to isolate the capacitor for each block. Next, as shown in FIG. 50, a third interlayer insulating layer 105c is formed on the entire surface including the second electrode 100 of the capacitor, and the second electrode 10c of the capacitor is formed.
By removing a part of the third interlayer insulating layer 105c above the zero, a shunt split word line contact hole 108 is formed.

Then, a metal layer is formed on the entire surface including the shunt word line contact holes 108 and selectively etched to form first and second shunt split word lines 109a and 109b. In a subsequent process, the first shunt split word line 109a and the first split word line 93a are brought into contact with each other in a peripheral circuit region outside the cell array so that the same signal is applied to the two lines. Similarly, the second shunt split word line 109b and the second split word line 93b are brought into contact in a peripheral circuit region outside the cell array so that the same signal is applied to the two lines. As shown in FIG. 51, in this embodiment, a transistor and a capacitor are formed for each block, and the capacitor is formed in parallel with each block and has a three-dimensional shape with its edges rising to increase the surface area. be able to.

Next, a fourth embodiment of the present invention for designing the layout shown in FIG. 42 will be described with reference to FIGS. First, as shown in FIG. 52, an element isolation layer 91 is formed in a predetermined region of a semiconductor substrate 90 by a field oxidation process to partition an active region in which a cell transistor, a ferroelectric capacitor, and the like are formed. The shape is the same as the previous example. Next, as shown in FIG. 53, a gate oxide film 92 and a polysilicon layer for gate formation are formed on the entire surface of the semiconductor substrate 90 to form the first and second split word lines SWL1 and SWL2. Then, the gate formation polysilicon layer is selectively etched by a photolithography process to form the first and second split word lines 93a, 93a.
3b is formed.

Next, as shown in FIG. 54, the patterned first and second split word lines 93a and 93b
Is used as a mask, an N ⁺ impurity is implanted into the exposed active region, and a source / drain region 96 is formed through a heat treatment process. Then, as shown in FIG. 55, the first and second split word lines 93a and 93b are formed over the entire surface thereof.
An interlayer insulating layer 105a is formed, and the source / drain regions 9 are formed.
6, the first interlayer insulating layer 10 on one of the impurity regions
5a is selectively removed to form a bit line contact hole 106. Next, as shown in FIG. 56, the first interlayer insulating layer 1 including the bit line contact hole 106 is formed.
A metal material layer for forming a bit line is formed on the entire surface of 05a so that the bit line contact hole 106 is completely buried. The first and second split word lines 93 are selectively formed by selectively patterning the bit line forming metal material layer.
a, the first and second bit lines 104 in a direction perpendicular to 93b.
a, 104b are formed.

Then, as shown in FIG. 57, a second interlayer insulating layer 105b is formed on the entire surface including the first and second bit lines 104a and 104b. Next, the second interlayer insulating layer 105b on another impurity region of the source / drain, the first
Capacitor contact hole 107 is formed by selectively removing interlayer insulating layer 105a. Next, as shown in FIG. 58, the first electrode layer 95 of the capacitor is formed on the entire surface of the second interlayer insulating layer 105b so as to completely fill the capacitor contact hole 107, and the first electrode layer 9 of the capacitor is formed.
5, a ferroelectric layer 99, a second electrode layer 100 of the capacitor
Is formed, and the capacitor first electrode layer 95, the ferroelectric layer 99, and the capacitor second electrode layer 100 are selectively patterned to form a capacitor.

Next, as shown in FIG. 59, a third interlayer insulating layer 105c is formed on the entire surface including the second electrode 100 of the capacitor, and a part of the third interlayer insulating layer 105c on the second electrode 100 of the capacitor is formed. Is removed to form a shunt split word line contact hole. Then, as shown in FIG. 60, a metal layer is formed on the entire surface including the shunt word line contact holes 108 and selectively etched to form the first and second shunt split word lines 1.
09a and 109b are formed. In a subsequent process, the first shunt split word line 109a and the first split word line 93a are brought into contact with each other in a peripheral circuit region outside the cell array so that the same signal is applied to the two lines. Similarly, the second shunt split word line 1
09b and the second split word line 93b are brought into contact in a peripheral circuit area outside the cell array so that the same signal is applied to the two lines.

Hereinafter, a description will be given of a ferroelectric memory according to a fifth embodiment of the present invention in which the structure of unit cells and the block division are different during layout design. FIG. 61 is a configuration diagram showing block divisions at the time of layout design according to the fifth embodiment of the present invention. SWL according to a fifth embodiment of the present invention
The ferroelectric memory has split word lines SWL1, SWL
In addition to WL2, shunt split word lines (SSWL1, SSWL1) connected to one electrode of each ferroelectric capacitor are formed as in the fourth embodiment, and two capacitors are formed in one cell. As shown in FIG. 61, a pair of SWL1 and SWL2 (including SSWL1 and 2) corresponds to one row, and a pair of Bit_n and Bit_n + 1 forms two columns. That is, the first and second split word lines SWL1 and SWL repeatedly formed in parallel with each other.
2, the first and second split word lines SWL1, SW
The first and second shunt split word lines SSWL1 and SSWL2 shunted from L2, the first transistor T1 having a gate connected to the first split word line SWL1, and the second transistor having a gate connected to the second split word line SWL2. The second transistor T2 and one electrode of the first transistor T1 are connected, and a bit line Bit_n formed perpendicular to the first and second split word lines SWL1 and SWL2 and one electrode of the second transistor T2 are connected. Being parallel to the bit line Bit_n, the first and second split word lines SWL1, SWL
Bit line Bit_ configured to be perpendicular to
n + 1, one electrode is connected to the other electrode of the first transistor T1, and the second split word line SWL2
And a lower first ferroelectric capacitor FC1-1 connected to the other electrode of the first transistor T1, one electrode connected to the other electrode of the first transistor T1, and the other electrode connected to the second shunt split word line SSWL2. An upper first ferroelectric capacitor FC1-2 and a lower second ferroelectric capacitor FC2 having one electrode connected to the other electrode of the second transistor T2 and the other electrode connected to the second split word line SWL2. -1 and the second transistor T2
And an upper second ferroelectric capacitor FC2-2 having one electrode connected to the other electrode and the other electrode connected to the first shunt split word line SSWL1.

In the fifth embodiment of the present invention having such a structure, each cell (a basic unit capable of storing two data) is divided into two blocks A and B, and each block is divided as follows. Designed.

The A block includes a first transistor T1, upper and lower first ferroelectric capacitors FC1-1, FC1-
2, and upper and lower second ferroelectrics (capacitor FC2-
1, FC2-2), bit line Bit_n, node 1
(N1), first shunt split word line SSW
L1 is formed, and a second transistor T2 is provided in the B block.
Upper and lower first ferroelectric capacitors FC1-1, FC1-
2, and upper and lower second ferroelectric capacitors FC2-
1, FC2-2, bit line Bit_n + 1, node 2 (N2), second shunt split word line SS
WL2 was formed.

The layout and process sequence of the ferroelectric memory according to the fifth embodiment of the present invention having such a sectional structure will be described below. The shape of the active area of each of blocks A and B is the same as that of the previous embodiment as shown in FIG. Next, as shown in FIG. 63, in order to form the first and second split word lines SWL1 and SWL2, a gate oxide film 92 and a gate forming polysilicon layer 93 are formed on the entire surface of the semiconductor substrate 90 in which the active region is partitioned. , A barrier conductive material layer 94 and a first electrode layer 95 of the capacitor are sequentially formed. Then, the stacked structure is selectively etched in a photolithography process to form first and second split word lines 93a and 93b. The barrier conductive material layer 94 may be oxidized into a high-resistance material layer in a subsequent heat treatment process, but in order to prevent a problem from occurring, the barrier conductive material layer 94 and the first electrode layer 95 of the capacitor patterned in the peripheral circuit region may be removed. The gate forming material layers 93 are brought into contact with each other. The first electrode layer 95 of the capacitor is Pt
And the like.

Next, as shown in FIG. 64, the patterned first and second split word lines 93a and 93b
Is used as a mask, an N ⁺ impurity is implanted into the exposed active region, and a source / drain region 96 is formed through a heat treatment process. Then, as shown in FIG. 65, a thin first oxide film 97a is deposited on the entire surface on which the first and second split word lines 93a and 93b are formed. As shown in FIG. 66, a planarization insulating layer 98 is formed on the thin first oxide film 97a. The planarization insulating layer 98 is made of SOG or BPSG, and has first and second split word lines 93a and 93b.
Fill between b.

Then, as shown in FIG. 67, when SOG is used as the planarizing insulating layer 98, the temperature is 800 to 900 ° C.
To reduce the volume by 20-30%. This prevents a flow in a subsequent heat treatment step, so that a problem of deterioration of device characteristics does not occur. After improving the viscosity of the planarization insulating layer 98 in this way, as shown in FIG. 68, the planarization insulating layer 98 is removed by a constant thickness in an etch-back process. At this time, the first oxide film 97a on the first electrode layer 95 of the capacitor is also removed, exposing the first electrode layer 95 of the capacitor. Next, as shown in FIG. 69, a first ferroelectric layer 99a for forming a lower capacitor is formed on the entire surface including the exposed first electrode layer 95 of the capacitor. Then, as shown in FIG. 70, a metal such as Pt is vapor-deposited on the entire surface of the first ferroelectric substance 99a to form the second electrode layer 10 of the capacitor.
0 is formed. Next, as shown in FIG. 71, the second electrode layer 100 of the capacitor is selectively patterned to form a second electrode 100a of the capacitor used as a plate electrode of the capacitor.

Then, as shown in FIG. 72, the second electrode 1
00a, and a second oxide film 97b is formed thereon. Further, as shown in FIG. 73, the second oxide film 97b and the first ferroelectric layer 99a on one of the source / drain impurity regions formed on both sides of the first and second split word lines 93a and 93b. , Planarization insulating layer 9
8. The first oxide film 97a is selectively removed to form a contact hole 101 for bringing one electrode of the capacitor into contact with one electrode of the cell transistor. Then, as shown in FIG. 74, a contact plug layer 102 filling the contact hole 101 is formed. After that, the second oxide film 97b is removed. The second oxide film 97b is for avoiding contact with the electrode of the capacitor (the electrode on the left side of the figure) which does not need to be connected to the transistor. Next, as shown in FIG. 75, a second ferroelectric layer 99b is deposited on the entire surface including the contact plug layer 102. And FIG.
As shown in FIG. 7, a metal material layer for forming an upper capacitor is formed on the second ferroelectric layer 99b, and is patterned to form first and second shunt splits in the same form as the lower split word lines 93a and 93b. Word line 1
09a and 109b are formed.

In the subsequent steps, the first shunt split word line 109a and the first split word line 93a
In the peripheral circuit area outside the cell array so that the same signal is applied to the two lines. Similarly, the second shunt split word line 109b and the second split word line 93b are brought into contact in a peripheral circuit region outside the cell array so that the same signal is applied to the two lines.

Next, as shown in FIG. 77, a third oxide film 97c is formed on the entire surface including the first and second shunt split word lines 109a and 109b. Then, as shown in FIG. 78, the first and second split word lines 93a,
The third oxide film 97c and the second ferroelectric layer 9 on another impurity region of the source / drain formed on both sides of 93b.
9b, the first ferroelectric layer 99a, the planarizing insulating layer 98, the first
The oxide film 97a is selectively removed to form a contact hole 103 for bringing the bit line into contact with the other electrode of the cell transistor. Next, as shown in FIG.
A metal material layer for forming a bit line is formed on the entire surface including the contact hole 103 and selectively patterned to form first and second bit lines 104a and 104b in a direction perpendicular to the first and second split word lines 93a and 93b. I do. The upper capacitor in this embodiment uses the electrode 100a in common, and the shunt split word line 109
a and b are used as the other electrodes. And the upper and lower capacitors span the A block and the B block,
It is formed in the direction of the word line.

In the SWL ferroelectric memory device of the present invention, the cross-sectional structure is simplified by using the gate electrode of the transistor as one electrode of the ferroelectric capacitor when designing the layout, and one SWL unit cell is formed. A transistor and a ferroelectric capacitor are formed in the same block or another block in any two blocks of the active region according to chip characteristics, thereby simplifying a layout structure.

[0046]

The SWL ferroelectric memory device according to the present invention has the following effects. According to the first, seventh and eleventh aspects of the present invention, since the cell plate line is not formed separately from the word line, the cell plate line is formed only of the word line necessary for forming the transistor. There is an effect that a simplified layout structure of the device can be provided. Further, since the gate electrode of the transistor is used as one electrode of the ferroelectric capacitor when designing the layout, there is an effect of simplifying the sectional structure. According to the second and third aspects of the present invention, since two transistors and two ferroelectric capacitors forming a pair of cells are configured in units of two blocks, the layout structure can be simplified. is there.
According to the fourth, fifth, ninth, and twelfth aspects of the present invention, after the split word line is formed, the space between the word lines is buried and etched back to expose the first electrode of the capacitor. Since the dielectric and the second electrode are formed thereon, there is an effect that the ferroelectric capacitor can be easily formed. Further, since the SWL ferroelectric memory device can be manufactured without forming the cell plate line, the manufacturing method is simplified. Further, according to the method of the present invention, since the first electrode of the ferroelectric capacitor is heat-treated, the second electrode of the capacitor is connected to the source of the transistor. This has the effect of improving the characteristics. According to the eighth aspect, there is an effect that the capacitor electrode is configured in a planar shape to ensure the easiness of the process. According to the sixth and tenth aspects of the present invention, since no cell plate line is formed, there is an effect of enabling a simplified layout design of the SWL ferroelectric memory device.

[Brief description of the drawings]

FIG. 1 is a characteristic diagram showing a hysteresis loop of a general ferroelectric substance.

FIG. 2 is a configuration diagram of a unit cell of a conventional ferroelectric memory.

FIG. 3 is a configuration diagram of a cell array of a conventional ferroelectric memory.

FIG. 4 is an operation waveform diagram of a conventional ferroelectric memory.

FIG. 5 is a configuration diagram of a cell of the ferroelectric memory according to the present invention.

FIG. 6 is a configuration diagram of a cell array of the ferroelectric memory according to the present invention.

FIG. 7 is an operation waveform diagram of the ferroelectric memory according to the present invention.

FIG. 8 is a configuration diagram showing block divisions at the time of layout design according to the first embodiment of the present invention.

FIG. 9

FIG. 24 is a layout configuration and a process sectional view of the ferroelectric memory according to the first embodiment of the present invention.

FIG. 25

FIG. 41 is a layout configuration and a process cross-sectional view of the ferroelectric memory according to the second embodiment of the present invention.

FIG. 42 is a configuration diagram showing block divisions at the time of layout design according to the third embodiment of the present invention.

FIG. 43

FIG. 51 is a layout configuration and a process cross-sectional view of the ferroelectric memory according to the third embodiment of the present invention.

FIG.

FIG. 60 is another layout configuration and a process sectional view of the ferroelectric memory according to the fourth embodiment of the present invention;

FIG. 61 is a configuration diagram showing block divisions at the time of layout design according to a fifth embodiment of the present invention.

FIG. 62

FIG. 79 is a layout configuration and a process cross-sectional view of the ferroelectric memory according to the fifth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 90 semiconductor substrate 91 element isolation layer 92 gate oxide film 93a, 93b first and second split word lines 94 barrier conductive material layer 95 first electrode layer of capacitor 96 source / drain regions 97a, 97b, 97c first, second, third oxidation Film 98 Flattening insulating layer 99 Ferroelectric layer 100 Second electrode layer of capacitor 101, 103 Contact hole 104a, 104b First and second bit line

Claims (12)

[Claims] A first active region having portions arranged in parallel and separated from each other and formed on a semiconductor substrate, the first and second active regions being formed in parallel across a first direction orthogonal to the parallel direction; , 2 split word lines; source / drain formed on both sides of a first split word line of the first active region; and both sides of a second split word line of the second active region, respectively, A barrier conductive material layer, a first electrode layer and a ferroelectric layer of a capacitor stacked on each of the lines, and one of a source / drain of the second active region; A second electrode layer of the first capacitor is connected to one of a source and a drain of the first active region, and is formed on the second split word line. A first electrode connected to the second electrode layer of the second capacitor and the other of the source / drain of the first active region, the first bit being formed to intersect the first and second split word lines vertically in the second direction. A first line connected to the other of the source and the drain of the second active region;
A nonvolatile ferroelectric memory device comprising: two split word lines; and a second bit line formed to intersect perpendicularly in a second direction. 2. A semiconductor substrate in which rectangular blocks having a major axis and a minor axis are repeatedly arranged, and four blocks adjacent at a certain point are all A-block, B-block,
A block and a B block are defined, and these four blocks are repeatedly arranged. The first active region is separated from the A block and another A block diagonally adjacent to the A block, and the second active region is formed. A B block horizontally adjacent to the A block and another B block diagonally adjacent to the B block and vertically adjacent to the A block.
2. The nonvolatile ferroelectric memory device according to claim 1, wherein the nonvolatile ferroelectric memory device is formed over blocks. 3. The non-volatile memory according to claim 1, wherein the first direction is a direction perpendicular to the long axis direction of the A and B blocks, and the second direction is the long axis direction of the A and B blocks. Ferroelectric memory device. 4. The first and second elements isolated by an element isolation layer.
Forming a gate oxide film, a polysilicon layer for forming a gate, a barrier conductive material layer and a first electrode layer of a capacitor sequentially on the entire surface of the semiconductor substrate having an active region; and selectively etching the stacked layers. Forming first and second split word lines crossing the first and second active regions by using the patterned first and second split word lines as a mask. Forming a first oxide film on the entire surface and then depositing a planarizing insulating layer; and improving the viscosity of the planarizing insulating layer by a heat treatment step.
Forming a ferroelectric layer and a second electrode layer on the entire surface after exposing the first electrode layer of the capacitor by removing the planarization insulating layer by a predetermined thickness in an etch-back process; Selectively patterning the two-electrode layer and depositing a second oxide film on the entire surface; forming a contact hole such that the drain regions of the first and second active regions are exposed; A contact plug layer contacting the drain region of the second active region and the second electrode layer of the capacitor on the second split word line; and the drain region of the second active region and the second electrode layer of the capacitor on the first split word line. Forming a third contact plug layer on the entire surface including the contact plug layer so that the source regions of the first and second active regions are exposed. Forming a contact hole and forming first and second bit lines in contact with a source region through the contact hole in a direction perpendicular to the first and second split word lines. Device manufacturing method. 5. The first and second elements isolated by an element isolation layer.
Forming a gate oxide film, a gate forming polysilicon layer, a barrier conductive material layer, and a first electrode layer of a capacitor sequentially on the entire surface of the semiconductor substrate having an active region; and selectively etching the stacked layers. Forming first and second split word lines crossing the first and second active regions; and forming source / drain regions in the exposed first and second active regions using the patterned first and second split word lines as a mask. Forming and depositing a first oxide film and a photoresist layer on the entire surface; removing a predetermined thickness of the photoresist layer filled between the first and second split word lines by an etch-back process; Removing the film to expose the first electrode layer of the capacitor and removing any remaining photoresist; and covering the entire surface including the exposed first electrode layer of the capacitor. Forming a ferroelectric layer and a second electrode layer of the capacitor, selectively patterning the second electrode layer of the capacitor, and then forming a second oxide film on the entire surface; A contact hole is formed to expose the region, a connection conductive layer connecting the drain region of the first active region to the second electrode layer of the capacitor on the second split word line through the contact hole, and a drain of the second active region. Forming a connection conductive layer connected to the region and the second electrode layer of the capacitor on the first split word line, and forming a third oxide film on the entire surface including the connection conductive layer between the first and second split word lines. After being buried, a contact hole is formed so that the source regions of the first and second active regions are exposed. Line 1
Forming the semiconductor memory device in a direction perpendicular to the two split word lines. 6. The first and second split word lines (SWL1, SWL2) configured in parallel with each other, and the first and second split word lines (SWL1, SWL).
L2), the first and second shunt split word lines (SSWL1, SSWL2), the first transistor (T1) having a gate connected to the first split word line (SWL1), and the second split word line (SSL1). SWL2), one gate of which is connected to the second transistor T2, and one electrode of the first transistor T1 which is connected to the first and second split word lines SWL1, SWL2.
A bit line (Bit_n) vertically connected to one of the electrodes of the second transistor (T2) is connected to be parallel to the bit line (Bit_n) and perpendicular to the first and second split word lines (SWL1, SWL2). (Bit_n + 1)
And one electrode is connected to the other electrode of the first transistor (T1), and the second shunt split word line (SS
WL2) has its other electrode connected to the first ferroelectric capacitor (FC1), and the other electrode of the second transistor (T2) has one electrode connected to the first shunt split word line (SS).
A nonvolatile ferroelectric memory device, comprising: a second ferroelectric capacitor (FC2) having the other electrode connected to WL1). 7. A first active region formed parallel to a first and second active region having portions arranged in parallel and separated from each other and formed on a semiconductor substrate, in a first direction orthogonal to the parallel direction. , 2 split word lines, source / drain formed on both sides of the first split word line of the first active region, and both sides of the second split word line of the second active region, respectively, A first bit line connected to any one of the source / drain of the first active region and intersecting the first and second split word lines in the second direction, and a source / drain of the second active region A second bit line connected to any one of the regions and intersecting the first and second split word lines in the second direction; and a source / drain of the first active region. And a first electrode layer of a capacitor formed in a cylinder shape having a bottom surface and a rectangular column above the first and second split word lines including the first active region and connected to another region of the first active region. And a portion of the first active region connected to another source / drain of the second active region and including the second active region.
A first electrode layer of a capacitor formed in the form of a cylinder having a bottom surface and a prism above the two split word lines, and a bottom surface and an inner side surface of the first electrode layer of both capacitors; A ferroelectric layer; a second electrode layer of the capacitor formed by being embedded inside the first electrode layers of the both capacitors; and a capacitor in the second active region formed above the first split word line. Of the first electrode connected to the second electrode layer of
A non-volatile ferroelectric, comprising: a shunt split word line; and a second shunt split word line formed above the second split word line and connected to the second electrode layer of the capacitor in the first active region. Body memory device. 8. The first capacitor of each capacitor connected to one of the source / drain of the first and second active regions.
8. The non-volatile ferroelectric memory device according to claim 7, wherein the electrode has a planar shape without a rectangular column portion. 9. The first and second elements isolated by an element isolation layer.
Forming a gate oxide film and a gate forming polysilicon layer over the entire surface of the semiconductor substrate having the active region, and selectively etching to form first and second split word lines crossing the first and second active regions; Using the patterned first and second split word lines as a mask, forming a source / drain region in the exposed active region and forming a first interlayer insulating layer over the entire surface; Forming a bit line contact hole so that the region is exposed, and forming first and second bit lines in contact with the source region through the bit line contact hole in a direction perpendicular to the first and second split word lines; Forming a second interlayer insulating layer, forming a contact hole such that each drain region of the first and second active regions is exposed, Forming a first electrode layer of the capacitor so as to be connected to each drain; forming a ferroelectric layer on the entire surface on which the first electrode layer of both capacitors is formed; Forming a second electrode layer of the capacitor so as to bury the second electrode layer; and forming a third interlayer insulating layer on the entire surface including the second electrode layers of the two capacitors, so that a part of the second electrode layer of the capacitor is exposed. Forming a contact hole, forming a metal layer on the entire surface, and selectively etching to form first and second shunt split word lines. Manufacturing method. 10. The first and second split word lines (SWL1, SWL2) configured in parallel with each other and the first and second split word lines (SWL1, SWL).
L2), first and second shunt split word lines SSWL1 and SSWL2, a first transistor T1 having a gate connected to the first split word line SWL1, and a second split word line SSW. SWL2), one gate of which is connected to the second transistor T2, and one electrode of the first transistor T1 which is connected to the first and second split word lines SWL1, SWL2.
A bit line (Bit_n) vertically connected to one of the electrodes of the second transistor (T2) is connected to be parallel to the bit line (Bit_n) and perpendicular to the first and second split word lines (SWL1, SWL2). (Bit_n + 1)
A lower first ferroelectric capacitor (FC1-1) having one electrode connected to the other electrode of the first transistor (T1) and the other electrode connected to the second split word line (SWL1); One electrode is connected to the other electrode of the first transistor (T1), and a second shunt split word line (SS) is connected.
WL2) is connected to the other electrode of the upper first ferroelectric capacitor (FC1-2), and the other electrode of the second transistor (T2) is connected to the other electrode of the second split word line (SWL2). Connected to the lower second ferroelectric capacitor (FC2-1)
And one electrode is connected to the other electrode of the second transistor (T2), and the first shunt split word line (SS
A nonvolatile ferroelectric memory device comprising an upper second shared transfer capacitor (FC2-2) connected to the other electrode of the nonvolatile ferroelectric memory (WL1). 11. A first active region formed in parallel with a first and second active region having portions arranged in parallel and separated from each other and formed on a semiconductor substrate, in a first direction orthogonal to the parallel direction. , 2 split word lines; source / drain formed on both sides of a first split word line of the first active region; and both sides of a second split word line of the second active region, respectively, A first conductive layer connected to one of a barrier conductive material layer, a first electrode layer and a first ferroelectric layer of the capacitor, and a source / drain of the second active region; A second electrode layer of the first capacitor to be formed and one of a source and a drain of the first active region are connected and formed on the second split word line. Of the second capacitor
An electrode layer; a second ferroelectric layer formed on the second electrode layer of each of the capacitors; and a second ferroelectric layer formed on the first split word line and connected to the second electrode layer of the first capacitor. A second shunt split word line formed above the first shunt split word line and the second split word line and connected to the second electrode layer of the second capacitor; insulated from the peripheral layer; A first bit line connected to one of the source / drain regions and intersecting the first and second split word lines in the second direction, and one of the source / drain regions of the second active region. A second bit line connected to the first region and the second bit line formed to intersect the first and second split word lines in the second direction. Conductor memory device. 12. The first and first elements isolated by an element isolation layer.
(2) A gate oxide film, a polysilicon layer for gate formation, a barrier conductive material layer,
Sequentially forming a first electrode layer of the capacitor; selectively etching the stacked layers to form first and second split word lines crossing the first and second active regions; Using the first and second split word lines as a mask, forming source / drain regions in the exposed first and second active regions, depositing a first oxide film and a planarizing insulating layer over the entire surface, and planarizing by a heat treatment process After improving the viscosity of the insulating layer, the planarizing insulating layer is removed to a certain thickness by an etch-back process to expose the first electrode layer of the capacitor, and then the first ferroelectric layer and the second Forming an electrode layer, selectively patterning a second electrode layer of the capacitor, and depositing a second oxide film on the entire surface, and exposing the drain regions of the first and second active regions. Ko Forming a contact hole, through which a drain region of the first active region and a contact plug layer contacting the second electrode layer of the capacitor on the second split word line; and a drain region of the second active region and the first split word line Forming a contact plug layer in contact with the second electrode layer of the capacitor on the line; forming a second ferroelectric layer on the entire surface including the contact plug layer; forming a second ferroelectric layer above the first split word line A first shunt split word line connected to the second electrode layer of the capacitor in the second active region;
Forming a second shunt split word line formed above the split word line and connected to the second electrode layer of the capacitor in the first active region; depositing a third oxide film to form the first and second active regions; Forming a contact hole such that the source region is exposed, and forming first and second bit lines in contact with the source region through the contact hole in a direction perpendicular to the first and second split word lines. A method for manufacturing a nonvolatile ferroelectric memory device, comprising: