JPH07312392A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To improve integration by reducing the memory cell area of a semiconductor storage (DRAM). CONSTITUTION:A memory cell consists of a first memory cell consisting of an n-ch transistor 17 and a lower capacitor 19 and a second memory cell consisting of a p-ch transistor 18 and an upper capacitor 20 and the first memory cell and the second memory cell are connected to common word wire 2 and bit wire 8. When the potential of the word wire 2 is equal to or more than a power supply voltage, read/write are performed for the capacitor 19. When the potential is equal to or less than a grounding voltage, read/write are performed for the capacitor 20. The memory cell area is reduced since the word wire 2 and the bit wire 8 are common.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a DRAM.

[0002]

FIG. 22 shows a conventional semiconductor memory device (DRA).
The structure of M) is shown. In FIG. 1A, 52 is a row address buffer for buffering an input row address signal, 53a is a row decoder for decoding a row address signal, 54 is a column address buffer for buffering an input column address signal, Reference numeral 55 is a column decoder for decoding a column address signal, 56a is a sense amplifier for writing / reading to / from a memory cell, and 57 is a memory array including a large number of memory cells. In the figure, “A” means one selected memory cell, and 2 and 8 in the memory array 57 are word lines and bit lines for selecting the memory cell A. The DRAM 51 includes the row address buffer 52, the row decoder 53a, the column address buffer 54, the column decoder 55, and the sense amplifier 56 described above.
a, a memory array 57.

FIG. 22B shows the structure of one memory cell. In FIG. 2B, 2 is a row decoder 53.
A word line selected by a to turn on / off the transistor of the memory cell on the specific row, 8 is a bit line connecting the transistor of the memory cell and the sense amplifier 56a, 17
Reference numerals 19a and 19a are n-ch transistors and capacitors which form a memory cell.

FIG. 23 is a diagram showing the structure of a memory cell of a conventional DRAM 51. In FIG. 23, 1 is a silicon substrate in which p-type impurities are diffused, and 2 is a normal impurity for imparting conductivity. Is a word line made of polycrystal silicon in which 4 is diffused, 4 is a storage node of a capacitor 19a made of polycrystal silicon in which ordinary impurities are also diffused, 5 is a dielectric film of the capacitor 19a, and 6 is a normal impurity. A cell plate of a capacitor 19a made of polycrystalline silicon, 8 is a bit line made of tungsten (W) polycide, 10 is an element isolation oxide film, 11
Is an n-type diffusion layer for substrate contact of the bit line 8 in which n-type impurities are diffused, 12 is an n-type diffusion layer for substrate contact of the storage node 4 in which n-type impurities are diffused, 2
Reference numerals 1 and 22 are oxide films for insulation. The part of the word line 2 between the n-type diffusion layers 11 and 12 constitutes a gate electrode, and the n-type diffusion layers 11 and 12 are the transistors 17.
The output electrode of.

Next, the operation will be described. When the row address input and the column address input are given, the row decoder 5
3a and the column decoder 55 decode these address signals, and select one memory cell A from the many memory cells forming the memory array 57. That is, the word line 2 is selected by the output of the row decoder 53a, and the corresponding transistor 17 is turned on. During the read operation, charges corresponding to the stored data accumulated in the capacitor 19a appear on the bit line 8 through the transistor 17. The sense amplifier 56a senses the change in the potential of the bit line 8 associated with the movement of the electric charge to detect data "0"
Distinguish "1". Then, based on the designation of the column decoder 55, the sense amplifier 56a selects predetermined data from the data of one column and outputs it to the outside through an input / output circuit (not shown).

On the other hand, in the write operation, the sense amplifier 56a selects one bit line 8 based on the designation of the column decoder 55 and corresponds to the data to be stored inputted from the input / output circuit (not shown). Electric charges are stored in the capacitor 19a via the transistor 17.

Here, a capacitor 19 for storing data
23a is composed of the storage node 4, the capacitor dielectric film 5 and the cell plate 6 shown in FIG.

[0008]

The conventional semiconductor memory device has the following problems. First, since the structure of the memory cell including the capacitor 19a and the transistor 17 of the semiconductor memory device (DRAM) is two-dimensional, it is necessary to secure the area of the capacitor 19a when performing fine processing to improve the degree of integration. It became difficult, and trying to secure the required area was an obstacle to improving the degree of integration. Also,
Secondly, as the number of memory cells increases, the number of word lines 2 and bit lines 8 connected to the memory cells also increases. Therefore, securing these areas becomes an obstacle, making it difficult to improve the degree of integration.

The present invention has been made to solve the above problems, and it is possible to improve the degree of integration of memory cells and obtain a semiconductor memory device capable of suppressing an increase in word lines and bit lines. To aim.

[0010]

According to another aspect of the present invention, there is provided a semiconductor memory device having a first conductivity type transistor having an output electrode connected to a bit line and a control electrode connected to a word line. A first capacitor connected to another output electrode of the transistor, a second conductivity type transistor having an output electrode connected to the bit line and a control electrode connected to the word line, and the second conductivity type transistor. A memory array including a plurality of memory cells each including a second capacitor connected to another output electrode of the transistor, and a first voltage applied to the word line when reading data from or writing data to the first capacitor. And applies a second voltage to the word line when reading data from the second capacitor or writing data. A decoder, and outputs a read signal to read the data stored in the memory cell based on the voltage change of the bit line, a sense amplifier for outputting a write signal to the memory cell to the bit line,
And a column decoder for controlling the sense amplifier.

According to another aspect of the semiconductor memory device of the present invention, at least one of the first conductivity type transistor and the second conductivity type transistor is formed of a thin film transistor.

According to another aspect of the semiconductor memory device of the present invention, the first capacitor and the second capacitor are formed by a groove-type capacitor formed by stacking them on top of each other.

According to a fourth aspect of the semiconductor memory device of the present invention, the first capacitor and the second capacitor are formed by a laminated capacitor.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, which comprises a step of forming a storage node by forming a storage node on a cell plate of a first capacitor, and controlling a transistor of a first conductivity type. A step of depositing an oxide film on the electrode in a stacked manner, further depositing a semiconductor thin film, and diffusing impurities on the semiconductor thin film to form a transistor of the second conductivity type; 1
A step of forming a contact hole so that the output electrode of the conductive type transistor and the output electrode of the second conductive type transistor are exposed, and then depositing a conductive material to form a bit line.

According to a sixth aspect of the method of manufacturing a semiconductor memory device of the present invention, a step of forming a first conductivity type transistor and a second conductivity type transistor, and a first capacitor overlaid on the first conductivity type transistor. Forming a storage node of the second capacitor, a step of forming a storage node of the second capacitor overlying the second conductivity type transistor, a storage node of the first capacitor and a storage node of the second capacitor. The method further comprises a step of forming a dielectric film by stacking, and then a step of depositing a conductive material to form a cell plate of the first capacitor and the second capacitor.

[0016]

According to the first aspect of the present invention, there are provided a first conductivity type transistor having an output electrode connected to a bit line and a control electrode connected to a word line, and another output electrode of the first conductivity type transistor. A connected first capacitor,
The output electrode is connected to the bit line and the control electrode is connected to the word line. The transistor is of a second conductivity type and the second capacitor is connected to another output electrode of the transistor of the second conductivity type. A memory array having a plurality of memory cells stores data, and when a row decoder reads data from the first capacitor or writes data, a first voltage is applied to the word line, and the second capacitor is applied. A second voltage is applied to the word line when reading data from or writing data to the word line, and the sense amplifier reads the data stored in the memory cell based on the voltage change of the bit line and outputs a read signal. At the same time, the write signal to the memory cell is output to the bit line, and the column decoder controls the sense amplifier. That.

According to the second aspect of the present invention, by using the thin film transistor, the first conductivity type transistor and the second conductivity type transistor are stacked.

According to the third aspect of the present invention, by using the groove type capacitor, the first capacitor and the second capacitor are laminated.

According to the fourth aspect of the present invention, the structure of the first capacitor and the second capacitor is simplified by using the multilayer capacitor.

According to another aspect of the present invention, a storage node is formed on the cell plate of the first capacitor so as to form a second capacitor, and an oxide film is formed on the control electrode of the transistor of the first conductivity type. And a semiconductor thin film are further deposited, impurities are diffused on the semiconductor thin film to form a second conductivity type transistor, and an output electrode of the first conductivity type transistor and After forming a contact hole so that the output electrode of the second conductivity type transistor is exposed, a conductive material is deposited to form a bit line.

In a sixth aspect of the present invention, a first conductivity type transistor and a second conductivity type transistor are formed, and a storage node of the first capacitor is formed so as to overlap with the first conductivity type transistor, A storage node of the second capacitor is formed on the transistor of the second conductivity type, and a dielectric film is formed on the storage node of the first capacitor and the storage node of the second capacitor. A conductive material is deposited to form the cell plates of the first capacitor and the second capacitor.

[0022]

【Example】

Example 1. FIG. 1 shows the configuration of a semiconductor memory device (DRAM) according to an embodiment of the present invention. In FIG. 3A, reference numeral 52 is a row address buffer for buffering an input row address signal, 53 is a row decoder for decoding the row address signal to select a specific row, and 54 is an input column address signal. A column address buffer for buffering, 55 is a column decoder for decoding a column address signal to select a specific column, 56 is a sense amplifier for writing / reading to / from a memory cell, and 57 is a memory array composed of many memory cells. Is. In addition, "A" in the figure
Means one selected memory cell. DRA
The M51 is composed of the above row address buffer 52, row decoder 53, column address buffer 54, column decoder 55, sense amplifier 56, and memory array 57.

Further, FIG. 1B shows the structure of one memory cell 57. In FIG. 2B, 2 is a word line which is selected by the row decoder 53 to turn on / off the transistor of the memory cell, 8 is a bit line which connects the transistor of the memory cell and the sense amplifier 56a,
Reference numerals 17 and 19 are driven by the word line 2 and outputs are connected to the bit line 8, and n-ch transistors and lower capacitors constituting the first memory cell, and 18 and 20 are driven by the word line 2. The output is a p-ch transistor which is a thin film transistor (TFT) connected to the bit line 8 and constitutes a second memory cell, and an upper capacitor.

The memory cell shown in FIG. 1B is different from the conventional memory cell in that it is composed of a combination of two transistors 17 and 18 and two capacitors 19 and 20.
Each of the first memory cell and the second memory cell made of these is connected to one word line 2 and one bit line 8. That is, unlike the conventional case, the memory cell A stores 2-bit data. Then, since reading / writing of 2-bit data is performed by one word line 2 and one bit line 8, the row decoder 5
3 and the sense amplifier 56 operate differently from the conventional one as described later.

Further, FIG. 2 shows the memory array 5 shown in FIG.
7 is a diagram showing the structure of a memory cell that is a part of FIG.
7 and a word line for turning on / off the p-ch transistor (TFT) 18, 3 is amorphous silicon in which n-type impurities are diffused, and 4 is a lower capacitor 19 made of a diffusion layer in which n-type impurities are diffused. Storage node, 5a
Is a dielectric film 5 which insulates the storage node 4 from the cell plate 6 made of polycrystalline silicon in which impurities for conductivity are diffused and which forms the lower capacitor 19.
Reference numeral b denotes a dielectric film that insulates the storage node 7 and the cell plate 6 of the upper capacitor 20 made of polycrystalline silicon in which p-type impurities are diffused and forms the upper capacitor 20. Note that one end of the storage node 4 has an n-ch
It functions as one output electrode of the transistor, and one end of the storage node 7 functions as one output electrode of the p-ch transistor.

Reference numeral 8 is a bit line made of tungsten (W) silicide, 10 is an element isolation oxide film, 11 is an n-type diffusion layer for substrate contact of the bit line 8 in which n-type impurities are diffused, and 13 is amorphous silicon 3. Is a p-type diffusion layer formed on both sides of the p-ch transistor (TF) composed of the amorphous silicon 3 and the p-type diffusion layer 13.
T) and 22 are oxide films for interlayer insulation. Note that p
The word line 2 between the type diffusion layers 13 and between the storage node 4 and the n-type diffusion layer 11 includes an n-ch transistor 17
And functions as a gate electrode of the p-ch transistor 18. The lower capacitor 19 and the upper capacitor 20 shown in FIG. 2 are so-called groove capacitors.

Next, the operation will be described. The initial voltage of the word line 2 in the circuit is half the power supply voltage because both the transistors 17 and 18 are turned off. That is, the initial voltage means a voltage when the memory cell is not accessed.

First, the write operation will be described. When writing “1” to the lower capacitor 19, the row decoder 53 causes the word line 2 to have a voltage higher than the power supply voltage, for example,
Applying V _CC + V _TH turns on the n-ch transistor 17. At this time, the p-ch transistor (TFT) 18
Is off. Then, the sense amplifier 56 discharges the electric charge of the lower capacitor 19 by setting the potential of the bit line 8 to 0V. When writing “0”, the sense amplifier 56 stores the electric charge in the lower capacitor 19 by setting the potential of the bit line 8 to the power supply voltage V _CC .

On the other hand, when writing "1" to the upper capacitor 20, the row decoder 53 applies a voltage equal to or lower than OV to the word line 2, for example, 0 V (ground potential) -V _TH , and p.
The -ch transistor (TFT) 18 is turned on. At this time, the n-ch transistor 17 is off. Then, the sense amplifier 56 discharges the electric charge of the lower capacitor 19 by setting the potential of the bit line 8 to 0V.
When writing “0”, the sense amplifier 56 stores the electric charge in the lower capacitor 19 by setting the potential of the bit line 8 to the power supply voltage.

Next, when reading the data of the lower capacitor 19, the row decoder 53 applies a voltage higher than the power supply voltage to the word line 2 and the n-ch transistor 17 is applied.
Turn on. At this time, the p-ch transistor (TF
T) 18 is off. Then, the sense amplifier 56
At this time, the change in the potential of the bit line 8 due to the charge transfer between the bit line 8 and the lower capacitor 19 is sensed to read the data.

On the other hand, when the data of the lower capacitor 20 is read out, the row decoder 53 outputs O to the word line 2.
Applying a voltage of V or less, p-ch transistor (TF
T) Turn on 18. At this time, the n-ch transistor 17 is off. Then, the sense amplifier 56 senses a change in the potential of the bit line 8 due to the charge transfer between the bit line 8 and the lower capacitor 19 at this time, and reads the data.

In this way, either the n-ch transistor 17 or the p-ch transistor 18 is selected depending on whether a voltage higher than the power supply voltage or a voltage lower than 0 V is applied to one word line 2. The two capacitors 19 and 20 can be independently written and read with data.
Therefore, when compared with a memory array having the same number of memory cells, the number of word lines required is half that of a conventional semiconductor memory device, and the area for them is small, so that the degree of integration is improved.

Further, in the first embodiment, since the TFT is used for the p-ch transistor 18 as shown in FIG. 2, the n-ch transistor 17 and the p-ch transistor 18 can be formed in an overlapping manner. Since the gate electrode can be formed by the word line 2, it is not necessary to form the gate electrode in each transistor, so that the area of the word line does not increase and the degree of integration is further improved.

Next, a method of manufacturing the semiconductor memory device according to the first embodiment will be described with reference to FIGS.

First, an element isolation oxide film 10 is formed on the surface of the p-type silicon substrate 1, and then a trench is formed in the silicon substrate 1. A storage layer 4 is formed by forming a diffusion layer in which n-type impurities are diffused in the trench. Next, a dielectric film (not shown) and polycrystalline silicon (not shown) are deposited, and patterned by photolithography and etching techniques to form the dielectric film 5a of the lower capacitor 19.
And the cell plate 6 is formed (FIG. 3).

Next, a dielectric film (not shown) and p (not shown)
Polycrystalline silicon in which the type impurities have been diffused is deposited and patterned by photolithography and etching techniques to form the dielectric film 5b of the upper capacitor 20 and the storage node 7. Further, an interlayer insulating film 14 for insulating between the cell plate 6 and the word lines 2 is formed on the cell plate 6 on the element isolation oxide film 10 by the same method as the element isolation oxide film 10 (FIG. 4).

Next, a gate oxide film and a polycrystalline silicon film (not shown) are deposited and patterned by photolithography and etching techniques to form the word line 2. This word line 2 includes n-ch transistors 17 and p.
Since it serves as a gate electrode for any of the -ch transistors 18, it is formed between the n-type diffusion layer 11 and the n-type diffusion layer 12 and between two p-type diffusion layers 13 formed in a process described later. To be done. Then, the n-type diffusion layers 11 and 12 are formed by the ion implantation technique. The n-type diffusion layer 12 is formed in contact with the storage node 4 and integrated with it. Then, after an oxide film (not shown) is deposited on the entire surface and planarized, anisotropic etching is performed on the entire surface until the word line is exposed. Furthermore, after depositing the gate oxide film 15 for the p-ch transistor (TFT) 18 on the entire surface, patterning is performed using photoengraving and etching techniques to form the output terminal of the p-ch transistor (TFT) 18 and the upper capacitor 20. A contact hole h for electrically contacting the storage node 8 is formed (FIG. 5).

Next, an amorphous silicon layer (not shown) in which n-type impurities are diffused is deposited and patterned by photolithography and etching techniques to form amorphous silicon 3. Then, two p-type diffusion layers 1 serving as a source region and a drain region of the p-ch transistor (TFT) 18 are formed by diffusing p-type impurities into a predetermined portion of the amorphous silicon 3 by an ion implantation technique.
3 is formed. At this time, one of the p-type diffusion layers 13 makes electrical contact with the storage node 7 through the contact hole h provided in the previous step (FIG. 5) (FIG. 6).

Next, after the interlayer insulating film 16 for insulating the word line 2 and the bit line 8 is formed, the bit line 8 and the n
Contact hole 9 for making contact with the mold diffusion layer 11
Are formed using photoengraving and etching techniques. The contact hole 9 is formed in the n-ch transistor 17 through the n
Not only is the type diffusion layer 11 exposed, but the p-type diffusion layer 13 of the p-ch transistor (TFT) 18 is also exposed (FIG. 7). This connects word line 2 to n-c
This is because it is necessary to connect to both the output terminal of the h-transistor 17 and the output terminal of the p-ch transistor 18.

Next, a bit line 8 is formed by depositing tungsten silicide and patterning it. Since the tungsten silicide is also deposited inside the contact hole 9 formed in the previous step, the bit line 8 is n−c
It is connected to the n-type diffusion layer 11 which is the output electrode of the h-transistor 17 and the p-type diffusion layer 13 which is the output electrode of the p-ch transistor 18 (FIG. 8).

As described above, according to the semiconductor memory device and its manufacturing method of the first embodiment, one memory cell is
As shown in FIG. 1B, since it is composed of two sets of transistors and capacitors, it is possible to store 2-bit data, and accordingly, write / read 2-bit data with one word line. You can Therefore, when compared with a memory array having the same storage capacity, half the number of word lines required in the prior art is sufficient and the area for forming the word line is half, so that the degree of integration is improved.

Further, since the two groove type capacitors are formed so as to be vertically stacked, it is possible to form the two capacitors in the area of one capacitor and to form the capacitors even though the memory capacity is doubled. Since the required area is the same as the conventional area, the degree of integration is improved.

Example 2. Although the first embodiment relates to the semiconductor device (DRAM) of the present invention using the groove type capacitor, a laminated type capacitor may be used instead of the groove type capacitor.

The second embodiment will be described below. FIG. 9 is a plan view of a memory cell of a DRAM according to the second embodiment, and FIGS. 10 to 13 are sectional views of the same. Figure 10
9 is a sectional view taken along the line AA ′ in the plan view of FIG. 9, showing an n-ch transistor 17 and a lower capacitor 19;
1 shows a first memory cell consisting of FIG. 11 also shows B
FIG. 7B is a cross-sectional view taken along the line −B ′, showing a second memory cell including the p-ch transistor 18 and the upper capacitor 20. FIG. 12 is a sectional view taken along line CC ′ of FIG.
A connection portion between the ch transistor 17 and the p-ch transistor 18 and the bit line 8 is shown. FIG. 13 is a sectional view taken along the line DD ′ of FIG.
7 and the storage node 4 of the lower capacitor 19, and the p-ch transistor 18 and the upper capacitor 2
0 shows the connection with the storage node 7.

In FIGS. 9 to 13, 41 to 43 are oxide films. The same reference numerals as those in FIG. 1 indicate the same or corresponding portions. The semiconductor memory device of FIGS. 9 to 13 uses a so-called laminated capacitor and also uses a buried bit line structure. Since the operation of the DRAM of the second embodiment having such a configuration is the same as that of the first embodiment, its explanation is omitted.

Next, a method of manufacturing the semiconductor memory device according to the second embodiment will be described with reference to FIGS. 14
18 to 18 are views showing a plan view and a sectional view of the semiconductor memory device for each step of the manufacturing method according to the second embodiment. 19 to 21 are sectional views showing steps after the step shown in FIG.

First, the element isolation oxide film 10 is formed on the surface of the silicon substrate 1. Then, after depositing a gate oxide film (not shown), a polysilicon film for forming the word line 2 is deposited, and the word line 2 is formed by patterning into a predetermined pattern by using ordinary photoengraving and etching techniques. To do. After that, the n-type impurity diffusion layers 11 and 12 are formed by using the ion implantation technique. Next, after depositing an oxide film 41 on the entire surface, it is planarized, and anisotropic etching is further performed on the entire surface until the word line 2 is exposed (FIG. 14). Note that, for convenience of description, the configuration shown in the plan view is represented by a solid line regardless of their vertical relationship (the same applies hereinafter). Further, in the plan view, the portion where the n-ch transistor 17 is formed is shown by a convex figure.

Next, after depositing the gate oxide film 15 for the TFT on the entire surface, amorphous silicon in which n-type impurities serving as a substrate for the TFT are diffused is deposited. Then, the amorphous silicon 3 for the p-ch transistor 18 is formed by patterning into a predetermined shape by using ordinary photoengraving and etching techniques. Next, the p-type diffusion layer 13 in which the p-type impurities to be the source region and the drain region of the p-ch transistor 18 are diffused is formed by the ion implantation technique (FIG. 15).

Next, an oxide film 42 is formed as an interlayer insulating film for insulating the p-ch transistor 18 and the bit line 8 from each other. Then, in order to connect the drain 11 of the n-ch transistor 17 and the drain 13 of the p-ch transistor 18 to the bit line 8, a normal photoengraving process,
Using the etching technique, the p-type diffusion layer 13 of the amorphous silicon 3 on which the TFT is formed and the n of the silicon substrate 1 are formed.
A contact hole 9a is formed so as to be in contact with the mold diffusion layer 11. Next, after depositing a tungsten silicide layer (not shown) on the entire surface including the inside of the contact hole 9a, predetermined patterning is performed to form the bit line 8 (FIG. 16).

Next, the bit line 8 and the upper capacitor 19,
After depositing an oxide film 43 as an interlayer insulating film for insulating the lower capacitor 20, n-c of the silicon substrate 1 is deposited.
In order to connect the n-type diffusion layer 12 of the h-transistor 17 and the storage node 4 of the lower capacitor 19, a contact hole 9b is formed by using ordinary photoengraving and etching techniques. Then, after depositing polycrystalline silicon in which n-type impurities have been diffused, the storage node 4 of the lower capacitor 19 is formed by removing unnecessary portions by using ordinary photolithography and etching techniques (FIG. 17). ).

Next, the nitride film 22 and the oxide film 2 overlaid thereon are formed.
3 is deposited to form p- on the amorphous silicon 3.
The p-type diffusion layer 13 which is the output electrode of the ch transistor 18
Then, a contact hole 9c with the storage node 7 of the upper capacitor 20 which is accessed by the TFT transistor 18 is formed by using a normal photolithography and etching technique. Then, p-ch is formed by depositing polycrystalline silicon in which p-type impurities are diffused and forming it into a predetermined pattern by using ordinary photoengraving and etching techniques.
Form the storage node 7 of the upper capacitor 20 which is accessed by the transistor 20 (FIG. 18).

Next, the oxide film 23 is removed by wet etching (FIG. 19). Next, the nitride film 22 is removed by wet etching (FIG. 20). Storage node 4
In the state shown in FIG. 20 in which the electrodes 7 and 7 are exposed, the dielectric film 5 of the capacitor is formed next, and the cell plate 6 is formed by further stacking polycrystalline silicon (FIG. 2).
2).

Through the above steps, it is possible to manufacture a DRAM including a laminated type capacitor. According to the second embodiment, the degree of integration is improved as in the case of using the groove type capacitor, and the structure is simpler than that in the case of using the groove type capacitor.

[0054]

As described above, according to the first aspect of the invention, the first conductivity type transistor having the output electrode connected to the bit line and the control electrode connected to the word line, the first conductivity type is provided. A second capacitor whose output electrode is connected to the bit line and whose control electrode is connected to the word line.
A memory array including a plurality of memory cells each including a conductive type transistor and a second capacitor connected to another output electrode of the second conductive type transistor; and when reading data from the first capacitor or when data is read from the first capacitor. When writing, apply a first voltage to the word line,
A row decoder that applies a second voltage to the word line when reading data from or writing data to the second capacitor, and data stored in a memory cell based on a voltage change of the bit line Since a read signal is output and a sense amplifier that outputs a write signal to the memory cell is output to the bit line and a column decoder that controls the sense amplifier, a word line and a bit for accessing the memory cell are provided. The area of the line can be reduced and the integration degree of the semiconductor memory device can be improved.

According to the invention of claim 2, the first
Since at least one of the conductive type transistor or the second conductive type transistor is formed of a thin film transistor, the area of the transistor of the memory cell can be reduced, and the integration degree of the semiconductor memory device is further improved. Can be made.

Further, according to the inventions of claims 3 and 5, since the first capacitor and the second capacitor are groove type capacitors formed by overlapping each other, the capacitor of the memory cell is The area can be reduced, and the integration degree of the semiconductor memory device can be further improved.

Further, according to the inventions of claims 4 and 6, since the first capacitor and the second capacitor are laminated capacitors, the integration degree of the semiconductor memory device is improved with a simple structure. Can be made.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a structure of a memory cell of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is a sectional view showing a structure of a memory cell of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a sectional view showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a sectional view showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 12 is a sectional view showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 13 is a sectional view showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 14 is a plan view and a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 15 is a plan view and a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

16A and 16B are a plan view and a sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 17 is a plan view and a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 18 is a plan view and a sectional view for explaining a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 19 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 20 is a cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 21 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of a conventional semiconductor memory device.

FIG. 23 is a cross-sectional view of the structure of a memory cell of a conventional semiconductor memory device.

[Explanation of symbols]

1 silicon substrate, 2 word line, 3 amorphous silicon, 4 storage node, 5 dielectric film, 6 cell plate, 7 storage node, 8 bit line, 9
Contact hole, 10 element isolation oxide film, 11, 1
2 n-type diffusion layer, 13 p-type diffusion layer, 14 interlayer insulating film, 15 gate oxide film, 16 interlayer insulating film, 17 n
-Ch transistor, 18 p-ch transistor, 1
9 lower capacitor, 20 upper capacitor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9056-4M H01L 29/78 311 C

Claims (6)

[Claims] 1. A first conductivity type transistor having an output electrode connected to a bit line and a control electrode connected to a word line, and a first conductivity type transistor connected to another output electrode of the first conductivity type transistor. A capacitor, a second conductivity type transistor having an output electrode connected to the bit line and a control electrode connected to the word line, and a second capacitor connected to another output electrode of the second conductivity type transistor. A memory array having a plurality of memory cells each consisting of
A first voltage is applied to the word line when reading data from or writing data to the first capacitor, and a word line is applied to the word line when reading data from the second capacitor or writing data. A row decoder that applies a second voltage, and data that is stored in the memory cell is read out based on the voltage change of the bit line to output a read signal, and a write signal to the memory cell is output to the bit line. A semiconductor memory device comprising a sense amplifier and a column decoder for controlling the sense amplifier. 2. At least one of the first conductivity type transistor and the second conductivity type transistor,
The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises a thin film transistor. 3. The semiconductor memory device according to claim 1, wherein the first capacitor and the second capacitor are groove type capacitors that are formed by being stacked on each other. 4. The semiconductor memory device according to claim 1, wherein the first capacitor and the second capacitor are laminated capacitors. 5. A step of forming a storage node by forming a storage node on the cell plate of the first capacitor to form a second capacitor, and depositing an oxide film on the control electrode of the transistor of the first conductivity type in an overlapping manner. Further, a step of depositing a semiconductor thin film and diffusing impurities on the semiconductor thin film to form a transistor of the second conductivity type; and an output electrode of the transistor of the first conductivity type and the first electrode on the insulating layer formed by overlapping. Two
A method of manufacturing a semiconductor memory device, comprising the steps of forming a contact hole to expose an output electrode of a conductive type transistor, depositing a conductive material, and forming a bit line. 6. A step of forming a transistor of a first conductivity type and a transistor of a second conductivity type; a step of forming a storage node of a first capacitor overlying the transistor of the first conductivity type; Forming a storage node of the second capacitor over the two conductivity type transistor; forming a dielectric film over the storage node of the first capacitor and the storage node of the second capacitor; After that, a step of depositing a conductive material to form the cell plates of the first capacitor and the second capacitor is carried out.