JP2000340760A - Nonvolatile semiconductor memory and drive method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an NAND type nonvolatile semiconductor memory of high integration, high-speed, and low power consumption and moreover having little disturbance. SOLUTION: A memory cell comprises a ferroelectric gate type dual-gate thin-film transistor, wherein a thin transistor is provided on both surfaces of a ferroelectric thin film 1, a plurality of the memory cells are connected in series to constitute a memory block, and a plurality of memory blocks are arranged to form a memory cell array. Related to the ferroelectrics gate type dual-gate thin-film transistor on one surface of the ferroelectric thin film 1, gate electrodes Wu2-Wu5 are provided via a gate insulating film 2, semiconductor thin-film 3, and a gate insulating film 4, and on the other surface, gate electrodes Wd1-Wd5 are provided via a gate insulating film 5, semiconductor thin film 6, and a gate insulating film 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory using a ferroelectric and a method of driving the same.

[0002]

2. Description of the Related Art A ferroelectric memory is a non-volatile memory capable of high-speed rewriting utilizing high-speed polarization reversal of a ferroelectric thin film and its residual polarization. This ferroelectric memory is of a type using a ferroelectric capacitor (FeRAM).
Type) and a type (ferroelectric gate type) in which a ferroelectric is connected to the gate portion of a transistor. Among them, the ferroelectric gate type is excellent in terms of cell area and nondestructive readout. As this ferroelectric gate type nonvolatile memory, MFS (Metal-Ferroelectrics-Semiconductor)
Type, MFIS (Metal-Ferroelectrics-Insulator-Semic
onductor) type and MFMIS (Metal-Ferroelectrics)
-Metal-Insulator-Semiconductor) type is known.

As described above, the ferroelectric gate type nonvolatile memory has the advantage of being excellent in cell area and non-destructive readout.
Since the transistor type is driven by a simple matrix,
When the ferroelectric of the selected memory cell is polarized, there is a problem of disturbance that the ferroelectric of the non-selected memory cell is affected. That is, FIG. 10 shows a part of a memory cell array of a one-transistor ferroelectric gate nonvolatile memory. MC11 ', MC12', MC
21 ′, MC22 ′ are memory cells composed of ferroelectric gate type transistors, B1a ′, B1b ′, B2
a 'and B2b' indicate bit lines, and W1 'and W2' indicate word lines. In this example, since simple matrix writing is performed, -V is applied to the gate of the ferroelectric gate type transistor.
_w / 3 (however, V _w voltage required for polarization inversion of the ferroelectric) disturb voltage is applied to every write to other memory cells. In this case, data can be written at a lower voltage and in a shorter time as compared with a flash memory in which electric charges are injected into a floating gate, but this causes a weakness in disturb. Furthermore, in order to suppress the disturb voltage -V _w / 3, it is necessary to transistors of non-selected memory cell is also made conductive to form a channel. For this reason, the fluctuation width of the threshold voltage due to the ferroelectric material is greatly restricted, and the range of characteristics required for the ferroelectric material is narrow. Further, since wiring connection to the source region and the drain region is required for each transistor of the memory cell, the cell area is increased as compared with the NAND type, and at the same time, fine processing of the ferroelectric is required, and the ferroelectric characteristics are increased. And it becomes difficult to use a ferroelectric material which is difficult to dry-etch such as reactive ion etching (RIE) such as SBT.

The above-mentioned disturb problem can be solved by adding a selection transistor to the memory cell. However, in this case, the cell area becomes large, so that high integration becomes difficult. Newly arise.

On the other hand, a flash memory is known as a nonvolatile memory. In a flash memory, information is stored by injecting and extracting electrons from and to a floating gate. In this flash memory, the injection of electrons requires a larger voltage and takes longer time than the polarization inversion of the ferroelectric, but this reduces the disturb problem. In this flash memory, a NAND type in which a plurality of transistors are arranged in series has been developed as a method in which a cell area is small and high integration is possible.

[0006]

Since the basic structure of a ferroelectric gate type nonvolatile memory is similar to that of a flash memory, the cell area is expected to be small when a NAND type is adopted. As described above, there is a problem of disturbance, and the transistor is turned on / off without inverting the polarization.
Since it is difficult to turn off the gate voltage and the fluctuation direction of the gate voltage and the threshold voltage of the transistor is opposite to that of the flash memory, the NAND type cell arrangement in the ferroelectric gate type nonvolatile memory has been It was difficult.

Japanese Patent Application Laid-Open Nos. 5-136377 and 5-136378 propose NAND-type nonvolatile semiconductor memories. However, these NAND-type nonvolatile semiconductor memories have extremely complicated structures and are difficult to realize. it is conceivable that.

Accordingly, an object of the present invention is to provide a highly integrated
NAN with high speed, low power consumption and little disturbance
An object of the present invention is to provide a nonvolatile semiconductor memory capable of realizing a D-type nonvolatile semiconductor memory and a driving method thereof.

[0009]

In order to achieve the above object, a nonvolatile semiconductor memory according to a first aspect of the present invention comprises a memory cell comprising thin film transistors provided on both sides of a ferroelectric thin film. A plurality of memory cells are connected in series to form a memory block, and a plurality of memory blocks are arranged to form a memory cell array.

In the first aspect of the present invention, typically, a plurality of memory cells are connected in series, and a select transistor is connected to at least one end of the series connection to form a memory block. The number of memory cells that constitute a memory block is basically arbitrary, and the higher the number of memory cells, the higher the integration.However, the path through which current flows through the transistors of the memory cells becomes longer, and a voltage drop occurs. The optimal number is selected according to the use of the nonvolatile semiconductor memory. Also, one end of the memory block
Typically, it is connected to a bit line via a selection transistor.

In the first aspect of the present invention, typically, a first gate insulating film is provided on one surface of the ferroelectric thin film.
A first gate electrode is provided via a first semiconductor thin film and a second gate insulating film, and a first semiconductor film forming a source region or a drain region in the first semiconductor thin film on both sides of the first gate electrode is provided. And a second gate electrode is provided on the other surface of the ferroelectric thin film via a third gate insulating film, a second semiconductor thin film and a fourth gate insulating film. A second semiconductor region forming a source region or a drain region is provided in the second semiconductor thin film on both sides of the second gate electrode, and the first semiconductor region provided in the first semiconductor thin film is provided. A first gate electrode and a first ferroelectric thin film in a portion facing the first gate electrode, the first ferroelectric thin film constituting a memory cell;
Of the ferroelectric gate type dual-gate thin film transistor, and the second semiconductor region provided in the second semiconductor thin film, the second gate electrode, and the portion of the ferroelectric material facing the second gate electrode A second ferroelectric gate type dual gate thin film transistor that forms a memory cell by the thin film is formed. Here, the ferroelectric thin film is provided in a continuous film shape over at least a plurality of memory cells, typically the entire memory cell array.

From the viewpoint of improving the degree of integration, the nonvolatile semiconductor memory according to the first aspect of the present invention as described above is stacked by sharing the first gate electrode or the second gate electrode. Accordingly, a stacked ultra-high integration nonvolatile semiconductor memory can be configured.

According to a second aspect of the present invention, a first gate insulating film, a first semiconductor thin film and a second gate insulating film are provided on one surface of a ferroelectric thin film via a first gate insulating film. An electrode is provided, a first semiconductor thin film constituting a source region or a drain region is provided in the first semiconductor thin film on both sides of the first gate electrode, and the first semiconductor thin film is formed on the other surface of the ferroelectric thin film. Is provided with a third gate insulating film, a second semiconductor thin film, and a fourth gate insulating film via a second gate electrode, and a source region is formed in the second semiconductor thin film on both sides of the second gate electrode. Alternatively, a second semiconductor region constituting a drain region is provided, and the first semiconductor region provided on the first semiconductor thin film, the first gate electrode, and a portion of the ferroelectric thin film opposed to the first gate electrode The first menu A first ferroelectric gate dual-gate thin film transistor forming a recell is formed, and is opposed to a second semiconductor region, a second gate electrode, and a second gate electrode provided in a second semiconductor thin film. A second ferroelectric gate type dual-gate thin film transistor forming a second memory cell is formed by the ferroelectric thin film of the portion to be formed, and a plurality of first memory cells are connected in series to form a first memory block. As well as
A plurality of second memory cells are connected in series to form a second memory block, and the first memory block and the second
Is a method of driving a nonvolatile semiconductor memory in which a memory cell array is configured by arranging a plurality of memory blocks, and when writing, serially connecting first memory blocks selected by a selection transistor connected to a bit line. The first ferroelectric gate type dual gate thin film transistor constituting the first memory cell is made conductive by the first gate electrode, and the second ferroelectric gate type dual gate thin film transistor at the intersection of the second memory block and the selected word line is turned on. Data is written by inverting the polarization of the ferroelectric connected to the gate portion of the second ferroelectric gate dual gate thin film transistor constituting the memory cell, and at the time of reading, data is selected by the select transistor connected to the bit line. Memory cells other than the selected memory cells of the first memory block The first ferroelectric gate dual gate thin film transistor to be formed is made conductive by the first gate electrode, and the first ferroelectric gate dual transistor constituting the selected memory cell is determined from the value of the bit line current at that time. The data is read by reading the polarization direction of the ferroelectric connected to the gate portion of the gate thin film transistor.

Incidentally, Japanese Patent Application Laid-Open Nos. Hei 7-161854, Hei 8-335645, Hei 7-183401
In the publication, gate electrodes are installed on both sides of the semiconductor thin film,
Ferroelectric gate type dual gate thin film transistors in which at least one of these gate electrodes is connected to a ferroelectric have been proposed, but they are not intended for application to a NAND type nonvolatile memory. Japanese Patent Application Laid-Open No. 10-12887 discloses an example in which a ferroelectric substance is used for applying a bias to a dual gate transistor. However, this ferroelectric substance is not used for holding data but for applying a bias. This is basically different from the present invention.

In the present invention constructed as described above, the thin film transistor provided on both sides of the ferroelectric thin film, that is, the memory cell is constituted by the ferroelectric gate type dual gate thin film transistor. By changing the gate voltage applied to the gate electrode of the ferroelectric gate type dual gate thin film transistor on one surface of the ferroelectric thin film, the ferroelectric thin film on the other surface is not changed without changing the polarization direction. The ferroelectric gate type dual gate thin film transistor can be turned on / off. Therefore, it is possible to arrange the memory cells in a NAND type while suppressing disturbance. This N
In the AND type array, since it is not necessary to make a wiring contact with the source region / drain region for each memory cell, a wiring space is not required, and the cell area can be reduced. Further, the polarization inversion of the ferroelectric is fast, and the voltage required for the polarization inversion is considerably lower than the voltage required for injecting electrons into the floating gate in the flash memory.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

FIG. 1 is a circuit diagram of a memory cell array of a NAND type nonvolatile semiconductor memory according to a first embodiment of the present invention.

In the NAND type nonvolatile semiconductor memory according to the first embodiment, a memory cell constituted by a ferroelectric gate type dual gate thin film transistor provided on both sides of a ferroelectric thin film constituting a ferroelectric gate Are connected in series to form memory blocks, and a plurality of memory blocks provided on both sides of the ferroelectric thin film are arranged to form a memory cell array.

That is, as shown in FIG. 1, n memory cells MCui (however,
i = 1 to n) are connected in series to form a memory block, and n memory cells MC on the other surface of the ferroelectric thin film
di (where i = 1 to n) are connected in series to form a memory block. One end of the memory block on one surface of the ferroelectric thin film is connected to a source line (not shown) via a selection transistor STu1, and the other end is connected to a bit line Bu via a selection transistor STu2. One end of the memory block on the other surface of the ferroelectric thin film is connected to a source line via a selection transistor STd1, and the other end is connected to a bit line Bd via a selection transistor STd2. Here, the select transistors STu1, STu2, STd1, STd2 are not ferroelectric gate type dual gate thin film transistors,
It is composed of a normal thin film transistor having a single gate electrode.

The gate electrode of the ferroelectric gate type dual gate thin film transistor constituting the memory cell at the corresponding stage of all the memory blocks on one surface of the ferroelectric thin film is constituted by a word line Wui. Similarly, the gate electrode of the ferroelectric gate type dual-gate thin film transistor forming the memory cell at the corresponding stage of all the memory blocks on the other surface of the ferroelectric thin film is connected to the word line W
di. Also, the selection transistors ST of all the memory blocks on one surface of the ferroelectric thin film
The gate electrodes of u1 and STu2 are connected to select line WSu, respectively.
1 and WSu2. Similarly, the gate electrodes of the select transistors STd1 and STd2 of all the memory blocks on the other surface of the ferroelectric thin film are respectively connected to select lines WS
d1 and WSd2.

Next, the NAND according to the first embodiment will be described.
A specific example of the structure of the nonvolatile semiconductor memory will be described.

FIG. 2 is a plan view showing a part of the memory cell array, FIG. 3 is a sectional view taken along line III-III of FIG.
FIG. 4 is a sectional view taken along the line IV-IV of FIG. 2, and FIG. 5 is a sectional view taken along the line VV of FIG.

As shown in FIGS. 2, 3, 4 and 5, a word line Wu is formed on one surface of a ferroelectric thin film 1 via a gate insulating film 2, a semiconductor thin film 3 and a gate insulating film 4.
i are provided extending in parallel with each other, and the word line Wdi is formed on the other surface of the ferroelectric thin film 1 in parallel with the word line Wui via the gate insulating film 5, the semiconductor thin film 6, and the gate insulating film 7. They are provided so as to extend in parallel with each other. The semiconductor thin film 3 in the portion between the adjacent word lines Wui is provided with an n ⁺ -type region 8 constituting a source region / drain region of a ferroelectric gate type dual gate thin film transistor constituting the memory cell MCui. The semiconductor thin film 3 other than the n ⁺ -type region 8 is p-type. Further, the semiconductor thin film 6 in a portion between the adjacent word lines Wdi includes:
An n ⁺ -type region 9 is provided which constitutes a source region / drain region of a ferroelectric gate type dual gate thin film transistor constituting a memory cell MCdi. The portion of the semiconductor thin film 6 other than the n ⁺ -type region 9 is p-type. Here, the channel region and the n ⁺ -type region 9 of the ferroelectric gate type dual gate thin film transistor constituting the memory cell MCii are provided at positions corresponding to each other, and the ferroelectric gate type dual gate thin film transistor constituting the memory cell MCdi Channel region and n ⁺ type region 8 are provided at positions corresponding to each other.

The ferroelectric thin film 1 is made of, for example, SBT, PZT
And other ferroelectric materials. Gate insulating films 2, 4, 5, 7
Is, for example, SiO ₂ , SiN, CeO ₂ , Al ₂ O ₃ ,
It is made of an insulator such as Ta ₂ O ₅ . Semiconductor thin films 3, 6
Is, for example, a polycrystalline Si thin film. Word lines Wui, W
di is made of, for example, polycrystalline Si, Ta, W, or the like. Similarly, the selection lines WSu1, WSu2, WSd1, WSd2 are also made of, for example, polycrystalline Si, Ta, W, or the like.

In one example of the NAND type nonvolatile semiconductor memory according to the first embodiment, the gate insulating films 2, 4,.
Reference numerals 5 and 7 are made of a CeO ₂ film having a thickness of 10 nm, and the ferroelectric thin film 1 is made of an SBT film having a thickness of 60 nm. This S
BT has a coercive electric field E _c of 6 × 10 ⁴ V / cm and a remanent polarization P
_r is 7 μC / cm ² and the relative dielectric constant is 200. Also,
Ferroelectric anti voltage V _c is 0.36V, ferroelectric inversion voltage 2
The V _c 0.72V, the cell reversal voltage is 2.5V. The variation width of the threshold voltage _Vth of the ferroelectric gate type dual gate thin film transistor is ± 2.4 V.

Next, an example of a method of manufacturing the NAND-type nonvolatile semiconductor memory according to the first embodiment having the above-described structure is a cross-sectional view corresponding to the cross-sectional view shown in FIG. 3 and FIGS. This will be described with reference to FIG.

First, as shown in FIG.
After polycrystalline Si, Ta, W, or the like is formed thereon, the film is patterned into a predetermined shape by etching to form a word line Wdi.

Next, as shown in FIG. 6B, the word line Wd
The concave portion between i is buried with the flattening film 11 to flatten the surface.

Next, as shown in FIG. 6C, SiO ₂ , SiN, CeO ₂ , A
A gate insulating film 7 and a semiconductor thin film 6 made of l ₂ O ₃ , Ta ₂ O ₅ or the like are sequentially formed.

Next, as shown in FIG.
Then, an n-type impurity is selectively implanted using, for example, a resist pattern (not shown) as a mask to form an n ⁺ -type region 9.

Next, as shown in FIG.
After a gate insulating film 5, a ferroelectric thin film 1, a gate insulating film 2, a semiconductor thin film 3, and a gate insulating film 4 are sequentially formed thereon, a word line Wui is formed on the gate insulating film 4 in the same manner as the word line Wdi. Form.

Thereafter, the supporting substrate 10 and the planarizing film 11
Is removed. Thereby, as shown in FIG. 2, FIG. 3, FIG. 4, and FIG. 5, the intended NAND nonvolatile semiconductor memory is manufactured.

Next, the NAND according to the first embodiment will be described.
A method for erasing, writing, and reading a nonvolatile semiconductor memory will be described.

First, as for erasing, as described later, writing is active writing using a voltage from a transistor, so that a special erasing process is not required and overwriting can be performed.

Writing is performed in order from the first word line to the n-th word line in the memory block. For example,
The processing is performed in order from the word line Wu1 to the word line Wun. In addition, writing can be performed independently even for memory cells connected to the same word line. The voltage required for the polarization reversal of the ferroelectric is V _w (for example, 2.5 V).
Here, as shown in FIG. 8, a state where the polarization direction of the ferroelectric is a direction in which the threshold voltage of the ferroelectric gate type dual gate thin film transistor constituting the memory cell is increased is defined as data “0”. A state in which the threshold voltage is reduced is defined as data “1”.

As an example, consider the case where data "1" is written to memory cell MCu1. In this case, the selection line WS
A voltage equal to or higher than the threshold voltage is applied to u1 to turn on the select transistor STu1, and the select line WSd1 is set to 0 V to turn off the select transistor STd1. On the other hand, all the memory cells MCd are connected to the word lines Wd1 to Wdn.
A voltage V _th E (see FIG. 8) necessary to turn on a transistor constituting i (i = 1 to n) is applied. Then, by applying a voltage higher than the threshold voltage to the selection line WSd2 to turn on the selection transistor STd2,
Applying a V _w to the bit line Bd. Thereby, in memory cell MCu1, n ^{+ at} a position corresponding to the channel region of the transistor constituting memory cell MCu1
When _Vw is applied to the mold region 9, polarization inversion of the ferroelectric occurs, and the threshold voltage of the transistor is lowered, so that data "1" is written. When writing data “0” to the memory cell MCu1, −V _w is applied to the bit line Bu. Thus, arbitrary data can be written to the memory cell MCu1.

Next, data "1" is stored in the memory cell MCd1.
Consider writing. In this case, the selection line WSu1
To 0V to turn off the selection transistor STu1, and apply a voltage higher than the threshold voltage to the selection line WSd1 to turn on the selection transistor STd1. on the other hand,
All the memory cells MCui are connected to the word lines Wu2 to Wun.
A voltage V _th E required to turn on a transistor constituting (i = 2 to n) is applied. At this time, the word line Wu1 is applied to prevent the inversion voltage from being applied to the memory cell MCu1 on the previously written word line Wu1.
By applying a -V _th to 1 to turn off the transistor constituting the memory cell MCU 1. Then, a voltage equal to or higher than the threshold voltage is applied to the selection line WSu2 to select the selection transistor ST.
By turning on the u2, applying a V _w to the bit line Bu. Thus, in the memory cell MCD1, polarization inversion of the ferroelectric by V _w is applied to the channel region to the n ⁺ -type region 8 at the corresponding position of the transistor occurs constituting the memory cell MCD1, transistor The threshold voltage drops, and data “1” is written. When writing data "0" into the memory cell MCd1 applies a -V _w to the bit line Bu. Thus, arbitrary data can be written to the memory cell MCd1.

In the same manner, writing is performed sequentially to the word lines Wun and Wdn while turning off the transistor which has been previously written for each bit line so that the data does not change.

By performing writing as described above, random writing cannot be performed, but writing with less disturbance can be performed.

When writing to another block, the selection transistors STu2 and STd2 are turned off to completely prevent disturbance.

Reading is performed as follows. For example,
When reading data from the memory cells of the memory block connected to the bit line Bu, the selection lines WSu1 and WSu
2, a voltage higher than the threshold voltage is applied to turn on the selection transistors STu1 and STu2. For example, when reading data from the memory cell MCu1, the word line Wu
_Vth E is applied to memory cells MCu2-Mun
The transistors constituting Cun are turned on. And
A predetermined read voltage is applied to the bit line Bu, and the source-
The current between the drains, that is, the current flowing through the bit line Bu is examined. When the current flows, the data of the memory cell MCu1 is “1”. When the current does not flow, the data of the memory cell MCu1 is “0”. Next, the memory cell M
When reading the data of Cdn, the word lines Wd1,
The memory cell MC by applying a V _th E to Wd3~Wdn-1
d1, the transistors constituting MCd3 to MCdn-1 are turned on. Then, a predetermined read voltage is applied to the bit line Bd, and a current between the source and the drain, that is, a current flowing through the bit line Bd is checked. When a current flows, the data of the memory cell MCdn is “1”, and when no current flows, the data of the memory cell MCdn is “0”.

Thereafter, data of each memory cell can be read out in the same manner. Thus, random access is possible at the time of reading.

As described above, according to the first embodiment, a memory cell is constituted by the ferroelectric gate type dual gate thin film transistors provided on both sides of the ferroelectric thin film 1, and a plurality of the memory cells are provided. A memory block is configured by connecting in series, and by arranging a plurality of memory blocks, high integration, high speed, low power consumption, and
It is possible to realize a NAND type nonvolatile semiconductor memory which has less disturbance problem which is a drawback of the ferroelectric gate type memory. Further, since it is not necessary to finely process the ferroelectric thin film 3 for each memory cell, it is easy to manufacture a NAND nonvolatile semiconductor memory. Next, the second embodiment of the present invention
A NAND-type nonvolatile semiconductor memory according to the embodiment will be described. FIG. 9 is a sectional view showing this NAND type nonvolatile semiconductor memory, and is a sectional view corresponding to FIG.

As shown in FIG. 9, the NAND nonvolatile semiconductor memory according to the second embodiment is configured by stacking three layers of the NAND nonvolatile semiconductor memory according to the first embodiment. More specifically, the NAND nonvolatile semiconductor memory according to the second embodiment is the same as the NAND nonvolatile semiconductor memory shown in FIG.
A similar NAND-type nonvolatile semiconductor memory (second layer) is stacked upside down on the (layer), and the same NAND-type nonvolatile semiconductor memory as the first-layer NAND nonvolatile semiconductor memory is stacked on top of it. -Type nonvolatile semiconductor memory (third layer)
Are laminated. No interlayer insulating film is required between each layer. The word line Wui is shared between the first-layer NAND nonvolatile semiconductor memory and the second-layer NAND nonvolatile semiconductor memory. The word line Wdi is shared by the second-layer NAND nonvolatile semiconductor memory and the third-layer NAND nonvolatile semiconductor memory.

According to the second embodiment, the same advantages as those of the first embodiment can be obtained, and further, there is an advantage that the degree of integration can be greatly improved by stacking. be able to.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical concept of the present invention are possible.

For example, the numerical values, structures, shapes, materials, processes, and the like described in the above embodiments are merely examples, and different numerical values, structures, shapes, materials, processes, and the like may be used as necessary. Is possible.

Further, the NAND described in the above embodiment
The method of manufacturing the nonvolatile semiconductor memory is only an example, and a different manufacturing method may be used.

Further, in the above-described second embodiment,
Although the NAND type nonvolatile semiconductor memory according to the first embodiment is stacked in three layers, the number of stacked layers is basically arbitrary.
It is possible to have two or four or more layers.

[0050]

As described above, according to the present invention, a memory cell is constituted by thin film transistors provided on both sides of a ferroelectric thin film, and a plurality of memory cells are connected in series to constitute a memory block. Since a memory cell array is configured by arranging a plurality of memory blocks, a NAND nonvolatile semiconductor memory with high integration, high speed, low power consumption, and low disturbance can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a NAND nonvolatile semiconductor memory according to a first embodiment of the present invention;

FIG. 2 is a plan view showing a partial structural example of a memory cell array of the NAND nonvolatile semiconductor memory according to the first embodiment of the present invention;

FIG. 3 is a sectional view taken along the line III-III in FIG. 2;

FIG. 4 is a sectional view taken along the line IV-IV in FIG. 2;

FIG. 5 is a sectional view taken along the line VV in FIG. 2;

FIG. 6 is a sectional view for explaining an example of the method for manufacturing the NAND nonvolatile semiconductor memory according to the first embodiment of the present invention;

FIG. 7 is a sectional view for explaining an example of the method for manufacturing the NAND-type nonvolatile semiconductor memory according to the first embodiment of the present invention;

FIG. 8 is a schematic diagram showing gate voltage-drain current characteristics of a ferroelectric dual gate thin film transistor constituting a memory cell of the NAND nonvolatile semiconductor memory according to the first embodiment of the present invention;

FIG. 9 is a sectional view showing a NAND-type nonvolatile semiconductor memory according to a second embodiment of the present invention;

FIG. 10 is a circuit diagram showing a one-transistor ferroelectric gate nonvolatile memory.

[Explanation of symbols]

MCu1-MCun, MCd1-MCdn... Memory cells, STu1, STu2, STd1, STd2.
Select transistors, Wu1-Wun, Wd1-Wdn.
..Word lines, WSu1, WSu2, WSd1, and WSd
2 ... Selection line, Bu, Bd ... Bit line, 1 ...
Ferroelectric thin film, 2, 4, 5, 7,... Gate insulating film,
3,6 ... semiconductor thin film, 8,9 ··· n ⁺ -type region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/788 H01L 29/78 371 29/792 F term (Reference) 5B025 AA07 AC01 AD03 AE00 AE05 AE06 AE08 5F001 AA17 AB02 AB20 AD12 AD41 AD51 AD52 AD53 AD70 AE02 AE08 AF10 5F083 EP22 EP28 EP33 EP34 EP49 EP76 FR06 FR10 GA01 GA05 GA09 GA11 GA30 HA02 JA01 JA02 JA03 JA06 JA14 JA15 JA17 JA19 JA39 KA01 LA16

Claims (7)

[Claims] 1. A memory cell is constituted by thin film transistors provided on both sides of a ferroelectric thin film, and a plurality of memory cells are connected in series to constitute a memory block.
A nonvolatile semiconductor memory comprising a plurality of memory blocks arranged to form a memory cell array. 2. The non-volatile semiconductor device according to claim 1, wherein a plurality of the memory cells are connected in series, and a selection transistor is connected to one end of the series connection to form a memory block. memory. 3. The nonvolatile semiconductor memory according to claim 1, wherein one end of said memory block is connected to a bit line. 4. A first gate electrode is provided on one surface of the ferroelectric thin film via a first gate insulating film, a first semiconductor thin film, and a second gate insulating film. A first semiconductor region constituting a source region or a drain region is provided in the first semiconductor thin film on both sides of the gate electrode of the first embodiment, and a third gate is provided on the other surface of the ferroelectric thin film. A second gate electrode is provided via an insulating film, a second semiconductor thin film, and a fourth gate insulating film, and a source region or a drain region is provided in the second semiconductor thin film on both sides of the second gate electrode. And a first semiconductor region provided in the first semiconductor thin film, the first gate electrode, and a portion of the portion facing the first gate electrode. Forcing A first ferroelectric gate type dual-gate thin film transistor constituting the memory cell by the body thin film, the second semiconductor region provided on the second semiconductor thin film, and the second gate electrode The second ferroelectric gate type dual gate thin film transistor constituting the memory cell is constituted by a portion of the ferroelectric thin film opposed to the second gate electrode. Non-volatile semiconductor memory. 5. The semiconductor device according to claim 4, wherein said plurality of nonvolatile semiconductor memories are laminated by sharing said first gate electrode or said second gate electrode. Non-volatile semiconductor memory. 6. The nonvolatile semiconductor memory according to claim 1, wherein said thin film transistor is a thin film transistor using a polycrystalline Si thin film. 7. A first gate electrode is provided on one surface of a ferroelectric thin film via a first gate insulating film, a first semiconductor thin film, and a second gate insulating film. A first semiconductor region constituting a source region or a drain region is provided in the first semiconductor thin film on both sides of the gate electrode, and a third gate insulating film is provided on the other surface of the ferroelectric thin film. A second gate electrode is provided via a film, a second semiconductor thin film, and a fourth gate insulating film, and a source region or a drain region is formed in the second semiconductor thin film on both sides of the second gate electrode. A first semiconductor region provided on the first semiconductor thin film, a first gate electrode, and a portion of the ferroelectric which is opposed to the first gate electrode. Thin film Ri together with the first ferroelectric gate type dual gate thin film transistors forming the first memory cell is constituted, the second
The second semiconductor region, the second gate electrode, and the portion of the ferroelectric thin film facing the second gate electrode, the second ferroelectric thin film forming the second memory cell. A dielectric gate type dual gate thin film transistor is configured, a plurality of the first memory cells are connected in series to form a first memory block, and a plurality of the second memory cells are connected in series to form a second memory cell. And a plurality of the first memory blocks and the plurality of the second memory blocks are arranged to constitute a memory cell array. When configuring the first memory cells connected in series of the first memory block selected by the connected selection transistors The first ferroelectric gate type dual gate thin film transistor is turned on by the first gate electrode, and the second memory cell constituting the second memory cell at the intersection of the second memory block and the selected word line is formed. The first memory selected by the selection transistor connected to the bit line at the time of writing and reading data by inverting the polarization of the ferroelectric connected to the gate portion of the ferroelectric gate dual gate thin film transistor of No. 2 The first ferroelectric gate type dual-gate thin film transistor constituting a memory cell other than the memory cell selected in the block is made conductive by the first gate electrode, and the first ferroelectric gate dual gate thin film transistor is selected from the value of the bit line current at that time. The first ferroelectric gate type dual gate thin film transistor constituting the memory cell Method for driving the nonvolatile semiconductor memory characterized by reading data by reading the polarization direction of the connected ferroelectric gate portion of the data.