JP3246294B2 - Ferroelectric memory device and method of manufacturing the same - Google Patents

Ferroelectric memory device and method of manufacturing the same

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JP3246294B2
JP3246294B2 JP27595695A JP27595695A JP3246294B2 JP 3246294 B2 JP3246294 B2 JP 3246294B2 JP 27595695 A JP27595695 A JP 27595695A JP 27595695 A JP27595695 A JP 27595695A JP 3246294 B2 JP3246294 B2 JP 3246294B2
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ferroelectric
bit line
pair
data
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JPH09121032A (en
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謙士朗 荒瀬
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ソニー株式会社
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Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell comprising two ferroelectric capacitors which are basically complementary to each other, thereby enabling stable operation, high integration and large capacity. The present invention relates to a ferroelectric memory device, and particularly to a device structure, a device operation operation, and a manufacturing method thereof.

[0002]

2. Description of the Related Art An oxide ferroelectric material having a perovskite structure (such as PbZrTiO 3 ) or an oxide ferroelectric material having a Bi-based layered perovskite structure (such as BiSr 2 Ta 2 O 9 ) is insulated from a capacitor. 2. Description of the Related Art A ferroelectric storage device in which a ferroelectric capacitor is formed as a film and data is stored according to the polarization direction of the ferroelectric capacitor is known.

Hereinafter, the hysteresis characteristic of a ferroelectric capacitor will be described with reference to FIG. In FIG. 12, (a) is a hysteresis characteristic, (b) and (c)
Indicates the states of the capacitors to which the first data (hereinafter referred to as data 1) and the second data (hereinafter referred to as data 0) having opposite phases are written.

In the ferroelectric memory device, in the hysteresis characteristic shown in FIG. 12A, a positive voltage is applied to the ferroelectric capacitor (C in the figure), and a residual polarization charge of + Qr remains (FIG. 12A). A) is data 1 (first data),
The state where the negative polarization voltage is applied (D in the figure) and the residual polarization charge of -Qr remains (B in the figure) is used as data 0 (second data) as a nonvolatile memory.

By the way, assuming that the above-described ferroelectric capacitor is used as a nonvolatile ferroelectric memory device, a method of forming one memory cell from one selection transistor and one ferroelectric capacitor (hereinafter referred to as a memory cell). 1TR-1
There is known a method of forming one memory cell from a CAP cell) and two select transistors and two ferroelectric capacitors (hereinafter, a 2TR-2CAP cell).

FIG. 13 is a memory array diagram of a ferroelectric memory device having 1TR-1CAP type cells.

The memory array shown in FIG. 13 has a so-called folded bit line structure. In the figure, MA and MA 'are memory cells, MRA and MRA' are comparison cells, WLA and WL.
A 'is a word line, BLA, BLA' is a bit line, PLA
Is a plate electrode line, RWLA, RWLA 'are word lines for driving the comparison cell, RPLA is a plate electrode line for driving the comparison cell, and CL is each bit line BLA, B
The load capacity of LA 'is shown. The memory cell MA includes a select transistor TA and a ferroelectric capacitor CA, and the memory cell MA ′ includes a select transistor TA ′.
And a ferroelectric capacitor CA '. The comparison cells MRA and MRA 'are provided for comparing and reading the data of the memory cells MA and MA'.
In the case of RA, it is constituted by the selection transistor TRA and the ferroelectric capacitor CRA, and in the case of the comparison cell MRA ', it is constituted by the selection transistor TRA' and the ferroelectric capacitor CRA '.

[0008] In the ferroelectric memory device having the 1TR-1CAP type cell shown in FIG.
The data reading of A is performed by comparison with a comparison cell MRA 'connected to a comparison bit line BLA' adjacent in the folding direction of the read bit line BLA ', and the data reading of the memory cell MA' is performed by reading the read bit BLA '. The comparison is performed with the comparison cell MRA connected to the comparison bit line BLA adjacent in the folding direction. In comparison cells MRA and MRA ', respectively, FIG.
In the hysteresis characteristic described above, the capacitor is optimally designed by adjusting, for example, the capacitor area or the bias voltage so as to be in an intermediate state when the residual polarization charge of + Qr or -Qr is read. Therefore, 1TR-1CA
In the P-type cell, the potential difference between the read bit line of the read cell and the comparison bit line of the comparison cell is amplified by the sense amplifier SA to determine data.

FIG. 14 is a memory array diagram of a ferroelectric memory device having 2TR-2CAP type cells.

In FIG. 14, MA is a memory cell, WL
A indicates a word line, BLA and BLA 'indicate bit lines, and PLA indicates a plate electrode line. The memory cell MA is composed of two select transistors TA and TA ′, which are complementary to each other, and two ferroelectric capacitors CA and CA ′. Note that CL indicates the load capacitance of each bit line BLA, BLA '.

In the ferroelectric memory device having the 2TR-2CAP type cell shown in FIG. 14, data is written to the memory cell MA by two complementary ferroelectric capacitors CA and CA ', respectively. A voltage is applied so as to be in the opposite polarization direction. Therefore, 2T
In the R-2CAP cell, in the hysteresis characteristic of FIG. 12A, the residual polarization charge of + Qr or -Qr causes the bit lines BLA, B at the time of data reading.
It is read to LA '(or in the opposite direction) and complementarily amplified by a sense amplifier.

[0012]

By the way, the above-mentioned 1
In a ferroelectric memory device having a TR-1CAP type cell, the memory cell is composed of one selection transistor and one ferroelectric capacitor, so that the memory cell area is small and suitable for increasing the capacity. However, it is difficult to optimally design the above-described comparative cell, and even if it is possible to optimally design the comparative cell, the potential difference between bit lines at the time of reading is reduced by half compared to the 2TR-2CAP type cell. . Further, in the 1TR-1CAP type cell,
Unlike the 2TR-2CAP type cell, the read cell and the comparison cell are arranged apart from each other on the layout. Therefore, there is a problem that the characteristics of the read cell or the comparison cell vary due to process variations, and that an operation margin at the time of read cannot be sufficiently secured, resulting in a lack of operation stability.

Further, in the ferroelectric memory device having the above-mentioned 2TR-2CAP type cell, a sufficient operation margin at the time of reading can be ensured and stable operation is possible, but the memory cell is composed of two selection transistors and two transistors. Since the ferroelectric capacitor is composed of a plurality of ferroelectric capacitors, there is a problem that the memory cell area becomes large and the capacity cannot be increased.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a ferroelectric memory device which stores data in accordance with the polarization direction of a ferroelectric capacitor, basically including two memory cells. An object of the present invention is to provide a ferroelectric memory device which can be operated stably, and can be highly integrated and can have a large capacity by being constituted by the ferroelectric capacitors of the above.

[0015]

In order to achieve the above object, a ferroelectric memory device according to the present invention comprises a plurality of pairs of main bit lines which are adjacent to each other and form a complementary pair and are wired in a column. Are connected to a plurality of pairs of sub-bit lines which are adjacent to each other and complementary to each other via connection means, and are complementary to each other at lattice positions where the sub-bit line pairs and the plurality of word lines arranged in rows intersect. A memory cell comprising a pair of ferroelectric capacitor pairs is arranged, and one electrode of each ferroelectric capacitor of the ferroelectric capacitor pair of each memory cell is connected to the corresponding sub-bit line of the sub-bit line pair. One electrode is connected to the corresponding sub-bit line of the capacitor pair of the sub-bit line pair, and the other electrode is connected to the word line, and the ferroelectric capacitors of the ferroelectric capacitor pair are complementarily inverted from each other. Minutes in the direction By stores either the data of the first data or the second data of opposite phases.

In the ferroelectric memory device, the connection means is a pair of MOS semiconductor elements complementary to each other, and a source electrode or a drain electrode of each MOS semiconductor element of the pair of MOS semiconductor elements. One is connected to the corresponding main bit line of the main bit line pair, the other is connected to the corresponding sub bit line of the sub bit line pair, and the gate electrode is connected to the selected gate line. The main bit line pair and the sub bit line pair are operatively connected in accordance with the voltage applied to the gate line.

In the ferroelectric memory device, each ferroelectric capacitor of the ferroelectric capacitor pair has the same size.

In the ferroelectric memory device, the first data may be written into the memory cell by selecting a ferroelectric capacitor of one of the ferroelectric capacitor pairs by selecting a sub-bit line that selects a word line potential higher than a selected word line potential. A voltage is applied in a direction in which the potential becomes higher, the ferroelectric capacitor is polarized in the direction of the applied electric field, and the other ferroelectric capacitor of the ferroelectric capacitor pair is set at a voltage higher than the selected word line potential. Also, by applying a voltage in a direction in which the potential of the selected sub-bit line becomes lower, the ferroelectric capacitor is polarized in the direction of the applied electric field, and the writing of the second data to the memory cell is performed by the ferroelectric capacitor. A voltage is applied to each of the ferroelectric capacitors of the pair of ferroelectric capacitors in a direction opposite to that in the case of writing the first data, and the ferroelectric capacitor pair is applied to the applied voltage. It carried out by the polarization direction.

In the ferroelectric memory device, when reading data from a memory cell, a ferroelectric capacitor pair is connected to a sub-bit line pair for selecting a main bit line pair, and a word line voltage for selection is changed. By determining the polarization state of each ferroelectric capacitor and detecting a change in the potential of each main bit line according to the change in the polarization state of each ferroelectric capacitor as a potential difference between the main bit line pair, data determination is performed. I do.

In the ferroelectric memory device, after reading data from the memory cell, data is rewritten to the memory cell.

Further, the ferroelectric memory device has a latch-type sense amplifier corresponding to each main bit line, and latches read data or write data in the sense amplifier so that data for a memory cell is latched. Write or read and rewrite are performed for all the memory cells connected to the selected word line.

Further, in the ferroelectric memory device, the data writing is performed simultaneously on both ferroelectric capacitors of the ferroelectric capacitor pairs of all the memory cells connected to the selected word line. After applying a voltage in the same direction and polarizing and erasing both the ferroelectric capacitors in the direction of the applied electric field, the ferroelectric capacitor pair of the memory cell is changed according to the data to be written to each memory cell. A voltage is applied to one of the ferroelectric capacitors in a direction opposite to that in the erase operation, and the one of the ferroelectric capacitors is polarized in the direction of the applied electric field.

In the ferroelectric memory device, the writing of the data is sequentially performed for each word line in units of all the word lines intersecting the sub-bit line pair selected by the selected gate line. Done.

Further, in the ferroelectric memory device, the data is read and rewritten in units of all word lines intersecting the sub-bit line pair selected by the selected gate line. It is performed in order.

Further, the method of manufacturing a ferroelectric memory device includes a step of forming a lower capacitor electrode of each memory cell by the sub-bit line pair, and a step of forming a ferroelectric capacitor insulating film of each memory cell. Forming an upper layer capacitor electrode for each memory cell, forming the word line such that the word line is connected to the upper capacitor electrode for each memory cell, and forming the main bit line pair. And

In the above-mentioned manufacturing method, the lower capacitor electrode (the sub-bit line pair) is formed of a first-layer platinum or oxide ceramic material, and the ferroelectric capacitor insulating film has a perovskite structure. The upper capacitor material is formed of an oxide ferroelectric material or an oxide ferroelectric material having a Bi-based layered perovskite structure, the upper layer capacitor material is formed of a second layer of platinum or an oxide ceramic material, and the word line is formed of a second layer. 1
The main bit line pair is formed of a second layer of aluminum, its alloy, or a composite film.

According to the ferroelectric memory device of the present invention, the memory cell is basically composed of two ferroelectric capacitors forming a pair complementary to each other.
Memory cells can be operated more stably as compared with the conventional type cells, and the memory cell area is smaller than that of the conventional 2TR-2CAP type cells, enabling high integration.
It is suitable for increasing the capacity.

Further, a pair is formed adjacent to and complementary to each other,
The sub bit number main bit line pairs wired in a column are connected to a plurality of complementary bit pairs adjacent to each other via connecting means, and are connected to the sub bit line pairs in a row. Memory cells each composed of a pair of ferroelectric capacitors complementary to each other are arranged at lattice positions where a plurality of word lines intersect with each other, so that memory cells connected to the main bit line pair during data writing and data reading are arranged. The number is divided, disturb during data writing is reduced,
In addition, it is easy to secure a margin at the time of data reading.

The means for connecting the main bit line pair and the sub-bit line pair is a pair of MOS semiconductor elements complementary to each other, and the source electrode of each MOS semiconductor element of the MOS semiconductor element. Alternatively, one of the drain electrodes is connected to the corresponding main bit line of the main bit line pair, the other is connected to the corresponding sub bit line of the sub bit line pair, and the gate electrode is connected to the selected gate line; This can be achieved by operatively connecting the main bit line pair and the sub bit line pair according to the applied voltage of the selection gate.

Further, by making each ferroelectric capacitor of the above-mentioned ferroelectric capacitor pair the same size, a memory cell can be completely complemented by two ferroelectric capacitors, and a stable operation can be realized. .

The first data is written to the memory cell by applying a voltage to one ferroelectric capacitor of the ferroelectric capacitor pair in a direction in which the potential of the selected sub-bit line becomes higher than the potential of the selected word line. The ferroelectric capacitor is polarized in the direction of the applied electric field, and the potential of the other sub-bit line for selecting another ferroelectric capacitor of the ferroelectric capacitor pair is lower than the potential of the selected word line. The ferroelectric capacitor is polarized in the direction of the applied electric field by applying a voltage in a given direction, and the second data is written to the memory cell by writing each of the ferroelectric capacitors of the ferroelectric capacitor pair. To
This can be performed by performing polarization in the direction opposite to the case of writing the first data.

For reading data from the memory cell, the data is connected to a sub-bit line pair for selecting a main bit line pair.
The word line voltage to be selected is changed to change the polarization state of each ferroelectric capacitor of the ferroelectric capacitor pair, and the change in the potential of each main bit line according to the change in the polarization state of each ferroelectric capacitor is determined. It is possible to determine data by detecting the potential difference of the main bit line.

Further, by rewriting the data in the memory cell after the data is read from the memory cell, the data can be recovered even if the data content in the memory cell is destroyed at the time of reading the data. .

Further, a latch-type sense amplifier is provided corresponding to each main bit line pair, and read data or write data is latched in the sense amplifier to write or read and rewrite data in the memory cell. Is performed collectively for all the memory cells connected to the selected word line, so that high-speed writing and reading of data can be performed, which is preferable.

In the data writing, a voltage is simultaneously applied to both ferroelectric capacitors of the pair of ferroelectric capacitors of all the memory cells connected to the selected word line in the same direction. Erasing the two ferroelectric capacitors in the direction of the applied electric field,
After the erasing step, a voltage is applied in a direction opposite to the erasing step to one of the ferroelectric capacitors of the pair of ferroelectric capacitors of the memory cell in accordance with data to be written to each memory cell. By configuring one of the ferroelectric capacitors in a writing step of polarizing in the direction of the applied electric field, it is possible to reduce the disturb voltage applied to the non-selected memory cells during data writing.

In addition, the above-described data writing is performed by the selection gate.
It is possible to limit the number of disturbances applied to the non-selected memory cells at the time of data writing by sequentially performing each word line in units of all word lines intersecting the sub-bit line pair selected by the data line. is there.

The data reading and rewriting are performed in order for each word line in units of all the word lines intersecting the sub-bit line pair selected by the selected gate line. At the time of rewriting, it is possible to limit the number of disturbances applied to the non-selected memory cells.

In the method of manufacturing a ferroelectric memory device according to the present invention, a step of forming a capacitor electrode in a lower layer of each memory cell by the sub-bit line pair and a step of forming a ferroelectric capacitor insulating film of each memory cell are performed. Forming the upper layer capacitor electrode for each memory cell, forming the word line so that the word line is connected to the upper capacitor electrode for each memory cell, This is possible by the step of forming pairs.

More specifically, for example, the lower-layer capacitor electrode (the sub-bit line pair) is formed of a first-layer platinum or oxide ceramic material, and the ferroelectric capacitor insulator has a perovskite structure. The upper layer capacitor electrode is formed of a second-layer platinum or oxide-based selenium mix material, and the word line is formed of a second-layer platinum-based or perovskite-structured perovskite-structured oxide ferroelectric material. Is the first
The main bit line pair is formed of a second layer of aluminum, its alloy, or a composite film.

[0040]

FIG. 1 is a diagram showing a memory array in a ferroelectric memory device according to the present invention.

In the memory cell diagram of FIG. 1, 1 in FIG.
Although only one sub-bit line pair is shown for each pair of main bit lines, this is for the sake of convenience, and in practice, a plurality of sub-bit line pairs are provided for each of the plurality of main bit line pairs. A sub-bit line pair is connected. Although the number of word lines intersecting the sub-bit line pair is M in the figure, specifically, four or sixteen are appropriate.

In the memory array diagram of FIG.
WLm and WLM are word lines, MBLN and MBLN 'are main bit line pairs complementary to each other, SBLN and SBL.
N 'is a complementary bit line pair complementary to each other, STN, S
TN ′ denotes a pair of complementary selection transistors for operatively connecting the main bit line pair and the sub bit line pair in accordance with the operation, and the selection transistor pair STN, ST
N ′ is controlled by the selected gate line SL. Each word line WL1, WLm, WLM and each sub-bit line pair SBLN,
At the intersection with the SBLN ', a memory cell M1, consisting of two ferroelectric capacitors forming a pair complementary to each other, is provided.
N, Mm, N, MM, N are arranged, the memory cell M1, N is formed of ferroelectric capacitors C1, N and C1, N ', and the memory cell MM, N is formed of ferroelectric capacitors CM, N and CM, N. ', Respectively. In the ferroelectric capacitor, one electrode is connected to a corresponding sub-bit line of the sub-bit line pair, and the other electrode is connected to a corresponding word line.

The transistors PCTN and PCTN 'are turned on by the precharge signal .phi.PC.
MBLN ′ is a transistor for precharging the precharge voltage to the precharge voltage VPC.
TN ′ is set to the main bit line pair M by the column selection signal φC.
This is a transistor for connecting BLN and MBLN ′ to the sense amplifier. The sense amplifier SAN is a sense amplifier connected to the main bit line pair MBLN, MBLN ′, is activated by the sense enable signal φSE, and senses a potential difference between the node potentials VN and VN ′.

FIG. 2 is a pattern layout diagram in the memory array diagram of FIG. FIG. 3 is a cross-sectional view of the device structure viewed from the AA ′ direction in the pattern layout diagram of FIG.

FIG. 3 is a diagram showing the pattern layout of FIG.
1 is a silicon substrate, 2
LOCOS element isolation, 3-gate oxide film, and 4 are source / drain n + diffusion layer regions of the select transistor pair STN, STN '. Reference numeral 5 denotes a selection gate line SL, which is a normal polysilicon or polycide gate electrode. 6
Is a pair of sub-bit lines SBLN and SBLN ', and is also a lower electrode of a ferroelectric capacitor. Specifically, it is formed of a first platinum layer. Reference numeral 7 denotes a ferroelectric capacitor insulator, specifically, a ferroelectric material having hysteresis characteristics, for example, PbZrTiO 3 , BiSr 2 Ta
It is formed of 2 O 9 or the like. Reference numeral 8 denotes an upper electrode of each of the ferroelectric capacitors C1, N, C1, N ', Cm, N, Cm, N', CM, N, and CM, N ', and more specifically, a second platinum layer. Is formed. Reference numeral 9 denotes an interlayer insulating film below the first-layer aluminum wiring, which is a normal CVD silicon oxide film.

The contact holes 10a, 10b, 10c, and 10d are contact holes under the first-layer aluminum wiring. The contact holes 10a and 10d correspond to the first-layer aluminum wiring and the n + diffusion layer region, respectively. The first-layer aluminum wiring is connected to the first-layer platinum layer, and the contact hole 10c is for connecting the first-layer aluminum wiring to the second-layer platinum layer. Reference numerals 11a, 11b, and 11c denote first-layer aluminum wirings. The first-layer aluminum wiring 11a is a bridge wiring of a sub-bit line, and the first-layer aluminum wiring 11b is word lines WL1, MLm, and WL.
M, the first-layer aluminum wiring 11c forms a pad aluminum layer for connecting the second-layer aluminum wiring to the n + diffusion layer region. Reference numeral 12 denotes an interlayer insulating film below the second-layer aluminum wiring, which is a normal CVD silicon oxide film. Reference numeral 13 denotes a contact hole below the second-layer aluminum wiring, and connects the second-layer aluminum wiring to the first-layer aluminum wiring. Reference numeral 14 denotes a second-layer aluminum interconnection, which is a main bit line pair MBLN, MBL
N ′.

Next, referring to the timing chart of FIG. 4 and the hysteresis characteristic of FIG. 6, the first embodiment in the case where data is written to a memory cell in the memory array diagram of FIG. 1 will be described in order. I do.

The timing chart of FIG. 4 shows that the word line WLm and the sub-bit line pair SBLN, SBLN 'are selected and the first data (hereinafter, one data) is stored in the memory cell Mm, N.
FIG. 9 is a timing chart when writing is performed. In this case, the data is written by applying a voltage to the ferroelectric capacitor Cm, N in a direction in which the potential of the selected sub-bit line is higher than the potential of the selected word line, and applying the applied electric field to the ferroelectric capacitor Cm, N. And a voltage is applied to the ferroelectric capacitor Cm, N ′ in a direction in which the potential of the selected sub-bit line is lower than the potential of the selected word line, and the ferroelectric capacitor is subjected to the applied electric field. This is done by polarization in the direction.

First, at time t1, the ferroelectric capacitor C
The main bit line MBLN connected to m, N is connected to the power supply voltage VCC.
(3.3 V), the main bit line MBLN 'connected to the ferroelectric capacitor Cm, N' is set to the ground voltage (0 V).

Next, at time t2, the selected gate line SL is set to 0.
From V to 5 V, the selected word line WLm connected to the ferroelectric capacitors Cm, N, Cm, N 'is connected to the power supply voltage VCC (3.3
V), unselected word lines WL1 to WLM other than WLm
To (1/2) VCC (1.65V). as a result,
The ferroelectric capacitor Cm, N 'moves to the state of the point D in the hysteresis characteristic of FIG. 6 by time t3.

Next, at time t3, the selected word line WLm falls to the ground voltage (0 V). As a result, the ferroelectric capacitor Cm, N moves to the state of the point C in the hysteresis characteristic of FIG. 6 by time t4, and the writing of one data to the memory cell Mm, N is completed. Finally at time t4
And all the main bit line pairs MBLN, MBLN ′ are set to 0V.
Then, the selected gate line SL and all the word lines WL1 to WLM are dropped to the ground voltage (0 V), thereby completing the write operation.

During data writing, non-selected word lines WL1 to WLM other than WLm are set to (1/2) VCC (1.65).
V). As a result, each ferroelectric capacitor of the non-selected memory cell other than Mm, N connected to the selected sub-bit line pair has (1/2) VCC (1.65 V). ) Is applied. The disturb voltage causes a problem when the disturb voltage is applied in a direction in which the polarization state is opposite to the polarization state recorded in the ferroelectric capacitor.

For example, when the ferroelectric capacitor of the non-selected memory cell is in the polarization state at the point A in the hysteresis characteristic of FIG. 6, the disturb voltage is applied, and as a result, the ferroelectric capacitor of the ferroelectric capacitor from the point A to the point A1. The polarization state changes. When the ferroelectric capacitor of the unselected memory cell is in the polarization state at the point B in the hysteresis characteristic of FIG. 6, the disturb voltage is applied, and as a result, the polarization state of the ferroelectric capacitor is changed from the point B to the point B1. Changes. However, when the polarization state of the ferroelectric capacitor in the non-selected memory cell is the polarization state of the point A in the hysteresis characteristic of FIG. 6 unless the polarization state changes from the point A to the point A3. When the ferroelectric capacitor of the unselected memory cell is in the polarization state at point B in the hysteresis characteristic of FIG. 6, unless the polarization state changes from point B to point B3, the polarization state does not reverse. No problem.

Next, referring to the timing chart of FIG. 5 and the hysteresis characteristic of FIG. 6, a description will be given of a second embodiment in which data is written to a memory cell in the memory array diagram of FIG. I do. The advantage of the second embodiment over the first embodiment of FIG. 4 is that the disturb voltage applied to each ferroelectric capacitor of the non-selected memory cell at the time of data writing is (1/2) VCC
(1.65 V) to (1/3) VCC (1.1 V).

In the case of FIG. 5, as in FIG.
FIG. 11 is a timing chart in a case where m and a pair of sub-bit lines SBLN and SBLN ′ are selected and one data is written to a memory cell Mm, N. In the case of the second embodiment of FIG.
Unlike the first embodiment shown in FIG. 4, a voltage is applied to both ferroelectric capacitors of all the ferroelectric capacitor pairs of all the memory cells connected to the selected word line in the same direction. Then, an erasing step in which both the ferroelectric capacitors are polarized in the direction of the applied electric field, and after the erasing step, which of the pair of ferroelectric capacitors of the memory cell is performed according to data to be written in each memory cell A voltage is applied to one of the ferroelectric capacitors in a direction opposite to the erasing step, and a writing step of polarizing one of the ferroelectric capacitors in the direction of the applied electric field is performed. , A data write operation is configured.

In this case, in the erasing step for the memory cell, the voltage is applied in a direction in which the word line potential is higher than the sub-bit line potential to polarize both ferroelectric capacitors in the direction of the applied electric field. The writing step for the memory cell is performed by applying a voltage in a direction in which the sub-bit line potential becomes higher than the word line potential and polarizing one of the ferroelectric capacitors in the direction of the applied electric field.

First, at time t1, all the main bit line pairs MBLN, MBLN 'are set to the ground voltage (0 V). Then, the selected gate line SL is changed from 0 V to 5 V, and the selected word line WLm is turned on. All the non-selected word lines WL1 to WLM other than WLm are set to the ground voltage (0 V) at the voltage VCC (3.3 V). As a result, both ferroelectric capacitors Cm, N, Cm, N 'of the ferroelectric capacitor pairs of all the memory cells connected to the selected word line WLm change to the state at point D in the hysteresis characteristic of FIG. By t2, the erasing step is completed.

Next, at time t2, the selected gate line SL and the selected word line WLm are dropped to the ground voltage (0 V), and then the polarization state is reversed to the polarization state at the time of erasing. Ferroelectric capacitor Cm, N to be written
Of the main bit line MBLN connected to the power supply voltage VCC
(3.3 V), the main bit line MBLN 'connected to the ferroelectric capacitor Cm, N', which can remain in the polarization state at the time of erasing.
Is set to (1/3) VCC (1.1 V). Next, at time t
In step 3, the selection gate line SL is set to 5 V, the selected word line WLm is set to the ground voltage (0 V), and all the non-selected word lines WL1 to WLM other than WLm are set to (2/3) VCC (2.2 V). . As a result, the ferroelectric capacitor Cm, N
The hysteresis characteristic moves from point D to point C by time t4, and the writing step is completed. Finally, at time t4, all main bit line pairs MBLN, MBL
After setting N 'to (1/3) VCC (1.1 V), the selected gate line SL and all word lines WL1 to WLM are dropped to the ground voltage (0 V), thereby completing the write operation. .

Note that during the writing step, W
Unselected word lines WL1 to WLM other than Lm are (2/3) VC
C (2.2 V). As a result, each ferroelectric capacitor of the non-selected memory cell other than Mm, N connected to the selected sub-bit line pair has (1/3) VCC (1.1
A disturb voltage V) is applied. The disturb voltage causes a problem when the disturb voltage is applied in a direction in which the polarization state is opposite to the polarization state recorded in the ferroelectric capacitor.

For example, when the ferroelectric capacitor of the non-selected memory cell is in the polarization state at the point A in the hysteresis characteristic of FIG. 6, as a result of the disturb voltage being applied, the ferroelectric capacitor of the ferroelectric capacitor from the point A to the point A2 is changed. The polarization state changes. Further, when the ferroelectric capacitor of the unselected memory cell is in the polarization state at point B in the hysteresis characteristic of FIG.
The polarization state of the ferroelectric capacitor changes from point to point B2. However, in the case of the second embodiment of FIG. 5, the disturbance to the ferroelectric capacitor of the non-selected memory cell can be significantly reduced as compared with the first embodiment of FIG. 4, based on the hysteresis characteristics of FIG. I understand. Therefore, it is impossible that the polarization state of the ferroelectric capacitor of the non-selected memory cell changes and is inverted.

In both the first embodiment of FIG. 4 and the second embodiment of FIG. 5, data is written to memory cells connected to one selected word line at a time. However, data writing may be performed sequentially for each word line, with the unit of data writing being all word lines intersecting the sub-bit line pair selected by the selection gate line. For example, in the case of the first embodiment shown in FIG. 4 and the second embodiment shown in FIG. 5, the data writing is performed using the word lines WL1 to WLM as one unit.
Data writing may be performed in the order of 1, WL2,... WLM. Such data writing in units of blocks makes it possible to limit the number of disturbances to the non-selected memory cells at the time of data writing to a maximum of (M-1) times, which is preferable from the viewpoint of preventing disturbance.

Subsequently, in the memory array diagram of FIG.
First case of reading data from a memory cell
Will be sequentially described with reference to the timing chart of FIG. 7 and the hysteresis characteristic of FIG.

The timing chart of FIG. 7 shows that one word recorded in the memory cell Mm, N is read out by selecting the word line WLm and the sub-bit line pair SBLN, SBLN ', and thereafter, the memory cell Mm, N FIG. 9 is a timing chart when rewriting one data to the memory. In this case, when reading data from the memory cell, the polarization state of each ferroelectric capacitor of the ferroelectric capacitor pair is changed by connecting the main bit line pair to the sub-bit line pair selecting the word line voltage to be selected. The data is determined by detecting the change in the potential of each main bit line according to the change in the polarization state of each ferroelectric capacitor as a potential difference between the pair of main bit lines. The rewriting of data to the memory cells is the same as that in the first embodiment of the data writing method of FIG.

First, at time t1, precharge signal φP
By raising C to the power supply voltage VCC (3.3 V) and raising the column selection signal φC to 5 V, the main bit line pair MBLN, MBLN ′ is precharged to the precharge voltage VPC (0 V) by time t2, The main bit line pair MBLN, MBLN ′ is connected to the sense amplifier node VN,
VN '.

Next, at time t2, the precharge signal φP
C is dropped to 0 V, and the main bit line pair MBLN, MBL
After N ′ is set in a floating state, the selection gate line S
L from 0V to 5V, and the selected word line WLm to which the read memory cell Mm, N is connected from 0V to the power supply voltage VCC.
(3.3V). As a result, the selected word line W
Each of the ferroelectric capacitors Cm, N, Cm, N 'of the ferroelectric capacitor pairs of all the memory cells connected to Lm is shown in FIG.
In the hysteresis characteristic of (1), the polarization state changes in the direction toward point D.

Therefore, the polarization state of the ferroelectric capacitor Cm, N, which was in the polarization state at the point A before reading, is inverted, and the potential change ΔV (+) of the main bit line MBLN is large. It is represented by 1). In addition, the polarization state of the ferroelectric capacitor Cm, N ', which was in the polarization state at the point B before reading, does not reverse, and the potential change of the main bit line MBLN', ΔV
(−) Is small and is represented by the following equation (2). ΔV (+) = VCC · [C (+) / {(M−1) · C (−) + C (+) + CB L}] (1) ΔV (−) = VCC · [C (−) / {M · C (−) + CBL}] (2) In the expressions (1) and (2), C (+) is the capacitance when the polarization state of the ferroelectric capacitor is inverted.
C (-) is the capacitance when the polarization state of the ferroelectric capacitor is not inverted, and CBL is the bit line capacitance. M is the number of word lines connected to the sub-bit line pair. In this case, the number is eight, and the power supply voltage VCC is 3.3 V. In the case of a general memory cell, C (+) ≒ 500fF, C
Since (−) ≒ 100 fF and CBL ≒ 1000 fF, from the expressions (1) and (2), ΔV (+), ΔV
(-) Is the following degree. ΔV (+) = 0.75V ΔV (−) = 0.18V

The above can be illustrated and described also in the hysteresis characteristic of FIG. That is, in the case of the ferroelectric capacitor Cm, N which was in the polarization state at the point A before the reading, the state moves from the state at the point A to the state at the point E and the polarization state is reversed. The ferroelectric capacitors C of non-selected memory cells other than Cm, N connected to the sub-bit line SBLN
1, N to CM, N move from the state of the point A to the state of the point G when the polarization state of the point A is present before the reading, and when the polarization state of the point B is present before the reading, The state moves from the state to the state at the point I, but the original polarization state is maintained as it is.

Further, in the case of the ferroelectric capacitor Cm, N 'which was in the polarization state at the point B before the reading, the F
Move to the point state, but do not reverse the polarization state. The ferroelectric capacitors C1, N to CM, of the non-selected memory cells other than Cm, N 'connected to the sub-bit line SBLN'.
N ′ moves from the state of the point A to the state of the point H when the polarization state of the point A is present before the reading, and is changed from the state of the point B to the point J when the polarization state of the point B is present before the reading. However, the original polarization state is maintained as it is. In addition,
In the hysteresis characteristic shown in FIG. 9, the inclination of the straight line indicated by the alternate long and short dash line A-E is the capacitance C when the above-mentioned polarization state is reversed.
(+), And the inclination of the straight line of the dashed line BF is the capacitance C (−) when the above-mentioned polarization state is reversed.
Is represented.

Next, at time t3, the selected gate line SL and then the selected word line WLm are lowered to 0 V, and at time t4, the sense enable signal φSE is changed to the power supply voltage VCC (3.3).
By raising the voltage to V), the sense amplifier SAN is activated. As a result, the sense amplifier SAN changes the potential change ΔV (−) (node potential VN) of the main bit line MBLN and the potential change ΔV (−) of the main bit line MBLN ′.
(Node potential VN ′).

Therefore, assuming that ΔV (+) = 0.75V and ΔV (−) = 0.18V, sense amplifier SA
N can sense a potential difference of about 0.47V. As a result, one data recorded in the read memory cell Mm, N is stored in the sense amplifier SAN at time t.
By 5, the sense latch is performed, the potential of the main bit line MBLN is set to the power supply voltage VCC (3.3 V), and the potential of the main bit line MBLN ′ is set to the ground voltage (0 V).

Now, from time t5, rewriting of data to the read memory cell Mm, N is started.

First, at time t5, select gate line SL is set to 0.
From V to 5 V, the selected word line WLm to which the memory cell Mm, N is connected is set to the power supply voltage VCC (3.3 V), and all non-selected word lines other than WLm are set to (1/2) VCC (1.6).
5V). As a result, the ferroelectric capacitor Cm,
N ′ moves to the state of point D in the hysteresis characteristic of FIG. 9 by time t6.

Next, at time t6, the selected word line WLm falls to the ground voltage (0 V). As a result, the ferroelectric capacitor Cm, N has a hysteresis characteristic of FIG.
The state moves to the point state by time t7, and the rewriting of data to the memory cell Mm, N is completed. Finally, at time t
In step 7, the column selection signal φC is dropped to 0 V, so that the main bit lines MBLN and MBLN ′ are disconnected from the sense amplifier nodes VN and VN ′, and then the precharge signal φPC is changed to the power supply voltage VCC (3.3 V). By starting up, all the main bit line pairs MBLN, MBLN ′
Is precharged to a precharge voltage VPC (0 V). After that, the selection gate line SL and all the word lines WL
By dropping 1 to WLM to the ground voltage (0 V), all the operations are completed.

During the data rewriting period, WLm
Word lines WL1 to WLM other than (1/2) VCC (1.6
5 V). As a result, the disturb voltage of (1/2) VCC (1.65 V) is applied to the ferroelectric capacitors of the non-selected memory cells other than Mm, N connected to the selected sub-bit line. Is applied. This is the same as the case of the first embodiment of the data writing described with reference to FIG.

Next, in the memory array diagram of FIG. 1, a second embodiment in which data is read from a memory cell will be described with reference to the timing chart of FIG. 8 and FIG.
Will be described in order with reference to the hysteresis characteristic of FIG. The advantage of the second embodiment over the first embodiment of FIG. 7 is that the disturbance voltage applied to the non-selected memory cells at the time of data rewriting is reduced from (1/2) VCC (1.65 V).
(1/3) VCC (1.1 V).

FIG. 8 is a timing chart in the case where one data recorded in the memory cell Mm, N is rewritten, as in the case of FIG. In this case, the reading of data from the memory cells is the same as in the first embodiment of the data reading method of FIG. Also,
Rewriting of data to the memory cells is the same as that in the second embodiment of the data writing method of FIG.

First, at time t1, precharge signal φP
By raising C to the power supply voltage VCC (3.3 V) and raising the column selection signal φC to 5 V, the main bit line pair MBLN, MBLN ′ is precharged to the precharge voltage VPC (0 V) by time t2. The main bit line pair MBLN, MBLN ′ is connected to the node V of the sense amplifier.
N, VN '.

Next, at time t2, the precharge signal φP
C is dropped to 0 V, and the main bit line pair MBLN, MBL
After N ′ is set in a floating state, the selection gate line S
L from 0V to 5V, and the selected word line WLm to which the read memory cell Mm, N is connected from 0V to the power supply voltage VCC.
(3.3V). As a result, the selected word line W
Each of the ferroelectric capacitors Cm, N, Cm, N 'of the ferroelectric capacitor pairs of all the memory cells connected to Lm is shown in FIG.
In the hysteresis characteristic of (1), the polarization state changes in the direction toward point D.

For this reason, the polarization state of the ferroelectric capacitor Cm, N, which was in the polarization state at the point A before reading, is inverted, and the potential change ΔV (+) of the main bit line MBLN is large. As described in the first embodiment, ΔV
(+) = 0.75V is expected. Further, the ferroelectric capacitor Cm, N ′ which was in the polarization state at the point B before reading was
The polarization state is not inverted, and the potential change ΔV (−) of the main bit line MBLN ′ is small, and ΔV (−) = 0.18 V is expected as described in the first embodiment of FIG.

The above can be illustrated and described also in the hysteresis characteristic of FIG. 9 as in the case of the first embodiment of FIG.

Next, at time t3, the selection gate line SL is
Next, the selected word line WLm is dropped to 0 V, and at time t4
And the sense enable signal φSE is changed to the power supply voltage VCC.
(3.3V), the sense amplifier S
Activate the AN. As a result, one data is sense-latched to the sense amplifier SAN by time t5, and the potential of the main bit line MBLN ′ is changed to the power supply voltage VCC (3.3).
V), and the potential of the main bit line MBLN ′ is set to the ground voltage (0 V).

Now, from time t5, rewriting of data to the read memory cell Mm, N is started.

First, at time t5, the column selection signal φC falls to 0 V, thereby causing the main bit line pair MBLN,
MBLN ′ is connected to nodes VN and V of the respective sense amplifiers.
After disconnection from N ′, all the main bit line pairs MBLN and MBLN ′ are precharged to the precharge voltage VPC (0 V) by raising the precharge signal φPC to the power supply voltage VCC (3.3 V). Subsequently, the selection gate line SL is set from 0 V to 5 V, the selected word line WLm is set to the power supply voltage VCC (3.3 V), and all the unselected word lines WL1 to WLM other than WLm are set to the ground voltage (0 V). . As a result, both ferroelectric capacitors Cm, N, Cm, N 'of the ferroelectric capacitor pairs of all the memory cells connected to the selected word line WLm return to the state of point D in the hysteresis characteristic of FIG. By t6, the erasing step is completed.

Next, at time t6, the selected gate line SL and the selected word line WLm fall to the ground voltage (0 V). Next, the power supply of the sense amplifier system is kept at the power supply voltage VCC (3.3 V) on the high side and the ground voltage (0 V) on the low side.
From (1/3) VCC (1.1v). Next, the column selection signal φC is dropped to 5 V, and again the potential of the main bit line MBLN is changed to the power supply voltage VCC (3.3 V) by the sense amplifier SAN, and the potential of the main bit line MBLN ′ is changed again.
(1/3) Set to VCC. Next, at time t7, the selected gate line SL is set to 5 V, and the selected word line WLm is set to the ground voltage (0
V), all non-selected word lines WL1 other than WLm
WLWLM is set to (2/3) VCC (2.2 V).

As a result, the ferroelectric capacitor Cm, N becomes
In the hysteresis characteristic of FIG. 9, the state moves from point D to point C by time t8, and the writing step is completed.
Finally, at time t8, the column selection signal φC falls to 0 V, thereby disconnecting the main bit line pair MBLN, MBLN ′ from the sense amplifier nodes VN, VN ′.
The precharge signal φPC is changed to the power supply voltage VCC (3.3 V).
To all main bit line pairs MBL
N, MBLN 'to the precharge voltage VPC (1/3 VCC
(1.1 V)). Thereafter, the selection gate line SL and all the word lines WL1 to WLM are lowered to the ground voltage (0 V), thereby completing all the operations.

During the data rewriting period, W
Word lines WL1 to WLM not selected other than Lm are (2/3) VC
C (2.2 V). As a result, (1/3) VCC (1) is applied to the ferroelectric capacitors of the non-selected memory cells other than Mm, N connected to the selected sub-bit line. .1V)
Will be applied. this is,
This is the same as the case of the second embodiment of the data write described in FIG. 5, and the disturbance to the unselected memory cells can be significantly reduced as compared with the case of the first embodiment of the data read of FIG.

In the case of the first embodiment shown in FIG. 7 and the case of the second embodiment shown in FIG. 8, data is simultaneously read from and read to the memory cells connected to one selected word line. Although rewriting is performed, data reading and rewriting are performed in units of all word lines intersecting the sub-bit line selected by the selection gate line, and data reading and rewriting are sequentially performed for each word line. Rewriting may be performed. For example, in the case of the first embodiment shown in FIG. 7 and the second embodiment shown in FIG. 8, data reading and rewriting are performed by the word lines WL1 to WLM.
.. WLM may be read and rewritten sequentially in the order of WL1, WL2,... WLM. By reading and rewriting data in block units as described above, it is possible to limit the number of disturbances to the non-selected memory cells at the time of data rewriting to a maximum of (M-1) times, which is preferable from the viewpoint of preventing disturbance. It is.

FIG. 10 is a diagram showing a specific circuit example of the sense amplifier SAN in the memory array diagram of FIG.

In the sense amplifier of FIG. 10, a p-channel MOS (hereinafter referred to as PMOS) transistor TP
1. N-channel MOS (hereinafter referred to as NMOS) transistor TN1 and PMOS transistors TP2, N
A latch circuit is constituted by a complementary inverter circuit constituted by the MOS transistor TN2. This latch circuit includes a PMOS transistor TP3 and an NMOS transistor TP3.
Transistor TN3 receives and activates sense enable signal φSE to amplify and latch the potential difference between nodes N1 and N2.

By providing a latch type sense amplifier as shown in FIG. 10 corresponding to each main bit line pair, it becomes possible to latch read data or write data in the sense amplifier. As a result, as shown in the examples of FIG. 4, FIG. 5, FIG. 7, and FIG. 8, writing, reading, and rewriting of data to the memory cells can be performed collectively for all the memory cells connected to the selected word line. it can.

Next, an example of a process flow for manufacturing the ferroelectric memory device of the present invention will be described.

FIGS. 11A to 11E are views showing a process flow up to the device structure sectional view of FIG.

First, as shown in FIG. 11A, a LOCOS element isolation region 2 and a gate oxide film 3 are formed on a silicon substrate 1, and a polysilicon or polycide gate electrode 5 is formed. Until the source / drain n + diffusion layer region 4 is formed by implantation, a normal CM
It is the same as the OS process.

Next, as shown in FIG. 11B, the first platinum layer is formed by, for example,
0 nm, and a ferroelectric thin film (for example, P
bZrTiO 3 , BiSr 2 Ta 2 O 9 ) is formed to a thickness of about 200 nm by sputtering or the like. Next, the first platinum layer and the ferroelectric thin film are simultaneously etched by RIE or the like to form a ferroelectric capacitor lower electrode 6 and a ferroelectric capacitor insulating film 7.

Next, as shown in FIG. 11C, the second platinum layer is formed by, for example,
A ferroelectric capacitor upper electrode 8 is formed by etching using an RIE method or the like.

Next, as shown in FIG.
After forming an interlayer insulating film (SiO 2 film) 9 by
After forming contact holes 10a, 10b, 10c, and 10d, a first aluminum layer is formed by a sputtering method, and further etched to form a sub bit line bridge wiring 11a, a word line 11b, and a pad aluminum. The layer 11c is formed.

Finally, as shown in FIG.
After an interlayer insulating film (SiO 2 film) 12 is formed on the side D, a contact hole 13 is formed, and thereafter, a second aluminum layer is formed by sputtering, and further etched to form a main bit line pair. 14 is formed. As a result of the above process flow, a device structure sectional view of FIG. 3 is obtained.

[0098]

As described above, according to the ferroelectric memory device of the present invention, a plurality of pairs of main bit lines which are adjacent to each other and form a complementary pair and are wired in a column are connected to each other. Connected to a plurality of pairs of sub-bit lines which are adjacent to each other and complementary to each other, and which are complementary to each other at lattice positions where the sub-bit line pairs and a plurality of word lines arranged in rows intersect. A memory cell composed of a ferroelectric capacitor pair is arranged. As a result, a memory cell composed of two ferroelectric capacitors can perform a completely complementary operation, so that a stable operation of the memory cell can be performed, and a ferroelectric memory device capable of high integration and large capacity can be provided. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a memory array of a ferroelectric memory device according to the present invention.

FIG. 2 is a diagram showing a pattern layout in the memory array diagram of FIG. 1;

FIG. 3 is a diagram showing a pattern A-
It is a figure which shows the device structure cross section seen from A 'direction.

FIG. 4 is a diagram showing a timing chart in the case of the first embodiment for writing data in the memory array diagram of FIG. 1;

5 is a diagram showing a timing chart in the case of a second embodiment in which data is written in the memory array diagram of FIG. 1;

FIG. 6 is a diagram showing hysteresis characteristics of a ferroelectric capacitor for explaining the first data writing embodiment of FIG. 4 and the second data writing example of FIG. 5;

FIG. 7 is a diagram showing a timing chart in the case of the first embodiment for reading data in the memory array diagram of FIG. 1;

FIG. 8 is a diagram showing a timing chart in the case of the second embodiment for reading data in the memory array diagram of FIG. 1;

9 is a diagram illustrating a hysteresis characteristic of a ferroelectric capacitor for describing the first data read embodiment of FIG. 7 and the second data read embodiment of FIG. 8;

FIG. 10 is a diagram showing a specific circuit of a sense amplifier.

FIG. 11 is a view showing a process flow of the ferroelectric memory device according to the present invention.

FIG. 12 is a diagram showing a hysteresis characteristic of a ferroelectric capacitor and a state of a capacitor in which first data and second data having phases opposite to each other are written.

FIG. 13 is a diagram showing a memory array of a ferroelectric memory device having 1TR-1CAP type cells.

FIG. 14 is a diagram showing a memory array of a ferroelectric memory device having 2TR-2CAP type cells.

[Explanation of symbols]

WL1 to WLM word line SL selection gate line φC column selection signal φPC precharge signal φSE sense enable signal M1, N to MM, N memory cell C1, N to CM, N, C1, N 'to CM , N '... Ferroelectric capacitor (pair) STN, STN' ... Selection transistor (pair) CTN, CTN '... Precharge selection transistor (pair) PCTN, PCTN' ... Column selection transistor (pair) SAN ... Sense amplifier MBLN, MBLN '... main bit line (pair) SBLN, SBLN' ... sub-bit line (pair) VPC ... precharge voltage VN, VN '... node voltage (pair) 1 ... silicon substrate 2 ... LOCOS element isolation 3 ... gate oxide film 4 ... source / drain N + diffusion layer region 5 ... polysilicon or polycide gate electrode 6 ... under ferroelectric capacitor Electrode 7: Ferroelectric capacitor insulating film 8: Ferroelectric capacitor upper electrode 9: Interlayer insulating film 10a, 10b, 10c, 10d under first layer aluminum wiring Contact hole 11a under first layer aluminum wiring, 11b, 11c: first-layer aluminum wiring 12: interlayer insulating film under second-layer aluminum wiring 13: contact hole under second-layer aluminum wiring 14: second-layer aluminum wiring

Continuation of the front page (51) Int.Cl. 7 identification code FI H01L 27/108 29/788 29/792 (58) Investigated field (Int.Cl. 7 , DB name) H01L 27/10 451 G11C 11/22 G11C 14/00 H01L 21/8242 H01L 21/8247 H01L 27/108 H01L 29/788 H01L 29/792

Claims (12)

(57) [Claims]
1. A plurality of main bit line pairs adjacent to each other and complementary to each other and wired in a column, and a plurality of sub bit lines adjacent to each other and complementary to each other via connection means. A memory cell comprising a pair of ferroelectric capacitors complementary to each other is arranged at a lattice position where the sub-bit line pair and a plurality of word lines wired in a row cross each other. One electrode of each ferroelectric capacitor of the ferroelectric capacitor pair is connected to the corresponding sub-bit line of the sub-bit line pair, and the other electrode is connected to the word line; A ferroelectric storage device that stores either first data or second data having opposite phases by mutually polarizing the dielectric capacitors in opposite directions.
2. The connection means according to claim 1, wherein said connection means are complementary to each other.
In the S-type semiconductor element pair, one of the source electrode or the drain electrode of each MOS-type semiconductor element of the MOS-type semiconductor element pair corresponds to the corresponding main bit line of the main bit line pair;
The other one corresponds to the corresponding sub-bit line of the sub-bit line pair,
2. A ferroelectric device according to claim 1, wherein said gate electrodes are respectively connected to a selected gate line, and said main bit line pair and said sub bit line pair are operatively connected in accordance with a voltage applied to said selected gate line. Body storage.
3. The ferroelectric memory device according to claim 1, wherein each ferroelectric capacitor of said ferroelectric capacitor pair has the same size.
4. A method of writing first data to a memory cell comprises applying a voltage to one of the ferroelectric capacitor pairs in a direction in which the potential of the selected sub-bit line is higher than the potential of the selected word line. The ferroelectric capacitor is polarized in the direction of the applied electric field, and the potential of the other sub-bit line for selecting another ferroelectric capacitor of the ferroelectric capacitor pair is lower than the potential of the selected word line. By applying a voltage in a certain direction to polarize the ferroelectric capacitor in the direction of the applied electric field, the second data is written to the memory cell by writing each ferroelectric capacitor of the ferroelectric capacitor pair to the memory cell. The ferroelectric capacitor is polarized in the direction of the applied electric field by applying a voltage in a direction in which the selected sub-bit line potential is lower than the selected word line potential. A voltage is applied to the other ferroelectric capacitor of the pair of ferroelectric capacitors in a direction in which the potential of the selected sub-bit line is higher than the potential of the selected word line, and the ferroelectric capacitor is subjected to the applied electric field. 2. The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device performs polarization by polarizing in a direction.
5. Reading data from a memory cell is performed by connecting a main bit line pair to a sub-bit line pair, changing a word line voltage to be selected, and changing the polarization of each ferroelectric capacitor of the ferroelectric capacitor pair. 2. The ferroelectric memory according to claim 1, wherein the state is changed, and the data is determined by detecting a change in the potential of each main bit line according to a change in the polarization state of each of the ferroelectric capacitors as a potential difference between the main bit line pair. Dielectric storage device.
6. The ferroelectric memory device according to claim 1, wherein after the data is read from the memory cell, the data is rewritten to the memory cell.
7. A latch type sense amplifier is provided for each main bit line pair, and read data or write data is latched in the sense amplifier to write or read and rewrite data in a memory cell. 2. The ferroelectric memory device according to claim 1, wherein the step is performed collectively for all the memory cells connected to the selected word line.
8. The data is written by simultaneously applying a voltage in the same direction to both ferroelectric capacitors of the pair of ferroelectric capacitors of all memory cells connected to the selected word line. After erasing the two ferroelectric capacitors by polarizing them in the direction of the applied electric field, one of the ferroelectric capacitors of the pair of ferroelectric capacitors of the memory cell may be used in accordance with data to be written to each memory cell. 2. The ferroelectric memory device according to claim 1, wherein a voltage is applied to the ferroelectric capacitor in a direction opposite to that during the erasing, and one of the ferroelectric capacitors is polarized in the direction of the applied electric field.
9. The data writing operation is performed sequentially for each word line in units of all word lines intersecting a sub-bit line pair selected by a selected gate line.
The ferroelectric storage device according to claim 1.
10. The reading and rewriting of data is performed sequentially for each word line in units of all word lines intersecting a sub-bit line pair selected by a selected gate line. Ferroelectric storage device.
11. A plurality of main bit line pairs adjacent to each other and complementary to each other and wired in a column, and a plurality of sub bit lines adjacent to each other and complementary to each other via connection means. A memory cell comprising a pair of ferroelectric capacitors complementary to each other is arranged at a lattice position where the sub-bit line pair and a plurality of word lines wired in a row intersect with each other. In the method of manufacturing a ferroelectric memory device, one electrode of each ferroelectric capacitor of the ferroelectric capacitor pair is connected to the corresponding sub-bit line of the sub-bit line pair and the other electrode is connected to the word line. Forming a lower capacitor electrode of each memory cell by the sub-bit line pair; forming an upper ferroelectric capacitor insulating film for each memory cell; and forming an upper capacitor electrode for each memory cell. Forming a word line such that the word line is connected to the upper capacitor electrode for each memory cell; and forming the main bit line pair. A method for manufacturing a storage device.
12. The lower capacitor electrode is formed of a first layer of platinum or an oxide ceramic material, and the ferroelectric capacitor insulator is a perovskite oxide ferroelectric material or a Bi layered perovskite structure. The upper capacitor electrode is formed of a second layer of platinum or an oxide ceramic material, and the word line is formed of a first layer of aluminum or an alloy thereof or a composite film. 12. The method for manufacturing a ferroelectric memory device according to claim 11, wherein the main bit line pair is formed of a second layer of aluminum, an alloy thereof, or a composite film.
JP27595695A 1995-10-24 1995-10-24 Ferroelectric memory device and method of manufacturing the same Expired - Fee Related JP3246294B2 (en)

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