JPH11340387A - Semiconductor device, its mounting method and electronic device - Google Patents

Semiconductor device, its mounting method and electronic device

Info

Publication number
JPH11340387A
JPH11340387A JP14912198A JP14912198A JPH11340387A JP H11340387 A JPH11340387 A JP H11340387A JP 14912198 A JP14912198 A JP 14912198A JP 14912198 A JP14912198 A JP 14912198A JP H11340387 A JPH11340387 A JP H11340387A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
support
wiring board
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14912198A
Other languages
Japanese (ja)
Inventor
Hideko Ando
英子 安藤
Hiroshi Kikuchi
広 菊地
Ikuo Yoshida
育生 吉田
Toshihiko Sato
俊彦 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14912198A priority Critical patent/JPH11340387A/en
Publication of JPH11340387A publication Critical patent/JPH11340387A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent damage of a semiconductor chip which is to be caused by the fitting of a heat dissipating member. SOLUTION: In a semiconductor device having a semiconductor chip 3 mounted on a mounting surface of a wiring board 1 in a state that a circuit forming surface is made to face the mounting surface of the wiring board 1, retaining members 8 for retaining a heat dissipating member 22 fitted to the back facing the circuit forming surface of the semiconductor chip 3 are arranged. The tip parts of the retaining members 8 are protruded from the back of the semiconductor chip 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、特に、発熱量が大きい半導体チップを有する半導体
装置に適用して有効な技術に関するものである。
The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a semiconductor chip having a large heat value.

【0002】[0002]

【従来の技術】パーソナルコンピュータ等の情報処理装
置にCPU(entral rocessing nit)として組み込
まれる半導体装置は、半導体チップから発生する発熱量
が大きいため、放熱体として例えばフィン型構造の放熱
体が装着される(取り付けられる)。このフィン型構造
の放熱体は、一般的に、半導体装置を実装基板に実装し
た後、半導体装置に装着される。
The semiconductor device incorporated into the information processing apparatus, such as the Related Art Personal computer as a CPU (C entral P rocessing U nit ) , since the amount of heat generated from the semiconductor chip is large, the heat radiation member, for example fin structure as a heat radiator Is attached (attached). In general, the radiator having the fin-type structure is mounted on a semiconductor device after the semiconductor device is mounted on a mounting board.

【0003】ところで、半導体装置においては、例え
ば、工業調査会発行の電子材料[1996年、4月号、
第14頁乃至第19頁]に記載されているように、配線
基板の実装面に回路形成面を向い合わせた状態で配線基
板の実装面上にバンプ電極を介在して半導体チップが実
装され、配線基板の実装面と半導体チップの回路形成面
との間の間隙領域に樹脂が充填されたパッケージ構造を
有する半導体装置が提案されている。この半導体装置
は、半導体チップの回路形成面と向い合うその裏面が外
部に露出されているため、半導体チップの裏面に熱伝導
材を介在して放熱体を直接装着することができる。
[0003] In the semiconductor device, for example, an electronic material [April 1996, April 1996,
14 to 19], a semiconductor chip is mounted on a mounting surface of a wiring board with a bump electrode interposed therebetween with a circuit forming surface facing a mounting surface of the wiring board; There has been proposed a semiconductor device having a package structure in which a resin is filled in a gap region between a mounting surface of a wiring board and a circuit forming surface of a semiconductor chip. In this semiconductor device, since the back surface facing the circuit forming surface of the semiconductor chip is exposed to the outside, a heat radiator can be directly mounted on the back surface of the semiconductor chip via a heat conductive material.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、半導体
チップの裏面に熱伝導材を介在して放熱体を装着する
際、以下の問題が生じる。
However, when the heat radiator is mounted on the back surface of the semiconductor chip with a heat conductive material interposed therebetween, the following problems occur.

【0005】放熱体は一般的に自動装着機によって装着
されるが、半導体チップの裏面に対して傾いた状態で装
着される場合がある。また、実装基板及び配線基板の反
り等により、放熱体の装着面に対して半導体チップの裏
面が傾いている場合がある。このような場合、半導体チ
ップの裏面の周縁部に放熱体が衝突し、半導体チップに
欠け、亀裂等の損傷が生じる。
The radiator is generally mounted by an automatic mounting machine, but may be mounted in an inclined state with respect to the back surface of the semiconductor chip. Further, the back surface of the semiconductor chip may be inclined with respect to the mounting surface of the heat radiator due to warpage of the mounting board and the wiring board. In such a case, the heat radiator collides with the peripheral portion of the back surface of the semiconductor chip, and the semiconductor chip is chipped and damages such as cracks occur.

【0006】本発明の目的は、半導体チップの損傷を防
止することが可能な技術を提供することにある。
An object of the present invention is to provide a technique capable of preventing damage to a semiconductor chip.

【0007】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【0008】[0008]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。
SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【0009】配線基板の実装面に回路形成面を向い合わ
せた状態で前記配線基板の実装面上に実装された半導体
チップを有する半導体装置であって、前記半導体チップ
の回路形成面と向い合うその裏面に装着される放熱体を
支持する支持体を有し、前記支持体は、前記半導体チッ
プの裏面よりも先端部が突出している。前記支持体は、
前記半導体チップの外周囲の外側において、前記配線基
板に固定されている。前記支持体は、前記半導体チップ
の外周囲を囲む枠型形状で構成されている。
A semiconductor device having a semiconductor chip mounted on a mounting surface of the wiring board with the circuit forming surface facing the mounting surface of the wiring board, the semiconductor device facing the circuit forming surface of the semiconductor chip. The semiconductor device has a support for supporting a heat radiator mounted on the back surface, and the support has a tip end projecting from the back surface of the semiconductor chip. The support is
Outside the outer periphery of the semiconductor chip, the semiconductor chip is fixed to the wiring board. The support has a frame shape surrounding the outer periphery of the semiconductor chip.

【0010】前記支持体はストライプ型形状で構成さ
れ、このストライプ型形状の支持体は、前記半導体チッ
プの互いに向い合う二つの辺の夫々の外側に設けられて
いる。前記支持体は円柱型形状又は角柱型形状で構成さ
れ、この円柱型形状又は角柱型形状の支持体は、前記半
導体チップの外周囲を囲むようにして複数点在してい
る。上述した手段によれば、半導体チップの裏面に熱伝
導材を介在して放熱体を装着する(取り付ける)際、放熱
体は支持体に支持されるので、半導体チップの裏面の周
縁部に放熱体の装着面が激突するのを回避することがで
きる。従って、放熱体の装着による半導体チップの損傷
を防止することができる。
The support is formed in a stripe shape, and the support having the stripe shape is provided outside each of two opposing sides of the semiconductor chip. The support is formed in a columnar or prismatic shape, and a plurality of the columnar or prismatic supports are scattered around the outer periphery of the semiconductor chip. According to the above-described means, when the heat radiator is mounted (attached) with a heat conductive material interposed on the back surface of the semiconductor chip, the heat radiator is supported by the support, so the heat radiator is provided on the peripheral portion of the back surface of the semiconductor chip. It is possible to prevent the mounting surface from crashing. Therefore, it is possible to prevent the semiconductor chip from being damaged by the attachment of the heat radiator.

【0011】[0011]

【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を詳細に説明する。なお、発明の実施の形態を
説明するための全図において、同一機能を有するものは
同一符号を付け、その繰り返しの説明は省略する。
Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

【0012】(実施形態1)本実施形態では、放熱体が
装着される半導体装置に本発明を適用した例について説
明する。
(Embodiment 1) In this embodiment, an example in which the present invention is applied to a semiconductor device to which a radiator is mounted will be described.

【0013】図1は本発明の実施形態1である半導体装
置の模式平面図であり、図2は図1のA−A線に沿う模
式断面図であり、図3は図2の要部拡大模式断面図であ
る。
FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a schematic sectional view taken along line AA of FIG. 1, and FIG. It is a schematic cross section.

【0014】図1及び図2に示すように、本実施形態の
半導体装置は、配線基板1の実装面1Xに回路形成面3
Yを向い合わせた状態で配線基板1の実装面1X上に半
導体チップ3を実装した構成になっている。
As shown in FIGS. 1 and 2, the semiconductor device of this embodiment has a circuit formation surface 3 X on a mounting surface 1 X of a wiring board 1.
The semiconductor chip 3 is mounted on the mounting surface 1X of the wiring board 1 with the Ys facing each other.

【0015】配線基板1の平面形状は例えば方形状で形
成されている。配線基板1は、例えばアルミナ(Al2
3)からなるセラミック基板で構成されている。配線基板
1の実装面1Xには複数の電極1A及び複数の電極1B
が形成されている。また、配線基板1の実装面1Xと向
い合うその裏面1Yには複数の電極1Cが形成されてい
る。この電極1A、1B、1Cの夫々は、配線基板1に
形成された配線を介して電気的に接続されている。
The planar shape of the wiring board 1 is, for example, a square shape. The wiring board 1 is made of, for example, alumina (Al 2 O
It is composed of a ceramic substrate consisting of 3 ). A plurality of electrodes 1A and a plurality of electrodes 1B are provided on the mounting surface 1X of the wiring board 1.
Are formed. In addition, a plurality of electrodes 1C are formed on the back surface 1Y of the wiring board 1 facing the mounting surface 1X. Each of the electrodes 1A, 1B and 1C is electrically connected via a wiring formed on the wiring board 1.

【0016】半導体チップ3の平面形状は例えば方形状
で形成されている。半導体チップ3は、例えば単結晶珪
素からなる半導体基板及びこの半導体基板上に形成され
た配線層を主体とする構成になっている。半導体チップ
3には、例えばパーソナルコンピュータ等の情報処理装
置にCPUとして組み込まれる回路システムが構成され
ている。このような回路システムが構成された半導体チ
ップ3においては、チップから発生する発熱量が大き
い。
The planar shape of the semiconductor chip 3 is, for example, rectangular. The semiconductor chip 3 has a configuration mainly including a semiconductor substrate made of, for example, single crystal silicon and a wiring layer formed on the semiconductor substrate. The semiconductor chip 3 constitutes a circuit system incorporated as a CPU in an information processing device such as a personal computer. In the semiconductor chip 3 having such a circuit system, a large amount of heat is generated from the chip.

【0017】半導体チップ3の回路形成面3Xには複数
の電極3Aが形成されている。この複数の電極3Aの夫
々は、半導体チップ3に構成された回路システムと電気
的に接続されている。
A plurality of electrodes 3A are formed on the circuit forming surface 3X of the semiconductor chip 3. Each of the plurality of electrodes 3 </ b> A is electrically connected to a circuit system configured on the semiconductor chip 3.

【0018】配線基板1の電極1A、半導体チップ3の
電極3Aの夫々は、これらの間に介在されたバンプ電極
2によって電気的にかつ機械的に接続されている。即
ち、本実施形態の半導体チップ3は、バンプ電極2を介
在して配線基板1の実装面1Xに実装されている。バン
プ電極2は、例えば、320〜325[℃]程度の液相
線温度を有する98[wt%]Pb−2[wt%]Sn
組成の半田材で形成されている。電極1A、電極3Aの
夫々は、バンプ電極2との高い濡れ性を確保するため、
例えば、クロム(Cr)膜、ニッケル(Ni)膜、金(Au)
膜の夫々を順次積層した多層膜で構成されている。
The electrode 1A of the wiring board 1 and the electrode 3A of the semiconductor chip 3 are electrically and mechanically connected by a bump electrode 2 interposed therebetween. That is, the semiconductor chip 3 of the present embodiment is mounted on the mounting surface 1X of the wiring board 1 with the bump electrode 2 interposed. The bump electrode 2 is, for example, 98 [wt%] Pb-2 [wt%] Sn having a liquidus temperature of about 320 to 325 [° C.].
It is formed of a solder material having a composition. Each of the electrode 1A and the electrode 3A has high wettability with the bump electrode 2,
For example, chromium (Cr) film, nickel (Ni) film, gold (Au)
It is composed of a multilayer film in which each of the films is sequentially laminated.

【0019】配線基板1の実装面1Xと半導体チップ3
の回路形成面3Xとの間の間隙領域には樹脂4が充填さ
れている。樹脂4としては、例えば、シリカ充填剤、硬
化促進剤、カップリング剤等が添加されたエポキシ系の
熱硬化性樹脂を用いている。このように、配線基板1の
実装面1Xと半導体チップ3の回路形成面3Xとの間の
間隙領域に樹脂4を充填することにより、配線基板1と
半導体チップ3との熱膨張係数の差に起因するバンプ電
極2の破損を防止することができる。
The mounting surface 1X of the wiring board 1 and the semiconductor chip 3
The resin 4 is filled in a gap region between the circuit formation surface 3X and the circuit formation surface 3X. As the resin 4, for example, an epoxy-based thermosetting resin to which a silica filler, a curing accelerator, a coupling agent, and the like are added is used. As described above, by filling the gap region between the mounting surface 1X of the wiring substrate 1 and the circuit forming surface 3X of the semiconductor chip 3 with the resin 4, the difference in the thermal expansion coefficient between the wiring substrate 1 and the semiconductor chip 3 can be reduced. The resulting damage to the bump electrode 2 can be prevented.

【0020】半導体チップ3の外周囲の外側には、例え
ば抵抗素子、容量素子等の基板実装部品6が複数設けら
れている。この基板実装部品6は、配線基板1の電極1
Bに半田材5を介在して電気的にかつ機械的に接続され
ている。半田材5としては、例えば300[℃]程度の
液相線温度を有する90[wt%]Pb−10[wt
%]Sn組成の半田材を用いている。
Outside the outer periphery of the semiconductor chip 3, a plurality of substrate mounting components 6, such as a resistance element and a capacitance element, are provided. The board-mounted component 6 is used for the electrode 1 of the wiring board 1.
B is electrically and mechanically connected via a solder material 5. As the solder material 5, for example, 90 [wt%] Pb-10 [wt] having a liquidus temperature of about 300 [° C] is used.
%] A solder material having a Sn composition is used.

【0021】配線基板1の電極1Cには、外部接続用端
子として、例えば球形状のバンプ電極9が電気的にかつ
機械的に接続されている。バンプ電極9は、例えば、1
83[℃]程度の共晶温度を有する37[wt%]Pb
−63[wt%]Sn組成の半田材で形成されている。
なお、電極1B、電極1Cの夫々は、前述の電極1Aと
同様の多層膜で構成されている。
A bump electrode 9 having a spherical shape, for example, is electrically and mechanically connected to the electrode 1C of the wiring board 1 as an external connection terminal. The bump electrode 9 is, for example, 1
37 [wt%] Pb having a eutectic temperature of about 83 [° C]
It is formed of a solder material having a composition of −63 [wt%] Sn.
In addition, each of the electrode 1B and the electrode 1C is formed of the same multilayer film as the electrode 1A described above.

【0022】半導体チップ3の回路形成面3Xと向い合
うその裏面3Yは外部に露出されている。この半導体チ
ップ3の裏面3Yには、図2に示すように、熱伝導材を
介在して放熱体22が装着される。放熱体22の装着
は、半導体装置を実装基板に実装する実装プロセスにお
いて行なわれる。
The back surface 3Y of the semiconductor chip 3 facing the circuit forming surface 3X is exposed to the outside. As shown in FIG. 2, a heat radiator 22 is mounted on the back surface 3Y of the semiconductor chip 3 with a heat conductive material interposed therebetween. The mounting of the heat radiator 22 is performed in a mounting process of mounting the semiconductor device on a mounting board.

【0023】半導体チップ3の外周囲の外側には、半導
体チップ3の裏面3Yに装着される放熱体22を支持す
る支持体8が設けられている。支持体8は接着材7を介
在して配線基板1の実装面1Xに接着固定されている。
本実施形態において、支持体8は、図1に示すように、
半導体チップ3を囲むようにして配線基板1の周縁に沿
って延在する枠型形状で構成されている。接着材7とし
ては、例えば熱硬化性の樹脂からなる接着材を用いてい
る。支持体8としては、例えば配線基板1と同一材料か
らなるものを用いている。
A support 8 for supporting a radiator 22 mounted on the back surface 3Y of the semiconductor chip 3 is provided outside the outer periphery of the semiconductor chip 3. The support 8 is bonded and fixed to the mounting surface 1X of the wiring board 1 with an adhesive 7 interposed therebetween.
In the present embodiment, as shown in FIG.
It has a frame shape extending along the periphery of the wiring board 1 so as to surround the semiconductor chip 3. As the adhesive 7, for example, an adhesive made of a thermosetting resin is used. The support 8 is made of, for example, the same material as the wiring board 1.

【0024】図3に示すように、配線基板1の実装面1
Xから支持体8の先端部8Aまでの高さH1は、配線基
板1の実装面1Xから半導体チップ3の裏面3Yまでの
高さH2よりも高くなっている。即ち、支持体8の先端
部8Aは、半導体チップ3の裏面3Yよりも突出してい
る。支持体8の先端部8Aは、放熱体22を支持し易い
ように平坦な構造になっている。
As shown in FIG. 3, the mounting surface 1 of the wiring board 1
The height H1 from X to the tip 8A of the support 8 is higher than the height H2 from the mounting surface 1X of the wiring board 1 to the back surface 3Y of the semiconductor chip 3. That is, the tip 8A of the support 8 protrudes from the back surface 3Y of the semiconductor chip 3. The distal end 8A of the support 8 has a flat structure so as to easily support the radiator 22.

【0025】次に、前記半導体装置の製造方法につい
て、図4(製造方法を説明するための模式断面図)を用
いて説明する。
Next, a method for manufacturing the semiconductor device will be described with reference to FIG. 4 (a schematic cross-sectional view for explaining the manufacturing method).

【0026】まず、配線基板1の実装面1Xに形成され
た電極1Aの表面に半田転写基板を位置決めし、その
後、所定の温度で半田を溶融してバンプ電極2を形成
し、その後、転写基板のみを除去する。半田としては、
例えば、320〜325[℃]程度の液相線温度を有す
る98[wt%]Pb−2[wt%]Sn組成のものを
用いる。ここまでの工程を図4(a)に示す。
First, the solder transfer board is positioned on the surface of the electrode 1A formed on the mounting surface 1X of the wiring board 1, and then the solder is melted at a predetermined temperature to form the bump electrodes 2, and then the transfer board is formed. Remove only As solder,
For example, one having a composition of 98 [wt%] Pb-2 [wt%] Sn having a liquidus temperature of about 320 to 325 [° C.] is used. FIG. 4A shows the steps up to this point.

【0027】次に、配線基板1の実装面1Xに半導体チ
ップ3の回路形成面3Xを向い合わせた状態で、配線基
板1の実装面1X上にバンプ電極2を介在して半導体チ
ップ3を配置する。
Next, with the circuit forming surface 3X of the semiconductor chip 3 facing the mounting surface 1X of the wiring substrate 1, the semiconductor chip 3 is arranged on the mounting surface 1X of the wiring substrate 1 with the bump electrode 2 interposed therebetween. I do.

【0028】次に、バンプ電極2を溶融して、配線基板
1の電極1Aと半導体チップ3の電極3Aとを電気的に
かつ機械的に接続する。バンプ電極2の溶融は、例えば
350[℃]程度の温度雰囲気中で行う。この工程によ
り、半導体チップ3は、配線基板1の実装面1X上にバ
ンプ電極2を介在して実装される。ここまでの工程を図
4(b)に示す。
Next, the bump electrode 2 is melted to electrically and mechanically connect the electrode 1A of the wiring board 1 and the electrode 3A of the semiconductor chip 3. The melting of the bump electrode 2 is performed, for example, in an atmosphere at a temperature of about 350 [° C.]. By this step, the semiconductor chip 3 is mounted on the mounting surface 1X of the wiring board 1 with the bump electrodes 2 interposed. FIG. 4B shows the steps up to this point.

【0029】次に、配線基板1の実装面1Xに形成され
た電極1Bの表面に例えばスクリーン印刷法で半田ペー
スト材(5)を印刷する。半田ペースト材(5)として
は、例えば、300[℃]程度の液相線温度を有する9
0[wt%]Pb−10[wt%]Sn組成の半田粒子
とフラックスとを混練した半田ペースト材を用いる。
Next, a solder paste material (5) is printed on the surface of the electrode 1B formed on the mounting surface 1X of the wiring board 1 by, for example, a screen printing method. The solder paste material (5) has a liquidus temperature of about 300 ° C., for example.
A solder paste material is used in which solder particles having a composition of 0 [wt%] Pb-10 [wt%] Sn and a flux are kneaded.

【0030】次に、配線基板1の電極1B上に半田ペー
スト材(5)を介在して基板実装部品6を配置し、その
後、所定の温度で半田ペースト材(5)を溶融して配線基
板1の電極1Bと基板実装部品6とを電気的にかつ機械
的に接続する。半田ペースト材(5)の溶融は、バンプ電
極2が溶融しない温度、例えば310[℃]程度の温度
雰囲気中で行う。
Next, the board-mounted component 6 is arranged on the electrode 1B of the wiring board 1 with the solder paste material (5) interposed therebetween, and then the solder paste material (5) is melted at a predetermined temperature to form a wiring board. The first electrode 1B and the board mounted component 6 are electrically and mechanically connected. The melting of the solder paste material (5) is performed in an atmosphere at a temperature at which the bump electrode 2 does not melt, for example, at a temperature of about 310 ° C.

【0031】次に、配線基板1の実装面1Xと半導体チ
ップ3の回路形成面3Xとの間に樹脂4を充填する。樹
脂4の充填は、配線基板1の実装面1Xと半導体チップ
3の回路形成面3Xとの間に毛細管現象を利用して液状
の熱硬化性樹脂を注入し、その後、プリベーク処理及び
硬化ベーク処理を施して行う。ここまでの工程を図4
(c)に示す。
Next, a resin 4 is filled between the mounting surface 1X of the wiring board 1 and the circuit forming surface 3X of the semiconductor chip 3. The filling of the resin 4 is performed by injecting a liquid thermosetting resin by utilizing a capillary phenomenon between the mounting surface 1X of the wiring board 1 and the circuit forming surface 3X of the semiconductor chip 3, and then performing a pre-bake process and a hard-baking process. Is performed. Figure 4 shows the steps up to this point.
It is shown in (c).

【0032】次に、配線基板1の実装面1Xに接着材7
を介在して支持体8を接着固定する。接着材7として
は、例えば熱硬化性の樹脂からなる接着材を用いる。こ
こまでの工程を図4(d)に示す。
Next, an adhesive 7 is attached to the mounting surface 1X of the wiring board 1.
The support body 8 is bonded and fixed with the interposition of. As the adhesive 7, for example, an adhesive made of a thermosetting resin is used. The steps up to this point are shown in FIG.

【0033】次に、配線基板1の裏面1Yを上向きにし
た状態で、配線基板1の電極1C上に、例えば183
[℃]程度の共晶温度を有する37[wt%]Pb−6
3[wt%]Sn組成の半田ボールを供給し、その後、
所定の温度で前記半田ボールを溶融してバンプ電極9を
形成する。半田ボールの供給は、例えば、ガラスマスク
を用いたボール供給法又は吸引治具を用いたボール供給
法で行う。また、半田ボールの溶融は、半田材5が溶融
しない温度、例えば240[℃]程度の温度雰囲気中で
行う。この工程により、図1乃至図3に示す半導体装置
がほぼ完成する。
Next, with the back surface 1Y of the wiring board 1 facing upward, for example, 183
37 [wt%] Pb-6 having a eutectic temperature of about [° C]
A solder ball having a composition of 3 [wt%] Sn is supplied.
The solder balls are melted at a predetermined temperature to form the bump electrodes 9. The supply of the solder balls is performed by, for example, a ball supply method using a glass mask or a ball supply method using a suction jig. The melting of the solder balls is performed in an atmosphere at a temperature at which the solder material 5 does not melt, for example, at a temperature of about 240 ° C. By this step, the semiconductor device shown in FIGS. 1 to 3 is almost completed.

【0034】この後、半導体装置は製品として出荷され
る。製品として出荷された半導体装置は、CPUモジュ
ール等の電子装置を構成する構成部品として実装基板に
実装される。
Thereafter, the semiconductor device is shipped as a product. A semiconductor device shipped as a product is mounted on a mounting board as a component constituting an electronic device such as a CPU module.

【0035】次に、前記半導体装置の実装方法につい
て、図5乃至図7(実装方法を説明するための模式断面
図)を用いて説明する。
Next, a method of mounting the semiconductor device will be described with reference to FIGS. 5 to 7 (schematic sectional views for explaining the mounting method).

【0036】まず、図1乃至図3に示す半導体装置を準
備する。
First, the semiconductor device shown in FIGS. 1 to 3 is prepared.

【0037】次に、実装基板20の実装面上に半導体装
置を配置し、その後、所定の温度でバンプ電極9を溶融
して実装基板20の電極20Aと配線基板1の電極1C
とを電気的にかつ機械的に接続する。バンプ電極9の溶
融は、例えば240[℃]程度の温度雰囲気中で行う。
この工程により、半導体装置は実装基板20の実装面上
にバンプ電極9を介在して実装される。ここまでの工程
を図5に示す。
Next, the semiconductor device is placed on the mounting surface of the mounting substrate 20, and thereafter, the bump electrodes 9 are melted at a predetermined temperature to form the electrodes 20A of the mounting substrate 20 and the electrodes 1C of the wiring substrate 1.
Are electrically and mechanically connected to each other. The melting of the bump electrode 9 is performed, for example, in an atmosphere at a temperature of about 240 [° C.].
By this step, the semiconductor device is mounted on the mounting surface of the mounting substrate 20 with the bump electrodes 9 interposed. The steps so far are shown in FIG.

【0038】次に、半導体チップ3の裏面上に熱伝導材
21を例えばディスペンサ法によって塗布する。熱伝導
材21としては、例えば熱伝導性グリース材又は熱伝導
性コンパンド材等の粘性材を用いる。ここまでの工程を
図6に示す。
Next, a heat conductive material 21 is applied on the back surface of the semiconductor chip 3 by, for example, a dispenser method. As the heat conductive material 21, for example, a viscous material such as a heat conductive grease material or a heat conductive compound material is used. The steps so far are shown in FIG.

【0039】次に、図7に示すように、半導体チップ3
の裏面3Yに熱伝導材21を介在して例えばフィン付構
造の放熱体22を装着する。放熱体22の装着は自動装
着機によって行なわれる。放熱体22としては、配線基
板1の平面サイズよりも大きい平面サイズ、例えば45
[mm]×45[mm]の平面サイズからなるものを用
いる。この工程において、半導体チップ3の外周囲の外
側には配線基板1の実装面1Xに固定された支持体8が
設けられ、支持体8の先端部8Aは半導体チップ3の裏
面3Yよりも突出していることから、放熱体22は支持
体8に支持されるので、半導体チップ3の裏面3Yの周
縁部に放熱体22の装着面22Aが衝突するのを回避す
ることができる。なお、放熱体22には、装着面22A
の反対側に電動ファン23が取り付けられている。
Next, as shown in FIG.
A radiator 22 having, for example, a finned structure is mounted on the back surface 3Y of the substrate with a heat conductive material 21 interposed therebetween. The mounting of the radiator 22 is performed by an automatic mounting machine. The radiator 22 has a plane size larger than the plane size of the wiring board 1, for example, 45 mm.
One having a plane size of [mm] × 45 [mm] is used. In this step, a support 8 fixed to the mounting surface 1X of the wiring board 1 is provided outside the outer periphery of the semiconductor chip 3, and the tip 8A of the support 8 protrudes beyond the back surface 3Y of the semiconductor chip 3. Since the radiator 22 is supported by the support 8, it is possible to prevent the mounting surface 22 </ b> A of the radiator 22 from colliding with the peripheral edge of the back surface 3 </ b> Y of the semiconductor chip 3. The radiator 22 has a mounting surface 22A.
The electric fan 23 is attached to the opposite side.

【0040】この工程により、実装基板20の実装面に
実装された半導体装置と、支持体8に支持され、かつ半
導体チップ3の裏面3Yに熱伝導材21を介在して装着
された放熱体22とを有する電子装置が構成される。
According to this step, the semiconductor device mounted on the mounting surface of the mounting board 20 and the radiator 22 supported by the support 8 and mounted on the back surface 3Y of the semiconductor chip 3 with the heat conductive material 21 interposed therebetween. An electronic device having:

【0041】このように、本実施形態によれば、以下の
効果が得られる。
As described above, according to the present embodiment, the following effects can be obtained.

【0042】(1)配線基板1の実装面1Xに回路形成
面3Xを向い合わせた状態で配線基板1の実装面1X上
に実装された半導体チップ3を有する半導体装置であっ
て、半導体チップ3の回路形成面3Xと向い合うその裏
面3Yに装着される放熱体22を支持する支持体8を有
し、支持体8の先端部8Aは半導体チップ3の裏面3Y
よりも突出している。この構成により、半導体チップ3
の裏面3Yに熱伝導材21を介在して放熱体22を装着
する(取り付ける)際、放熱体22は支持体8に支持され
るので、半導体チップ3の裏面3Yの周縁部に放熱体2
2の装着面22Aが激突するのを回避することができ
る。この結果、放熱体22の装着による半導体チップ3
の損傷を防止することができる。
(1) A semiconductor device having a semiconductor chip 3 mounted on the mounting surface 1X of the wiring substrate 1 with the circuit forming surface 3X facing the mounting surface 1X of the wiring substrate 1, And a support 8 for supporting a heat radiator 22 mounted on the back surface 3Y of the semiconductor chip 3 opposite to the circuit forming surface 3X.
More protruding. With this configuration, the semiconductor chip 3
When the heat radiator 22 is mounted (attached) to the rear surface 3Y of the semiconductor chip 3 with the heat conductive material 21 interposed therebetween, the heat radiator 22 is supported by the support body 8, so that the heat radiator 2
The collision of the second mounting surface 22A can be avoided. As a result, the semiconductor chip 3 due to the mounting of the heat radiator 22
Damage can be prevented.

【0043】また、放熱体22の装着による半導体チッ
プ3の損傷を防止することができるので、半導体装置の
実装プロセス、換言すれば電子装置の製造プロセスにお
ける歩留まりを高めることができる。
Further, since the semiconductor chip 3 can be prevented from being damaged by the attachment of the heat radiator 22, the yield in the semiconductor device mounting process, in other words, the electronic device manufacturing process can be improved.

【0044】(2)支持体8は半導体チップ3の外周囲
の外側において、配線基板1の実装面1Xに固定されて
いる。この構成により、支持体8を介在することなく、
熱伝導材21を介在して半導体チップ3の裏面3Yに放
熱体22を装着することができるので、半導体チップ3
の裏面3Yと放熱体22の装着面22Aとの間の距離を
小さくすることができる。この結果、半導体チップ3か
ら放熱体22への伝達効率を低下させることなく、放熱
体22の装着による半導体チップ3の損傷を防止するこ
とができる。
(2) The support 8 is fixed to the mounting surface 1X of the wiring board 1 outside the outer periphery of the semiconductor chip 3. With this configuration, without the support 8 interposed,
Since the heat radiator 22 can be mounted on the back surface 3Y of the semiconductor chip 3 with the heat conductive material 21 interposed therebetween, the semiconductor chip 3
The distance between the back surface 3Y and the mounting surface 22A of the radiator 22 can be reduced. As a result, it is possible to prevent the semiconductor chip 3 from being damaged due to the attachment of the heat radiator 22 without reducing the transmission efficiency from the semiconductor chip 3 to the heat radiator 22.

【0045】なお、本実施形態では、枠型形状で支持体
8を構成した例について説明したが、図8(模式平面図)
に示すように、ストライプ型形状で支持体8を構成し、
このストライプ型形状の支持体8を半導体チップ3の互
いに向い合う二つの辺の夫々の外側に設けてもよい。こ
の場合、前述の実施形態の半導体装置に比べて、半導体
装置の平面サイズを小さくすることができる。
In this embodiment, an example in which the support 8 is formed in a frame shape has been described, but FIG. 8 (schematic plan view)
As shown in the figure, the support 8 is formed in a stripe shape,
The stripe-shaped support 8 may be provided outside each of two opposing sides of the semiconductor chip 3. In this case, the planar size of the semiconductor device can be reduced as compared with the semiconductor device of the above embodiment.

【0046】また、図9(模式平面図)に示すように、円
柱型形状で支持体8を構成し、この円柱型形状の支持体
8を半導体チップ3の外周囲の外側に複数点在させても
よい。この場合においても、前述の実施形態の半導体装
置に比べて、半導体装置の平面サイズを小さくすること
ができる。
Further, as shown in FIG. 9 (schematic plan view), the support 8 is formed in a cylindrical shape, and a plurality of the cylindrical supports 8 are provided outside the outer periphery of the semiconductor chip 3. You may. Also in this case, the planar size of the semiconductor device can be reduced as compared with the semiconductor device of the above-described embodiment.

【0047】また、図示していないが、角柱型形状で支
持体8を構成し、この角柱型形状の支持体8を半導体チ
ップ3の外周囲の外側に複数点在させてもよい。この場
合においても、前述の実施形態の半導体装置に比べて、
半導体装置の平面サイズを小さくすることができる。
Although not shown, the support 8 may have a prismatic shape, and a plurality of the prismatic supports 8 may be provided outside the outer periphery of the semiconductor chip 3. Also in this case, compared to the semiconductor device of the above-described embodiment,
The planar size of the semiconductor device can be reduced.

【0048】また、本実施形態では、支持体8として配
線基板1と同一の材料で形成されたものを用いた例につ
いて説明したが、支持体8としてはこれに限定されず、
例えばアルミニウム合金材又は樹脂からなるものを用い
てもよい。
Further, in the present embodiment, an example in which the support 8 is formed of the same material as the wiring board 1 has been described, but the support 8 is not limited thereto.
For example, a material made of an aluminum alloy material or a resin may be used.

【0049】(実施形態2)本実施形態では、マルチ・
チップ型の半導体装置に本発明を適用した例について説
明する。
(Embodiment 2) In this embodiment, a multi-
An example in which the present invention is applied to a chip-type semiconductor device will be described.

【0050】図10は本実施形態の半導体装置の模式平
面図であり、図11は図10のB−B線に沿う模式断面
図である。
FIG. 10 is a schematic plan view of the semiconductor device of the present embodiment, and FIG. 11 is a schematic cross-sectional view taken along the line BB of FIG.

【0051】図10及び図11に示すように、本実施形
態2の半導体装置は、配線基板1の実装面1Xに回路形
成面3Yを向い合わせた状態で配線基板1の実装面1X
上に四つの半導体チップ3を実装した構成になってい
る。各半導体チップ3の裏面3Yには、前述の実施形態
1の半導体装置と同様に、半導体装置を実装する実装プ
ロセスにおいて、熱伝導材を介在して放熱体が装着され
る。
As shown in FIGS. 10 and 11, the semiconductor device according to the second embodiment has the mounting surface 1X of the wiring board 1 with the circuit forming surface 3Y facing the mounting surface 1X of the wiring board 1.
The configuration is such that four semiconductor chips 3 are mounted thereon. In the mounting process of mounting the semiconductor device, a heat radiator is mounted on the back surface 3Y of each semiconductor chip 3 in the mounting process of mounting the semiconductor device, similarly to the semiconductor device of the first embodiment.

【0052】各半導体チップ3の外周囲の外側には、各
半導体チップ3の裏面3Yに装着される放熱体を支持す
る支持体8が設けられている。支持体8は接着材7を介
在して配線基板1の実装面1Xに接着固定されている。
本実施形態において、支持体8は円柱型形状で構成さ
れ、各半導体チップ3の外周囲の外側に複数点在してい
る。各支持体8は配線基板1の実装面1Xから先端部8
Aまでの高さが同一の高さになっており、各支持体8の
先端部8Aは配線基板1の実装面1Xから半導体チップ
3の裏面3Yまでの高さよりも高くなっている。
Outside the outer periphery of each semiconductor chip 3, a support 8 for supporting a heat radiator mounted on the back surface 3Y of each semiconductor chip 3 is provided. The support 8 is bonded and fixed to the mounting surface 1X of the wiring board 1 with an adhesive 7 interposed therebetween.
In the present embodiment, the supports 8 are formed in a columnar shape, and are scattered outside the outer periphery of each semiconductor chip 3. Each of the supports 8 extends from the mounting surface 1X of the wiring board 1 to the tip 8
The height to A is the same, and the tip 8A of each support 8 is higher than the height from the mounting surface 1X of the wiring board 1 to the back surface 3Y of the semiconductor chip 3.

【0053】このように構成された半導体装置において
も、前述の実施形態1と同様に、放熱体の装着による半
導体チップ3の損傷を防止することができる。また、半
導体装置の実装プロセス(電子装置の製造プロセス)にお
ける歩留まりを高めることができる。また、半導体チッ
プ3から放熱体への伝達効率を低下させることなく、放
熱体の装着による半導体チップ3の損傷を防止すること
ができる。
In the semiconductor device thus configured, similarly to the first embodiment, the semiconductor chip 3 can be prevented from being damaged by the attachment of the heat radiator. Further, the yield in the semiconductor device mounting process (electronic device manufacturing process) can be increased. Further, it is possible to prevent the semiconductor chip 3 from being damaged due to the attachment of the heat radiator without lowering the transmission efficiency from the semiconductor chip 3 to the heat radiator.

【0054】(実施形態3)本実施形態では、放熱体を
有する半導体装置に本発明を適用した例について説明す
る。図12は本発明の実施形態3である半導体装置の模
式断面図である。
Embodiment 3 In this embodiment, an example in which the present invention is applied to a semiconductor device having a heat radiator will be described. FIG. 12 is a schematic sectional view of a semiconductor device according to Embodiment 3 of the present invention.

【0055】図12に示すように、本実施形態の半導体
装置は、配線基板1の実装面1Xに回路形成面3Yを向
い合わせた状態で配線基板1の実装面1X上にバンプ電
極2を介在して半導体チップ3が実装され、半導体チッ
プ3の裏面3Yに熱伝導材21を介在して放熱体22が
装着されたパッケージ構造で構成されている。
As shown in FIG. 12, in the semiconductor device of this embodiment, the bump electrode 2 is interposed on the mounting surface 1X of the wiring board 1 with the circuit forming surface 3Y facing the mounting surface 1X of the wiring board 1. The semiconductor chip 3 is mounted, and a heat dissipation member 22 is mounted on the back surface 3Y of the semiconductor chip 3 with a heat conductive material 21 therebetween.

【0056】半導体チップ3の外周囲の外側には放熱体
22を支持する支持体8が設けられている。支持体8は
接着材7を介在して配線基板1の実装面1Xに接着固定
され、支持体8の先端部8Aは半導体チップ3の裏面3
Yよりも突出している。本実施形態の支持体8は半導体
チップ3の外周囲を囲ようにして形成された枠型形状で
構成されている。
A support 8 for supporting the heat radiator 22 is provided outside the outer periphery of the semiconductor chip 3. The support member 8 is bonded and fixed to the mounting surface 1X of the wiring board 1 with an adhesive 7 interposed therebetween.
It protrudes more than Y. The support 8 of the present embodiment has a frame shape formed so as to surround the outer periphery of the semiconductor chip 3.

【0057】本実施形態の半導体装置は前述の実施形態
1と同様の製造プロセスで形成されるが、本実施形態の
半導体装置では、製造プロセスにおいて、バンプ電極9
を形成した後、半導体チップ3の裏面3Yに熱伝導材2
1を介在して放熱体22が装着される。
The semiconductor device of this embodiment is formed by the same manufacturing process as that of the first embodiment. However, in the semiconductor device of this embodiment, the bump electrode 9 is formed in the manufacturing process.
Is formed on the back surface 3Y of the semiconductor chip 3,
The heat radiator 22 is mounted with the intermediary 1 interposed therebetween.

【0058】このように構成された半導体装置において
も前述の実施形態1と同様の効果が得られる。
The same effect as in the first embodiment can be obtained in the semiconductor device having the above-described configuration.

【0059】また、放熱体22の装着による半導体チッ
プ3の損傷を防止できるので、半導体装置の製造プロセ
スにおける歩留まりを高めることができる。
Since the semiconductor chip 3 can be prevented from being damaged by the mounting of the heat radiator 22, the yield in the semiconductor device manufacturing process can be improved.

【0060】なお、支持体8はストライプ型形状又は円
柱型形状若しくは角柱型形状で構成してもよい。
The support 8 may have a stripe shape, a column shape, or a prism shape.

【0061】(実施形態4)本実施形態では、支持体が
設けられた放熱体を有する半導体装置に本発明を適用し
た例について説明する。図13は本発明の実施形態4で
ある半導体装置の模式断面図である。
(Embodiment 4) In this embodiment, an example in which the present invention is applied to a semiconductor device having a radiator provided with a support will be described. FIG. 13 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention.

【0062】図13に示すように、本実施形態の半導体
装置は、配線基板1の実装面1Xに回路形成面3Yを向
い合わせた状態で配線基板1の実装面1X上にバンプ電
極2を介在して半導体チップ3が実装され、半導体チッ
プ3の裏面3Yに熱伝導材21を介在して放熱体22が
装着されたパッケージ構造で構成されている。
As shown in FIG. 13, in the semiconductor device of the present embodiment, the bump electrode 2 is interposed on the mounting surface 1X of the wiring board 1 with the circuit forming surface 3Y facing the mounting surface 1X of the wiring board 1. The semiconductor chip 3 is mounted, and a heat dissipation member 22 is mounted on the back surface 3Y of the semiconductor chip 3 with a heat conductive material 21 therebetween.

【0063】半導体チップ3の外周囲の外側には放熱体
22を支持する支持体8が設けられている。支持体8は
放熱体22に一体化され、放熱体22の装着面22Aか
ら支持体8の先端部8Aまでの高さH3は、配線基板1
の実装面1Xから半導体チップ3の裏面3Yまでの高さ
H2よりも高くなっている。本実施形態の支持体8は、
半導体チップ3の外周囲を囲むようにして、配線基板1
の周縁に沿って形成された枠型形状で構成されている。
A support 8 for supporting the radiator 22 is provided outside the outer periphery of the semiconductor chip 3. The support 8 is integrated with the radiator 22, and the height H3 from the mounting surface 22 </ b> A of the radiator 22 to the tip 8 </ b> A of the support 8 is equal to the height of the wiring board 1.
Is higher than the height H2 from the mounting surface 1X to the back surface 3Y of the semiconductor chip 3. The support 8 of the present embodiment includes:
The wiring board 1 is arranged so as to surround the outer periphery of the semiconductor chip 3.
Is formed along the periphery of the frame.

【0064】本実施形態の半導体装置は前述の実施形態
1と同様の製造プロセスで形成されるが、本実施形態の
半導体装置では、製造プロセスにおいて、バンプ電極9
を形成した後、半導体チップ3の裏面3Yに熱伝導材2
1を介在して放熱体22が装着される。
The semiconductor device of this embodiment is formed by the same manufacturing process as that of the first embodiment. However, in the semiconductor device of this embodiment, the bump electrodes 9 are formed in the manufacturing process.
Is formed on the back surface 3Y of the semiconductor chip 3,
The heat radiator 22 is mounted with the intermediary 1 interposed therebetween.

【0065】このように構成された半導体装置において
も前述の実施形態1と同様の効果が得られる。
The same effect as that of the first embodiment can be obtained in the semiconductor device having such a configuration.

【0066】また、放熱体22の装着による半導体チッ
プ3の損傷を防止できるので、半導体装置の製造プロセ
スにおける歩留まりを高めることができる。
Further, since the damage of the semiconductor chip 3 due to the mounting of the heat radiator 22 can be prevented, the yield in the semiconductor device manufacturing process can be increased.

【0067】なお、本実施形態では、放熱体22に支持
体8を一体化した例について説明したが、支持体8は放
熱体22の装着面22Aに接着材を介在して接着固定し
てもよい。
In this embodiment, the example in which the support 8 is integrated with the radiator 22 has been described. However, the support 8 may be fixed to the mounting surface 22A of the radiator 22 with an adhesive. Good.

【0068】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。
As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

【0069】[0069]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

【0070】放熱体の装着による半導体チップの損傷を
防止することができる。
The semiconductor chip can be prevented from being damaged by the mounting of the heat radiator.

【0071】また、半導体チップから放熱体への伝達効
率を低下させることなく、放熱体の装着による半導体チ
ップの損傷を防止することができる。
Further, it is possible to prevent the semiconductor chip from being damaged due to the attachment of the heat radiator without lowering the transmission efficiency from the semiconductor chip to the heat radiator.

【0072】また、半導体装置の実装プロセス(電子装
置の製造プロセス)における歩留まりを高めることがで
きる。
Further, the yield in the semiconductor device mounting process (electronic device manufacturing process) can be increased.

【0073】また、半導体装置の製造プロセスにおける
歩留まりを高めることができる。
Further, the yield in the semiconductor device manufacturing process can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態1である半導体装置の模式平
面図である。
FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.

【図2】図1のA−A線に沿う模式断面図である。FIG. 2 is a schematic sectional view taken along line AA of FIG.

【図3】図2の要部拡大模式断面図である。FIG. 3 is an enlarged schematic cross-sectional view of a main part of FIG. 2;

【図4】本発明の実施形態1である半導体装置の製造方
法を説明するための模式断面図である。
FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

【図5】本発明の実施形態1である半導体装置の実装方
法を説明するための模式断面図である。
FIG. 5 is a schematic cross-sectional view for explaining a method of mounting the semiconductor device according to the first embodiment of the present invention.

【図6】本発明の実施形態1である半導体装置の実装方
法を説明するための模式断面図である。
FIG. 6 is a schematic cross-sectional view for explaining a method of mounting the semiconductor device according to the first embodiment of the present invention;

【図7】本発明の実施形態1である半導体装置の実装方
法を説明するための模式断面図である。
FIG. 7 is a schematic cross-sectional view for explaining a method of mounting the semiconductor device according to the first embodiment of the present invention.

【図8】本発明の実施形態1の第一変形例である半導体
装置の模式平面図である。
FIG. 8 is a schematic plan view of a semiconductor device according to a first modification of the first embodiment of the present invention.

【図9】本発明の実施形態1の第二変形例である半導体
装置の模式平面図である。
FIG. 9 is a schematic plan view of a semiconductor device which is a second modification of the first embodiment of the present invention.

【図10】本発明の実施形態2である半導体装置の模式
平面図である。
FIG. 10 is a schematic plan view of a semiconductor device according to a second embodiment of the present invention.

【図11】図10のB−B線に沿う模式断面図である。FIG. 11 is a schematic sectional view taken along the line BB of FIG. 10;

【図12】本発明の実施形態3である半導体装置の模式
断面図である。
FIG. 12 is a schematic sectional view of a semiconductor device according to a third embodiment of the present invention.

【図13】本発明の実施形態4である半導体装置の模式
断面図である。
FIG. 13 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…配線基板、1X…実装面、1Y…裏面、1A,1
B,1C…電極、2…バンプ電極、3…半導体チップ、
3X…回路形成面、3Y…裏面、4…樹脂、5…半田
材、6…基板実装部品、7…接着材、8…支持体、9…
バンプ電極、20…実装基板、20A…電極、21…熱
伝導材、22…放熱体、23…電動ファン。
DESCRIPTION OF SYMBOLS 1 ... Wiring board, 1X ... Mounting surface, 1Y ... Back surface, 1A, 1
B, 1C ... electrode, 2 ... bump electrode, 3 ... semiconductor chip,
3X: circuit forming surface, 3Y: back surface, 4: resin, 5: solder material, 6: board mounted component, 7: adhesive material, 8: support, 9 ...
Bump electrode, 20: mounting board, 20A: electrode, 21: heat conductive material, 22: heat radiator, 23: electric fan.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 俊彦 東京都青梅市新町六丁目16番地の3 株式 会社日立製作所デバイス開発センタ内 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Toshihiko Sato 3-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】 配線基板の実装面に回路形成面を向い合
わせた状態で前記配線基板の実装面上に実装された半導
体チップを有する半導体装置であって、 前記半導体チップの回路形成面と向い合うその裏面に装
着される放熱体を支持する支持体を有し、前記支持体
は、前記半導体チップの裏面よりも先端部が突出してい
ることを特徴とする半導体装置。
1. A semiconductor device having a semiconductor chip mounted on a mounting surface of a wiring substrate with a circuit forming surface facing a mounting surface of the wiring substrate, wherein the semiconductor device faces a circuit forming surface of the semiconductor chip. A semiconductor device, comprising: a support for supporting a heat dissipating body mounted on a back surface of the semiconductor chip, wherein the support has a tip end projecting from a back surface of the semiconductor chip.
【請求項2】 配線基板の実装面に回路形成面を向い合
わせた状態で前記配線基板の実装面上に実装された半導
体チップを有し、前記半導体チップの回路形成面と向い
合うその裏面に熱伝導材を介在して放熱体が装着された
半導体装置であって、 前記放熱体を支持する支持体を有し、前記支持体は、前
記半導体チップの裏面よりも先端部が突出していること
を特徴とする半導体装置。
2. A semiconductor chip mounted on a mounting surface of the wiring board in a state where a circuit forming surface faces a mounting surface of the wiring board, and a semiconductor chip mounted on a back surface facing the circuit forming surface of the semiconductor chip. A semiconductor device having a heat radiator mounted thereon with a heat conductive material interposed therebetween, wherein the semiconductor device has a support for supporting the heat radiator, and the support has a tip protruding from a back surface of the semiconductor chip. A semiconductor device characterized by the above-mentioned.
【請求項3】 前記支持体は、前記半導体チップの外周
囲の外側において、前記配線基板に固定されていること
を特徴とする請求項1又は請求項2に記載の半導体装
置。
3. The semiconductor device according to claim 1, wherein the support is fixed to the wiring board outside an outer periphery of the semiconductor chip.
【請求項4】 配線基板の実装面に回路形成面を向い合
わせた状態で前記配線基板の実装面上に実装された半導
体チップを有し、前記半導体チップの回路形成面と向い
合うその裏面に熱伝導材を介在して放熱体が装着された
半導体装置であって、 前記放熱体を支持する支持体を有し、前記支持体は前記
放熱体に固定又は一体化され、前記放熱体の装着面から
前記支持体の先端部までの高さは、前記配線基板の実装
面から前記半導体チップの裏面までの高さよりも高くな
っていることを特徴とする半導体装置。
4. A semiconductor chip mounted on a mounting surface of the wiring board with a circuit forming surface facing a mounting surface of the wiring board, and a semiconductor chip mounted on a back surface facing the circuit forming surface of the semiconductor chip. A semiconductor device having a radiator mounted thereon with a heat conductive material interposed therebetween, comprising a support for supporting the radiator, wherein the support is fixed or integrated with the radiator and the radiator is mounted. A semiconductor device, wherein a height from a surface to a tip portion of the support is higher than a height from a mounting surface of the wiring board to a back surface of the semiconductor chip.
【請求項5】 前記支持体は、前記半導体チップの外周
囲の外側に設けられていることを特徴とする請求項4に
記載の半導体装置。
5. The semiconductor device according to claim 4, wherein the support is provided outside an outer periphery of the semiconductor chip.
【請求項6】 前記支持体は、前記半導体チップの外周
囲を囲む枠型形状で構成されていることを特徴とする請
求項1乃至請求項5のうち何れか一項に記載の半導体装
置。
6. The semiconductor device according to claim 1, wherein the support has a frame shape surrounding an outer periphery of the semiconductor chip.
【請求項7】 前記支持体は、ストライプ型形状で構成
され、このストライプ型形状の支持体は、前記半導体チ
ップの互いに向い合う二つの辺の夫々の外側に設けられ
ていることを特徴とする請求項1乃至請求項5のうち何
れか一項に記載の半導体装置。
7. The semiconductor device according to claim 1, wherein the support is formed in a stripe shape, and the support having the stripe shape is provided outside each of two opposing sides of the semiconductor chip. The semiconductor device according to claim 1.
【請求項8】 前記支持体は、円柱型形状又は角柱型形
状で構成され、この円柱型形状又は角柱型形状の支持体
は、前記半導体チップの外周囲を囲むようにして複数点
在していることを特徴とする請求項1乃至請求項5のう
ち何れか一項に記載の半導体装置。
8. The support member is formed in a columnar shape or a prismatic shape, and a plurality of the cylindrical or prismatic supports are scattered around the outer periphery of the semiconductor chip. The semiconductor device according to claim 1, wherein:
【請求項9】 前記半導体チップは、バンプ電極を介在
して前記配線基板の実装面に実装されていることを特徴
とする請求項1乃至請求項8のうち何れか一項に記載の
半導体装置。
9. The semiconductor device according to claim 1, wherein the semiconductor chip is mounted on a mounting surface of the wiring board via a bump electrode. .
【請求項10】 配線基板の実装面に回路形成面を向い
合わせた状態で前記配線基板の実装面上に実装された半
導体チップと、前記半導体チップの回路形成面と向い合
うその裏面よりも先端部が突出し、前記半導体チップの
外周囲の外側において前記配線基板に固定された支持体
とを有する半導体装置を準備し、 前記半導体装置を実装基板に実装した後、前記半導体チ
ップの裏面に熱伝導材を介在して放熱体を装着すること
を特徴とする半導体装置の実装方法。
10. A semiconductor chip mounted on a mounting surface of the wiring board with the circuit forming surface facing the mounting surface of the wiring board, and a tip end of a back surface facing the circuit forming surface of the semiconductor chip. Preparing a semiconductor device having a portion protruding and a support fixed to the wiring substrate outside the outer periphery of the semiconductor chip; and mounting the semiconductor device on a mounting substrate, and then conducting heat conduction to the back surface of the semiconductor chip. A method for mounting a semiconductor device, comprising: mounting a heat radiator with a material interposed therebetween.
【請求項11】 配線基板の実装面に回路形成面を向い
合わせた状態で前記配線基板の実装面上に半導体チップ
が実装された半導体装置と、前記半導体チップの回路形
成面と向い合うその裏面に熱伝導材を介在して装着され
た放熱体とを有し、 前記半導体装置は実装基板の実装面上に実装され、 放熱体は前記配線基板の実装面に固定された支持体に支
持され、 前記支持体は半導体チップの裏面よりも先端部が突出し
ていることを特徴とする電子装置。
11. A semiconductor device having a semiconductor chip mounted on a mounting surface of the wiring board with the circuit forming surface facing the mounting surface of the wiring board, and a back surface facing the circuit forming surface of the semiconductor chip. A semiconductor device is mounted on the mounting surface of the mounting board, and the heat radiator is supported by a support fixed to the mounting surface of the wiring board. An electronic device, wherein the support has a tip protruding from the back surface of the semiconductor chip.
【請求項12】 配線基板の実装面に回路形成面を向い
合わせた状態で前記配線基板の実装面に半導体チップが
実装された半導体装置と、前記半導体チップの回路形成
面と向い合うその裏面に熱伝導材を介在して装着された
放熱体とを有し、 前記半導体装置は実装基板の実装面に実装され、 前記放熱体は前記半導体チップの裏面と向い合う装着面
に支持体を有し、 前記放熱体の装着面から前記支持体の先端部までの高さ
は、前記配線基板の実装面から前記半導体チップの裏面
までの高さよりも高くなっていることを特徴とする電子
装置。
12. A semiconductor device having a semiconductor chip mounted on a mounting surface of the wiring board in a state where the circuit forming surface faces the mounting surface of the wiring substrate, and a semiconductor device having a back surface facing the circuit forming surface of the semiconductor chip. A radiator mounted with a heat conductive material interposed therebetween, wherein the semiconductor device is mounted on a mounting surface of a mounting substrate, and the radiator has a support on a mounting surface facing the back surface of the semiconductor chip. An electronic device, wherein a height from a mounting surface of the heat radiator to a tip portion of the support is higher than a height from a mounting surface of the wiring board to a back surface of the semiconductor chip.
JP14912198A 1998-05-29 1998-05-29 Semiconductor device, its mounting method and electronic device Pending JPH11340387A (en)

Priority Applications (1)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100708045B1 (en) * 2001-09-05 2007-04-16 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its manufacturing method
KR100779345B1 (en) * 2001-08-17 2007-11-23 앰코 테크놀로지 코리아 주식회사 Semiconductor package
JP2007324334A (en) * 2006-05-31 2007-12-13 Toshiba Corp Heat-conductive grease and electronic apparatus
JP2015165545A (en) * 2014-02-28 2015-09-17 板橋精機株式会社 Power module and manufacturing method therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100779345B1 (en) * 2001-08-17 2007-11-23 앰코 테크놀로지 코리아 주식회사 Semiconductor package
KR100708045B1 (en) * 2001-09-05 2007-04-16 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its manufacturing method
JP2007324334A (en) * 2006-05-31 2007-12-13 Toshiba Corp Heat-conductive grease and electronic apparatus
JP2015165545A (en) * 2014-02-28 2015-09-17 板橋精機株式会社 Power module and manufacturing method therefor

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