JPH11338768A - Method and device for memory control and recording medium for the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To equally interleave respective memory modules by selecting memory interfaces equally by the layers of an interleave hierarchy and equally selecting two memory modules connected to the memory interface of the bottom layer. SOLUTION: A main memory 3 has memory modules 41-48 and is connected to a system controller 2 through memory interfaces 7 respectively. Two other memory interfaces 7 to be interleaved are connected under memory interface control to form the interleave hierachy as a path through which a processor 1 accesses the memory modules 4. The memory interfaces 7 are selected equally, layer by layer, from the top layer to the bottom layer and the two memory modules 4 connected to the memory interface 7 of the bottom layer are equally selected to determine a memory module 4 to be accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method for interleaving access to a storage device from a processor, a memory control device for executing the memory control method, and a program for causing a computer system to execute the memory control method. It relates to a recorded recording medium.

[0002]

2. Description of the Related Art In recent computer systems, control called interleaving is performed in order to make the memory access speed close to the processing speed of a high-speed processor. Interleaving divides a storage area into a plurality of areas called banks, allows each bank to operate independently in parallel, and reads / writes data simultaneously or alternately, thereby lowering the processing speed of the system at the time of memory access. It is a method of suppressing.

[0003] By the way, in recent years, computer systems have been downsized and opened up, and functions different from those of mainframes conventionally used have been demanded. One of such functions is to make it possible to mix and mount memory elements having different storage capacities and different numbers of internal banks. The internal bank is a bank included in a memory element itself such as a DRAM or an SRAM.

[0004]

When interleaving is performed on a storage device in which memory elements having different storage capacities and different numbers of internal banks coexist, the conventional memory control method uses the storage capacity and the memory capacity among the mounted memory elements. Since the interleaving is performed according to the memory element having the smallest number of internal banks, there is a problem that the storage capacity is wasted.

In recent years, the speed of improvement in the degree of integration of memory elements has been tremendous. When a user attempts to add a memory, a memory element having twice or four times the storage capacity of the originally mounted memory element becomes mainstream. Sometimes. In such a case, if the memory element originally mounted is removed and a memory element having a large storage capacity is newly mounted, the memory element originally mounted becomes useless, and this places a heavy burden on the user.

Therefore, in order to solve such a problem,
For example, in Japanese Patent Application Laid-Open No. Hei 6-309223, a bank is divided into blocks of a fixed size, and the mounting state of a memory is stored in a configuration register for each block. Then, when an address to be accessed by the processor is specified, the configuration register is referred to and the address is converted according to the mounting state of the memory, so that interleaving can be performed even when the memory is expanded by one bank. The technology is described.

However, in the technique described in Japanese Patent Application Laid-Open No. 6-309223, only the storage capacity of a DRAM unit and information of a bank number obtained by having a plurality of DRAMs are held, so that a DRAM having an internal bank is provided. It is difficult to carry out interleaving when the device is mounted.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and performs even interleaving even when memory elements having different storage capacities and different numbers of internal banks coexist. It is an object of the present invention to provide a memory control method and a memory control device that can perform the above.

[0009]

According to a first aspect of the present invention, there is provided a memory control method for interleaving a storage device capable of mounting a plurality of memory modules each including at least one memory element from a processor. A memory control method, comprising a plurality of memory interfaces that are interfaces for accessing the memory module, and connecting two other memory interfaces to be interleaved under the memory interface, thereby enabling the processor Forming an interleave layer serving as a path for accessing the memory module, and selecting the memory interface equally for each layer from the highest layer to the lowest layer of the interleave layer; Inn It said processor by selecting evenly two memory modules connected to the face is a method of determining the memory module to be accessed.

At this time, of the memory modules,
A storage capacity equal to the smallest memory module is defined as a unit, and a storage capacity obtained by dividing the storage capacity by the number of memory modules capable of mounting the unit is defined as a block. When a value given as an initial value is set as the number of allocated blocks, it is determined whether a memory module having a storage area remaining is connected to a subordinate memory interface for each of the interleaving layers, and If a memory module having a storage area remaining on both sides is connected, the number of allocated blocks of the corresponding memory module is set to 2
When a memory module having a storage area remaining in only one of the memory interfaces is connected, the number of blocks allocated to the corresponding memory module is held as it is, and the number is calculated for each memory module. Blocks equal to the number of allocated blocks
The unit is configured by allocating each of the memory modules, and the processor may access the storage device for each unit, and among the bits of the line address designated by the processor, the unused bits are not used. The memory interface and the memory module may be respectively selected from the upper layer to the lower layer of the interleave layer by using the least significant bit in order.

In addition, the number of internal banks of the memory module is written as a bank control table for each memory module, and it is determined whether or not a storage area remains in the memory module by referring to the bank control table. In addition, a bit indicating the bank number of the memory element to be accessed by the processor may be found from the line address, and the bit numbers of the row address and the column address of the memory element are written as an address bit position table, and the address bit position is written. By referring to the table, bits indicating the row address and the column address of the memory element to be accessed by the processor may be found from the line addresses.

Further, the memory module may be composed of one or two sides. When m is an integer of 0 or more, the memory element has 2 ^m internal banks. Is also good.

On the other hand, a memory control device of the present invention is a memory control device for allowing a processor to access a storage device capable of mounting a plurality of memory modules each including at least one memory element in an interleaved manner. A plurality of memory interfaces that are interfaces for accessing the memory module. By connecting two other memory interfaces to be interleaved under the memory interface, an interleave becomes a path for accessing the memory module from the processor. Forming a hierarchy, from the highest hierarchy to the lowest hierarchy of the interleaving hierarchy,
A system control device that determines the memory module to be accessed by the processor by equally selecting the memory interface for each hierarchy and equally selecting two memory modules connected to the lowermost memory interface Have

At this time, of the memory modules,
A storage capacity equal to the smallest memory module is defined as a unit, and a storage capacity obtained by dividing the storage capacity by the number of memory modules capable of mounting the unit is defined as a block. When the value given as the initial value is the number of allocated blocks, the system control device determines, for each of the interleaving layers, whether or not a memory module whose storage area remains in the subordinate memory interface is connected. If a memory module having a storage area remaining is connected to both of the memory interfaces, the number of allocated blocks of the corresponding memory module is divided by 2, and the storage area is stored only in one of the memory interfaces. If the remaining memory module is connected In this case, the unit is configured by retaining the number of blocks allocated to the corresponding memory module as it is, and allocating the same number of blocks from each memory module as the number of allocated blocks calculated for each memory module. The processor may access the storage device for each of the units, and the system control device sequentially uses the least-significant bit that is not used among the bits of the line address designated by the processor. Then, the memory interfaces may be selected and the memory modules may be selected from the upper layer to the lower layer of the interleave layer.

Further, the system control device refers to the bank control table in which the number of internal banks of the memory module is written for each memory module and the bank control table, and stores a storage area in the memory module. A number discriminator for judging whether or not a memory element remains, and for finding out a bit indicating a bank number of a memory element to be accessed by a processor from the line address. With reference to the address bit position table in which the bit numbers of the row address and column address of the element are written, respectively, and referring to the address bit position table, the row address and the column address of the memory element to be accessed by the processor from the line addresses. Showing And address discrimination unit to find the door,
May be provided.

Further, the memory module may be composed of one or two sides. When m is an integer of 0 or more, the memory element has 2 ^m internal banks. Is also good.

In the memory control method and the memory control device as described above, an interleave hierarchy is formed by connecting two other memory interfaces to be interleaved under the memory interface, and the interleave hierarchy is formed from the highest level to the lowest level. Toward the lower layer, the memory interface is evenly selected for each layer, and the two memory modules connected to the lowest layer memory interface are equally selected, so that the memory modules are evenly interleaved. Is performed.

Also, it is determined whether or not a memory module having a storage area remaining in a subordinate memory interface is connected to each of the interleaving layers, and a memory module having a storage area remaining in both memory interfaces is checked. Is connected, the number of allocated blocks of the corresponding memory module is divided by 2, and if a memory module having a storage area remaining in only one of the memory interfaces is connected, the corresponding memory module is connected. The number of allocated blocks is held as it is, and the number of blocks equal to the number of allocated blocks calculated for each memory module is allocated from each memory module to form a unit. Access to the memory It is possible to install additional child in units, it is possible to perform uniform interleaving even if memory modules having different memory capacities.

Further, by referring to the bank control table, a bit indicating the bank number of the memory element to be accessed by the processor can be specified from the vacant state of the storage area of the memory module and the line address. By referring to the position table,
Since the bits indicating the row address and the column address of the memory element accessed by the processor can be specified from the line address, the storage areas of all the memory modules can be used effectively.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a computer system that executes the memory control method of the present invention. FIG. 2 is a block diagram showing another example of the configuration of a computer system that executes the memory control method of the present invention. FIG.

As shown in FIG. 1, the computer system controls a processor 1 for performing arithmetic processing, a main memory 3 for storing information necessary for processing by the processor 1, and an access from the processor 1 to the main memory 3. A system control device 2, an input device for inputting information and instructions to the processor 1, an output device for outputting a processing result of the processor, and the like, and a main memory 3. And a recording medium 6 on which a program for performing the program is recorded.

The processor 1 reads programs and data stored in the recording medium 6 into the main memory 3 and executes an interleave process described below according to the programs stored in the main memory 3. Note that the recording medium 6 may be a magnetic disk, a semiconductor memory, a CD-ROM, or other recording means.

The main memory 3 includes a plurality of memory modules.
Has a (FIG. 1, the first memory module 4 _{1 to} eighth memory module 4 ₈₎ is connected to the system control unit 2 via the memory interface 7, respectively (slot and connection wiring for inserting a memory module, etc.) ing. Each memory interface 7 can be connected to two memory modules.

Incidentally, one memory interface 7
When the memory interface 7 is occupied by the memory access request from the processor 1 to one of the two memory modules connected to the memory module, the memory access request to the other memory module ends the preceding memory access processing. You will have to wait.

However, if the memory interface 7 occupied by the preceding memory access request is different from the memory interface 7 occupied by the subsequent memory access request, the subsequent memory access request does not have to wait. That is, interleaving between two memory modules having different memory interfaces 7 can perform memory access processing at a higher speed than performing interleaving between two memory modules that commonly use the memory interface 7.

Each memory module is not only directly connected to the system controller 2 as shown in FIG.
Memory interface unit as shown in Figure 2: there may be connected via a (LSI and circuit for the relay such Figure the 2 first memory interface unit ₈₁ and the second memory interface unit _82). In such a configuration, it is desirable to use the two memory interface units equally. This is because, if the two memory interface units are not used equally, the memory access cannot be performed equally to all the memory modules connected to them.

By the way, in the computer system shown in FIGS. 1 and 2, it can be considered that the system controller 2 and each memory module are connected by a plurality of layers of memory interfaces. Such a hierarchical structure is called an interleaved hierarchy. Although FIG. 2 shows a configuration in which the memory interface unit has only one layer, the memory interface unit may have a plurality of layers. As described above, when accessing a memory module via such an interleave layer, a memory interface unit or a memory interface unit is provided for each layer from an upper layer closer to the system controller 2 to a lower layer closer to the memory module. Are desirably used equally.

Therefore, in order to use the memory interfaces evenly, the number of memory interfaces that can be connected to the memory interface unit is preferably 2 ⁿ (n is an integer of 0 or more). Similarly, in order to uniformly access the memory modules, the number of memory modules connectable to the memory interface is set to 2 ⁿ (n
Is an integer of 0 or more). When the interleaving is performed only from the upper layer to the predetermined intermediate layer, it is not necessary to reduce the number of memory interfaces in the lower layer where the interleaving is not performed to ²ⁿ . When interleaving is not performed between memory modules, the number of memory modules connected to the memory interface does not need to be ²ⁿ .

By the way, as described above, each memory module has a plurality of internal banks. The number of internal banks is determined by a memory element of the memory module, for example, S
Number of internal banks ( ²ⁿ :
n is an integer of 1 or more) and the number of SDRAMs connected in parallel in the address direction in the memory module. Generally, the number of internal banks of an SDRAM is 2
The number of internal banks in a memory module (Single Sided memory module) in which only one SDRAM is connected in the address direction is either two banks or four banks, and two SDRAMs are provided in the address direction. Connected memory module (Double
The number of internal banks of the sided memory module) is four or eight.

On the other hand, since the memory access unit is generally the same as the caching size (hereinafter, referred to as a line size) of the processor, it is not accessed at one time over a plurality of memory modules.

For example, assuming that memory access is performed in 64-bit units, the address at that time is represented by A [63:
0], the line (cache management unit,
Here, an address (hereinafter, referred to as a line address) for designating a storage area to be accessed is, for example, A
[63: 6]. In this case, which memory interface unit is used to access the main memory 3 is determined by A [63: 6], and A [5: 0] is irrelevant.

It should be noted, memory interface connected to the system controller is referred to as a first memory interface 9 ₁ and the second memory interface 9 ₂ shown in FIG. 2, is connected to the first memory interface unit 8 ₁ called memory interface and the third memory interface 9, _third and fourth memory interface 9 _4, the second memory interface unit ₈₂ a memory interface connected to the fifth memory interface 9 ₅
And referred to as a memory interface _{9 6} sixth.

[0034] At this time, in order to use the memory interfaces evenly is used interchangeably first memory interface 9 ₁ and the ₂ second memory interface 9, further third memory interface 9 ₃ and the fourth the memory interface 9 _4, or the memory interface 9 ₅ of the fifth and a memory interface 9 ₆ 6 may be used alternately.

When the total capacity of the memory modules under the _first memory interface 91 is equal to the total capacity of the memory modules under the _second memory interface 92, the least significant bit (A [6]) of the line address selecting one by the value of the first memory interface 9 ₁ or second memory interface 9 _2.
Similarly, the total capacity of the memory modules under the _third memory interface 93 and the fourth memory interface 9
If the total capacity of the memory modules under the _fourth line is equal, the second bit (A
[7]) third the value of the memory interface _{9 3}
Or selecting one of the fourth memory interface 9 _4.

Further, the fifth memory interface 9₅
Total capacity of subordinate memory modules and sixth memory in
Face 9₆The total capacity of the subordinate memory modules
If they are equal, the value of A [7] of the line address
5 memory interface 9 ₅Or the sixth memory in
Face 9₆Select one of

[0037] However, if the total capacity of the total capacity and the second memory interface 9 ₂ subordinate memory module of the first memory interface 9 ₁ under memory modules are different, the first memory interface 9
Total capacity and the second memory interface 9 also total amount of ₂ under the memory module equals the total capacity of the third memory interface 9 ₃ subordinate memory modules and the fourth memory interface 9 ₄ under the ₁ under memory module If differs the total capacity of the memory module is, or if the total capacity and is different from the fifth memory interface 9 total amount of ₅ under the memory module of the sixth memory interface 9 ₆ memory modules under the the Only uses two bits in the line address, two memory interface units 8
_{1, 8 2} can not be used equally.

In the memory control method of the present invention, first, among the mounted memory modules, the storage capacity of the memory module having the smallest storage capacity is defined as a unit capacity.
The entire storage area of the main memory 3 is divided into a plurality of unit capacities (the unit capacities are hereinafter referred to as units). Then, a unit number of 0 origin is assigned to each unit in ascending order of the address number. Further, the storage capacity of each unit is divided by the maximum number of memory modules that can be mounted (hereinafter, the divided storage capacity is referred to as a block), and a block number of 0 origin is assigned to each block in ascending order of the address number. I will do it.

For example, if a maximum of eight memory modules can be mounted and the memory capacity of the smallest memory module among the mounted memory modules is 256 MB, one unit is 256 MB and one block Is 32 MB. In addition, when a maximum of 16 memory modules can be mounted, and the storage capacity of the memory module having the smallest storage capacity among the mounted memory modules is 1 GB, one unit is 1 GB and one block is 64 MB. Become.

When more than two memory interfaces are connected to a certain hierarchy (however,
^m : m is an integer of 2 or more), and the hierarchy is virtually divided so that the number of memory interfaces becomes two. For example, in the configuration of FIG. 1, since the number of memory interfaces connected to the system control device 2 is 4, the space between the system control device 2 and the memory module is divided into two layers each having two memory interfaces.

That is, assuming that interleaving is performed between two memory modules connected to the same memory interface, in the highest interleaving hierarchy,
A first memory interface 9 ₁ and the second memory interface 9 ₂ performs interleaving between the third memory interface 9, _third and fourth memory interface 9 _4, at its lower interleave hierarchy, first memory interface _{9 1} and the second between the memory interface _{9 2} or the third memory interface _{9 3,}
Performing interleaving between the fourth memory interface 9 _4. Further, in the lowest interleaving hierarchy, interleaving is performed between two memory modules connected to the same memory interface. FIG. 3 shows such an interleave hierarchy in an easy-to-understand manner.

FIG. 3 is a block diagram showing an example of the configuration of an interleave hierarchy of a computer system that executes the memory control method of the present invention. Referring to FIG. 3, the interleave layer is composed of three layers, a first layer, a second layer, and a third layer, in order from the highest layer. Here, the objects to be interleaved are referred to as members, and the other is referred to as a partner when viewed from one of the two members in the same interleaving hierarchy. Also, two members of a partner are collectively called a group. In the example of FIG.
The first memory module and the second memory module are in the same group in the third hierarchy. A first memory module and a second memory module;
And the fourth memory module are the same group in the second hierarchy.

For such an interleaved hierarchy, the memory control method of the present invention executes the following processing.

First, each member (memory module) of the lowest hierarchy has a variable called the number of allocated blocks. Here, the initial value of the number of allocated blocks of the member having the remaining storage area is the maximum mountable member number, and the initial value of the allocated block number of the member having no remaining storage area is “0”.

Next, it is checked whether or not a storage area remains in both members under each layer, and if a storage area remains in both members, the number of allocated blocks is divided by "2". If the storage area remains in only one member, no processing is performed. By repeating this up to the lowest hierarchy, the number of blocks to be allocated to each member of the lowest hierarchy where the storage area remains is calculated.

Here, it can be seen that the total number of blocks allocated to each member is equal to the maximum number of mountable members, and the total storage capacity is equal to the storage capacity of the unit.
That is, in the memory control method of the present invention, the main memory 3 is accessed for each unit, and each unit is configured by a block (a value equal to the number of allocated blocks) allocated from each memory module.

Then, at the time of memory access, it is checked in order from the upper layer whether or not a storage area remains in both subordinate members. If a storage area remains in both members, the line address is not used. The member to be accessed is determined by the value of the lower bit.

According to the above rules, the most effective interleaving can be realized even when memory modules having different storage capacities and different numbers of internal banks coexist.

When the memory control method of the present invention is actually performed, a table including entries corresponding to each unit is prepared, and information on the installed memory modules is stored in each entry in advance. Then, the storage capacity and the number of internal banks of each memory module constituting the unit are obtained by referring to the table, and the memory module number and the bank number to be accessed are determined (described in detail in the embodiment).

Next, using the computer system shown in FIG. 4 as an example, the above-described memory control method of the present invention will be described more specifically.

FIG. 4 is a block diagram showing an example of the configuration of a computer system in which a maximum of eight memory modules can be mounted on the main memory. In the computer system shown in FIG. 4, the second memory module, the seventh memory module, and the eighth memory module are not mounted,
The mounted first memory module and the third to sixth memory modules have different storage capacities and different numbers of internal banks. Note that the total storage capacity of the mounted memory modules is 2
Since the capacity of the memory module having the smallest storage capacity among the mounted memory modules is 256 MB, the storage area of 2 GB is divided into eight 256 MB units.

Here, the address "000000000000"
000000 ”to“ 000000000ffffff ”
“f” is a storage area of the unit number “0”, and has addresses “000000000001000000” to “000000”.
“0001ffffffff” is a storage area of the unit number “1”. Hereinafter, similarly, the address “000000”
0000000000 ”to“ 000000007fff
Unit numbers are assigned to the storage area of ffff ″ (unit number “7”).

Since a maximum of eight memory modules can be mounted in the main memory, the value obtained by dividing the storage capacity of the unit (256 MB) by 8, that is, 32 MB is the storage capacity of the block.

In the configuration shown in FIG. 4, the storage capacity under the first memory interface unit and the storage capacity under the second memory interface unit are the same, each being 1 GB. Furthermore, the total storage capacity of the first memory module and the second memory module (not mounted) and the storage capacity of the third memory module and the fourth memory module are the same, each of which is 512 MB.
It is.

In such a configuration, in order to use the first memory interface unit and the second memory interface unit equally, the line address A
Using the value of [6], for example, if A [6] is “0”, the first memory interface unit is selected and A
When [6] is "1", the second memory interface unit is selected.

In order to use the two memory interfaces under the first memory interface unit equally, the value of A [7] of the line address is used, for example, when A [7: 6] is "00". In this case, a memory interface connected to the first memory module and the second memory module (not mounted) is selected, and A [7: 6] is set to “10”.
In the case of (1), a memory interface connected to the third memory module and the fourth memory module is selected. At this time, since the second memory module is not mounted,
Only the first memory module is selected. Further, since the third memory module and the fourth memory module are respectively mounted, one of the two memory modules is selected according to the value of A [8] of the line address.

On the other hand, the seventh memory module and the eighth memory module under the second memory interface unit are not mounted. Therefore, when A [6] of the line address is “1”, a memory interface connected to the fifth memory module and the sixth memory module is selected. At this time, one of the two memory modules is selected according to the value of the line address A [7].

On the other hand, when the number of internal banks of each memory module is different, the bank number to be accessed is specified by the bit immediately above the bit of the line address used to specify the memory module.

For example, since the fourth memory module is selected when A [8: 6] of the line address is "110", its bank number is specified using two bits of A [10: 9]. . Since the fifth memory module is selected when A [7: 6] of the line address is “01”, its bank number is specified using three bits of A [10: 8].

The contents described above will be described once again by applying the above-described interleaving rule.

In FIG. 4, there are two lower layers when viewed from the two memory interface units. Also,
Since up to eight memory modules can be mounted in the computer system shown in FIG. 4, the initial number of blocks allocated to the first memory module, the third memory module, the fourth memory module to the sixth memory module is initialized. The values are respectively “8”, and the initial values of the numbers of allocated blocks of the second memory module, the seventh memory module, and the eighth memory module are respectively “0”.

Since there are memory modules under both of the two memory interfaces connected to the system controller, the number of allocated blocks is divided by two. Therefore, at this time, the number of blocks allocated to the first memory module, the third memory module, the fourth memory module to the sixth memory module is “4”, and the second memory module, the seventh memory module, The number of blocks assigned to each of the module and the eighth memory module is “0”.

Next, since each memory interface under the first memory interface unit has a memory module, the number of blocks to be allocated is further divided by "2". Therefore, at this time, the number of blocks allocated to the first memory module, the third memory module, and the fourth memory module is “2”, and the number of blocks allocated to the second memory module is “0”.

On the other hand, since the two memory interfaces under the second memory interface unit have only one memory interface, the number of blocks allocated to the fifth memory module and the sixth memory module is “4”. ".

Subsequently, in the lowest layer, since the second memory module is not mounted, the number of blocks assigned to the first memory module is "2" as it is. Further, since the third memory module and the fourth memory module are respectively mounted, the number of blocks allocated to the third memory module and the fourth memory module is further divided by “2” to “1”. Become.

Similarly, the fifth memory module and the sixth memory module
Of the fifth memory module and the sixth memory module are further divided by “2” to “2”.

That is, finally, the number of blocks allocated to the first to eighth memory modules is “2”, “0”, “1”, “1”, “2”,
"2", "0", and "0". Therefore, in order to configure one unit (256 MB), 64 MB (two blocks) is allocated from each of the first memory module, the fifth memory module, and the sixth memory module, and the third memory module, 32 MB (one block) is allocated from each of the fourth memory modules.

Therefore, even when memory modules having different storage capacities or different numbers of internal banks are mounted, or even when an arbitrary memory module is not mounted, interleaving is performed using the maximum number of banks obtained from all mounted storage areas. It can be carried out.

The memory interface connecting the system controller and the main memory may have a bus structure, and the main memory may be directly connected to a processor or an IO device.

[0070]

Next, an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 5 is a block diagram showing the configuration of a first embodiment of the system control device shown in FIG.
FIG. 6 is a block diagram showing a configuration example of the main memory shown in FIG. FIG. 7 is a table showing an example of the configuration of the BCT shown in FIG. 5, and FIG.
It is a table figure showing an example of 1 composition of PT.

In FIG. 5, the system control device 2 includes an initial setting information section 30 for obtaining initial setting values of a bank control table and an address bit position table, which will be described later, from information of a memory module mounted on the main memory 3. , A register 10 for temporarily holding a line address sent from the processor 1, and a bank control table (hereinafter referred to as a bank control table) for storing the storage capacity and the number of internal banks of a memory module or a memory element (for example, DRAM) of the main memory 3. , BCT) 11, a first address decoder 17 for searching the number of internal banks stored in the BCT 11, a write address sent from the processor 1 to the BCT 11 at the time of initialization, or a BC
A first selector 16 for validating any one of the line addresses transmitted to T11 and outputting to the first address decoder 17 and a read / write selector signal for switching the first selector 16 are temporarily held. A first read / write selector signal register 20;
, A first write address register 21 for temporarily storing a write enable signal for the BCT 11, a first write enable register 22 for temporarily storing a write enable signal for the BCT 11, and a first write register for temporarily storing information to be written to the BCT 11. Write data register 23 and B
The main memory 3 includes a number discriminator 12 for discriminating a card number, a stack number, a memory module number, a side number, a bank number, and the like to be accessed from the data stored in the CT 11 and the line address sent from the processor. Memory device (for example, DRAM)
An address bit position table (hereinafter referred to as ABPT) 13 for storing the number of address bits of each row address and column address, a second address decoder 19 for searching the number of address bits stored in the ABPT 13, A second selector which validates either the write address of the number of address bits transmitted from the processor 1 at the time of setting or the discrimination result transmitted from the number discriminating unit 12 at the time of memory access and outputs it to the second address decoder 19. 18 and a second read / write selector signal register 24 for temporarily holding a read / write selector signal for switching the second selector 18.
A second write address register 25 for temporarily storing a write address for the ABPT 13;
13, a second write enable register 26 for temporarily storing a write enable signal for ABPT1.
3, a second write data register 27 for temporarily holding information to be written, a row address and a column for accessing the main memory 3 from the number of address bits stored in the ABPT 13 and a line address sent from the processor 1. Address discriminator 14 for discriminating addresses
And the determined mounting addresses (card number, stack number, memory module number, side number, bank number, row address and column address designating bits in the DRAM) corresponding to each internal bank. Address buffer 15 and mounting address buffer 15
And a main memory output arbitration unit 29 for creating a selection condition for the third selector 28. Note that the processor 1 performs the BC control according to the initialization program recorded in the initialization information section 30.
Initial settings of T11 and ABPT13 are respectively performed.

In FIG. 6, the main memory 3 is composed of two cards, for example, a first card 31 and a second card 32, and the first card 31 and the second card 32 are different from each other. Four memory modules (first memory module 311 to fourth memory module 314 for first card 31 and fifth memory module 321 to eighth memory module 324 for second card) can be mounted.

Here, the 4 card mounted on the first card 31
Of the two memory modules, the two memory modules (the first memory module 311 and the second memory module 312) on the left side of the figure are referred to as a first left stack 315, and the two memory modules on the right side of the figure are The memory modules (the third memory module 313 and the fourth memory module 314) are transferred to the first write stack 316.
Call. Similarly, of the four memory modules mounted on the second card 32, the two memory modules (the fifth memory module 321 and the sixth memory module 322) on the left side in FIG. The two memory modules (the seventh memory module 323 and the eighth memory module 324) on the right side in FIG. 6 are referred to as a left stack 325 and a second right stack 326.
Call. The main memory shown in FIG. 6 can have different storage capacities and different numbers of internal banks for each memory module.

In FIG. 7, the BCT 11 is composed of a plurality of entries consisting of 2-bit data, ie, 16-bit data, respectively corresponding to eight memory modules.

Here, 2 corresponding to each memory module
Each bit data indicates the number of internal banks of the memory module (for example, “00”: no mounting, “0”
1 ": Internal bank number 2," 10 ": Internal bank number 4," 11 ": Internal bank number 8).

That is, the bit (15-1) of each entry
4) indicates the number of internal banks of the first memory module 311. Bits (13-12) indicate the number of internal banks of the second memory module 312. The bit (1
1-10) indicates the number of internal banks of the third memory module 313, and bits (9-8) indicate the number of internal banks of the fourth memory module 314. Bit (7-6) indicates the number of internal banks of the fifth memory module 321 and bit (5-4) indicates the number of internal banks of the sixth memory module 322. Further, bit (3-2) indicates the number of internal banks of the seventh memory module 323, and bit (2-1) indicates the number of internal banks of the eighth memory module 324.

Therefore, by referring to each entry of the BCT 11, it is possible to determine the presence / absence of a free storage area of a memory module necessary for each unit and the number of internal banks.

The number of entries in the BCT 11 is as follows.
At least (maximum storage capacity / unit) (for example, when the maximum storage capacity is 2 GB and the unit is 256 MB, the number of entries is 8).

Further, in this embodiment, an example is shown in which the storage capacity of each memory module and the number of internal banks are stored in the BCT 11, but the BCT 11 stores information on the side of each memory module (Single Sided Memory Module). Or Double Sided memory module)
May also be stored together. In this case, the number of internal banks of the memory element is stored instead of the number of internal banks of the memory module.

In FIG. 8, the number of address bits of each memory module stored in the ABPT 13 differs depending on the storage capacity and the type of the mounted memory element. Generally, the number of bits of a row address is 10 to 13, and the number of bits of a column address is generally 10 to 13. The number of bits is 8-11.

Each entry of the ABPT 13 has 2 bits (00: bit number 10, 0) indicating the number of bits of the row address.
1: Bit number 11, 10: Bit number 12, 11: Bit number 13) and 2 bits indicating the bit number of the column address (00: Bit number 8, 01: Bit number 9, 10: Bit number 10, 11: The number of bits is 11). Here, bit (3-2) indicates the row address, and bit (1-0) indicates the number of bits of the column address.

In the example shown in FIG. 8, the first
The entries No. to Eighth respectively show the bit numbers of the row address and the column address of the first memory module to the eighth memory module.

Each entry of the ABPT 13 is referred to by the card number, stack number, memory module number, and bank number of the memory module to be accessed, which is determined by the number determining unit 12.

Next, a method of initializing the BCT 11 will be described with reference to FIGS.

FIG. 9 is a schematic diagram showing a specific configuration example of the main memory shown in FIG. 6, and FIG. 10 is a table showing the configuration of the BCT corresponding to the main memory shown in FIG. Note that the main memory shown in FIG. 9 shows a configuration in which each memory module has the same storage capacity and a different number of internal banks. The storage capacity of the unit is 2
56 MB (each entry of BCT11 is 256 MB
), And the storage capacity of the block is 32 MB.

At the time of initialization, the processor 1 first obtains mounting memory information for each memory module,
Write to the initial setting information section 30. Here, the mounted memory information is, for example, the storage capacity of each memory module and the number of internal banks.

Subsequently, the processor 1 sets the write enable signal to "1". At this time, the first selector 16
Validates the write address sent from the processor 1 according to the select signal. In this state, the processor 1 reads the number of internal banks of each memory module from the initial setting information section 30, and writes initial data to the BCT 11.

As described above, assuming that the storage capacity of the unit is 256 MB, it is necessary to secure a 128 MB storage area from each of the two cards in order to perform interleaving between the two cards equally. Further, in order to perform interleaving evenly between the stacks, it is necessary to secure a storage area of 64 MB from each of the two stacks. Furthermore, in order to perform interleaving evenly between the memory modules, it is necessary to secure a storage area of 32 MB from each of the two memory modules. That is, one entry is created by securing a storage area in units of 32 MB from each of the eight memory modules.

As shown in FIG. 9, if the number of internal banks of the first memory module is 4, the data of bits (15-14) of BCT11 is "10". Also,
Assuming that the number of internal banks of the second memory module is 2, the data of the bit (13-12) of BCT11 is "01". Similarly, the eighth memory module (BC
One entry is created by writing data up to the bit (1-0) of T11.

Subsequently, the storage capacity used to create this one entry is subtracted from each memory module.
By repeating the same processing until the storage capacity of each memory module becomes zero, the BCT 11 as shown in FIG. 10 is created.

Since the BCT 11 is regarded as having no memory mounted on each memory module when the total storage capacity of the main memory (for example, 2 GB) is exceeded, all subsequent entries contain "00". Written.

Next, the memory interleaving method after the initialization of the BCT 11 will be described.

When a line address is received from the processor 1, the received line address is temporarily stored in the register 10. The first address decoder 17 outputs the bit (34-2) of the line address stored in the register 10.
8) and BCT based on the decoded result
Search for 11. Here, since the storage capacity of the unit is 256 MB (one entry is 256 MB), the bit (27-0) is used as data of the unit.

The first selector 16 validates the write address at the time of initial setting and validates the line address at the time of normal memory access, according to the select signal from the processor.

The number discriminating section 12 determines the card number, stack number, memory module number, side number, and bank number of the memory module to be accessed based on the 16-bit data and the line address read by searching the BCT 11. And so on.

Hereinafter, a method of determining these numbers will be described with reference to the flowchart of FIG. FIG. 11 is a flowchart showing a processing procedure of the number discriminating unit shown in FIG. In the following description, the bit address (34-28) of the line address is “000100” and the fourth entry of the BCT is read. The data of the read entry is “10011110”.
01110110 ", and the value of the bit (10-5) of the line address is" 101101 "(bit (4-0) is not used because memory access is performed in units of 32 bytes).

In FIG. 11, the number discriminating section 12 first judges whether or not there are two cards in which a memory module is mounted in the main memory 3 (step S).
1).

In step S1, the logical sum of bits (15-8) of the data read by searching the BCT 11 is calculated, and if "1", there is a first card on which a memory module is mounted. Is determined. Also, the logical sum of bits (8-0) is calculated, and if "1", it is determined that there is a second card on which a memory module is mounted.
Here, since the logical sum of the bit (15-8) and the bit (8-0) is “1”, it can be seen that the memory module is mounted on both the first card and the second card.

The card number to be accessed is determined by the value of A [6] of the line address.
Is "1", access is made to card number 1 (second card) (step S2).

Next, the number judging section 12 judges whether or not there are two stacks on which the memory modules are mounted.
(Step S3).

In step S3, the logical sum of bits (7-4) of the data read by searching the BCT 11 is calculated, and if "1", it is determined that there is a left stack on which a memory module is mounted. I do. Also, the logical sum of the bits (3-0) is calculated, and if "1", it is determined that there is a write stack in which the memory module is mounted.

The stack number to be accessed is determined by the value of the least significant bit of the line address that is not used. Here, since the corresponding A [7] is “0”,
Access stack number 0 (left stack of the second card) (step S4).

Next, the number determination section 12 determines whether or not two memory modules are mounted on each stack (step S5).

In step S5, of the data read by searching the BCT 11, the logical sum of the bits (7-6) is calculated, and if "1", it is determined that one memory module is mounted. . Bit (5-4)
Is calculated, and if "1", it is determined that the other memory module is mounted (step S5).

The memory module number to be accessed is determined based on the value of the least significant bit of the line address that is not used. Here, since the corresponding A [8] is “1”, the memory module number 1 (the sixth memory module of the second card / left stack) is accessed (step S6).

Next, the number determination section 12 determines whether or not there are memory elements on two sides (Side) of each memory module (step S7).

In this embodiment, since the side information is not stored in the BCT 11, no determination is made here. The side number to be accessed is determined based on the value of the least significant bit of the line address that is not used (step S).
8) However, in this embodiment, since the side information is not specified by the line address, no determination is made here.

Next, the number determining section 12 determines the internal bank number of the memory module (step S9).

In step S9, since the bit (5-4) of the data read by searching the BCT11 is "11", the number of internal banks of the sixth memory module of the second card is eight. It is determined that there is.

The bank number to be accessed is determined by the value of at least one bit including the least significant bit of the line address that is not used (steps S10 to S12). Here, since the number of internal banks is 8, the bank number to be accessed is determined by three bits (10-8) of the line address, and the value is "101", so the bank number is 5. Therefore, it is determined that the area to be accessed is the internal bank of bank number 5 of the second card, the second left stack, and the sixth memory module.

Next, a method of initializing the ABPT 13 will be described.

At the time of initialization, the processor 1 first obtains information of the mounting memory from the main memory 3 for each memory module. Here, the information of the mounted memory is the storage capacity and type of the memory module mounted in the main memory 3. The number of bits of the row address and the column address stored in the ABPT 13 differs depending on the storage capacity and type of the memory element included in the memory module. Generally, the number of bits of the row address is 10 to 13 and the number of bits of the column address is 8-11.

Subsequently, when the processor 1 sets the write enable signal to 1, the second selector 18 validates the write address from the processor 1 according to the select signal. At this time, the write data, that is, the bit numbers of the row address and the column address are stored in the ABPT 13 for each memory module.

The address discriminator 14 decodes the card number, the stack number, the memory module number, the side number, the bank number, and the like discriminated by the number discriminator 12, and searches the ABPT 13.

The 4-bit information read by referring to the ABPT 13, the line address received from the processor 1, and the card number, stack number, memory module number, side number, A row address and a column address to be accessed are determined based on the bank number.

Next, a method of determining a row address and a column address will be described with reference to FIG. FIG. 12 is a flowchart illustrating a processing procedure of the address determination unit illustrated in FIG. In the following, the card number, stack number, memory module number,
In addition to the example used to determine the side number and the bank number, data “0100” is stored in the entry of the ABPT 13 corresponding to the memory module number 1 (sixth memory module) of the left stack of the second card 32. The case where the data has been written will be described as an example.

First, the address discriminating unit 14 checks how many bits of the line address are used to designate a card number, a stack number, a memory module number, and a bank number.

In this embodiment, since the number of cards is 2, the number of stacks is 2, the number of memory modules is 2, and the number of internal banks is 8, the bit (10-5) of the line address is used.
Use That is, the most significant bit used to indicate the card number, stack number, memory module number, and bank number is the tenth bit of the line address.

Next, the address discriminator 14 determines the ABPT 13 based on the card number, stack number, memory module number, and bank number determined by the number discriminator 12.
And obtain the number of bits of the column address. (Step S13).

The column address to be accessed includes the least significant bit of the line address which is not used.
It is determined by 11 bits (step S14 to step S1).
7). In this embodiment, since the bit (1-0) of the corresponding entry of the ABPT 13 is "00", the number of bits of the column address is 8. Therefore, "0" is set in the bit (18-11) of the line address and the upper three bits.
The column address is obtained by adding. This is because the mounting address to be sent to the main memory 3 is secured as a column address for 11 bits.

Next, the address discriminator 14 determines the ABPT 13 based on the card number, stack number, memory module number, and bank number discriminated by the number discriminator 12.
To obtain the bit number of the row address. (Step S18).

The row address to be accessed includes the least significant bit not used in the line address.
Discrimination is performed using 13 bits (steps S19 to S2)
2). In this embodiment, since the bit (3-2) of the corresponding entry of the ABPT 13 is "01", the number of bits of the row address is 11. Therefore, "0" is set in the bit (29-19) of the line address and its upper two bits.
Is the row address. This is because the mounting address sent to the main memory has 13 bits as a row address.

Next, the obtained mounting address is stored in the mounting address buffer 15 for each card number, stack number, memory module number, and bank number. The mounting address buffer 15 has a maximum number of internal banks of the main memory 3, that is, 64 in this case.
It has a buffer for storing data for each unit.

One of the mounting addresses stored in the mounting address buffer 15 is selected by the third selector 28 according to the arbitration of the main memory output arbitration unit 29, and is sent to the main memory 3.

The main memory output arbitration unit 29 performs arbitration by, for example, the Round Robin method. in this way
By using the Round Robin method, memory accesses do not concentrate on the same bank, so that effective interleaving is performed.

Therefore, BCT11 and ABPT13
, All memory modules can be used effectively, so that even if there are memory modules having different numbers of internal banks, interleaving can be performed.

Furthermore, since each entry of the BCT 11 is created with the same storage capacity, even if there are memory modules having different storage capacities, uniform interleaving can be performed.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 13 is a schematic diagram showing another specific configuration example of the main memory, and FIG. 14 is a table diagram showing a configuration of the BCT corresponding to the main memory shown in FIG.

The main memory of this embodiment has the same storage capacity of the card and the stack, although the storage capacity of each memory module and the number of internal banks are different. The storage capacity of the unit is the first
The size is 256 MB as in the embodiment.

As described in the first embodiment, when the storage capacity of the unit is 256 MB, in order to configure each entry of the BCT, it is necessary to secure a storage area of 128 MB from each card and 64 MB from each stack. There is.

In this embodiment, as shown in FIG.
Since only the first memory module is mounted on the left stack of this card, a storage area of 64 MB (for two blocks) is secured from the first memory module. Since two memory modules are mounted on the write stack, a storage area of 32 MB (for one block) is secured from each.

On the other hand, since no memory module is mounted on the left stack of the second card, a storage area cannot be secured from the left stack of the second card. However, since two memory modules are mounted on the write stack, 64M
A storage area for B (two blocks) is secured. One entry of the BCT is created by securing a storage area from each of the memory modules mounted as described above.

As in the first embodiment, the storage capacity used to create one entry is subtracted from each memory module, and this is repeated until the storage capacity of each memory module becomes zero. A BCT as shown in FIG. 14 is created. In the BCT, it is considered that no memory module is mounted in any memory module when the total storage capacity of the main memory exceeds 2 GB, so that “00” is written in all subsequent entries.

Therefore, when there is a memory module that is not mounted, each entry of the BCT is created so as not to access the memory module that is not mounted.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 15 is a block diagram showing another configuration example of the system control device shown in FIG.

This embodiment includes a diagnostic unit 40 in which the same data and initial setting program as the initial setting information section used in the first and second embodiments are recorded. Set the initial value of the address bit position table. The other configuration is the same as that of the first embodiment, and a description thereof will be omitted.

At the time of initial setting, the diagnostic unit 40 acquires mounted memory information for each memory module, similarly to the processor of the first embodiment. Here, the mounting memory information is
The storage capacity and the number of internal banks of each memory module are the same as in the first embodiment.

Subsequently, the diagnostic unit 40 creates BCT and ABPT based on the acquired mounting memory information.

Thereafter, the processor 1 performs the same processing as in the first embodiment by referring to the created BCT and ABPT, and determines the row address and the column address of the memory module to be accessed.

Therefore, the same effects as in the first embodiment can be obtained by creating the BCT and the ABPT by the diagnostic unit 40 in the same manner as in the first embodiment.

[0144]

Since the present invention is configured as described above, the following effects can be obtained.

From the highest level of the interleave level to the lowest level, a memory interface is uniformly selected for each level, and two memory modules connected to the lowest level memory interface are equally selected. Thus, uniform interleaving can be performed on each memory module.

[0146] For each layer of the interleave layer, it is confirmed whether or not a memory module having a storage area remaining in a subordinate memory interface is connected, and a memory module having a storage area remaining in both memory interfaces is checked. Is connected, the number of allocated blocks of the corresponding memory module is divided by 2, and if a memory module having a storage area remaining in only one of the memory interfaces is connected, the corresponding memory module is connected. The number of allocated blocks is held as it is, and the number of blocks equal to the number of allocated blocks calculated for each memory module is allocated from each memory module to form a unit. Access to the memory It is possible to install additional child in units, it is possible to perform uniform interleaving even if memory modules having different memory capacities.

Therefore, even when memory modules with different storage capacities or different numbers of internal banks are mounted, or when any memory module is not mounted,
Interleaving can be performed with the maximum number of banks obtained from all mounted storage areas.

Further, by referring to the bank control table, a bit indicating the bank number of the memory element to be accessed by the processor can be specified from the empty state of the storage area of the memory module and the line address. By referring to the position table,
Since the bits indicating the row address and the column address of the memory element accessed by the processor can be specified from the line address, the storage areas of all the memory modules can be used effectively. Therefore, the memory element originally mounted when adding the memory element is not wasted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a computer system that executes a memory control method according to the present invention.

FIG. 2 is a block diagram illustrating another configuration example of a computer system that executes the memory control method of the present invention.

FIG. 3 is a block diagram showing a configuration example of an interleave hierarchy of a computer system that executes a memory control method of the present invention.

FIG. 4 is a block diagram illustrating a configuration example of a computer system in which a maximum of eight memory modules can be mounted on a main memory.

FIG. 5 is a block diagram showing a configuration of a first example of the system control device shown in FIG. 1;

FIG. 6 is a block diagram illustrating a configuration example of a main memory illustrated in FIG. 1;

FIG. 7 is a table showing an example of the configuration of the BCT shown in FIG. 5;

FIG. 8 is a table diagram showing a configuration example of the ABPT shown in FIG. 5;

FIG. 9 is a schematic diagram showing a specific configuration example of a main memory shown in FIG. 6;

FIG. 10 is a BCT corresponding to the main memory shown in FIG. 9;
FIG. 3 is a table diagram showing the configuration of FIG.

11 is a flowchart illustrating a processing procedure of a number discriminating unit illustrated in FIG. 5;

FIG. 12 is a flowchart illustrating a processing procedure of an address determination unit illustrated in FIG. 5;

FIG. 13 is a schematic diagram showing another specific configuration example of the main memory.

FIG. 14 shows a BC corresponding to the main memory shown in FIG.
FIG. 3 is a table showing a configuration of T.

FIG. 15 is a block diagram illustrating another configuration example of the system control device illustrated in FIG. 1;

[Explanation of symbols]

1 processor 2 system controller 3 main memory 4 _1, 311 a first memory module 4 _2, 312 second memory module 4 _3, 313 third memory module 4 _4, 314 the fourth memory module 4 _5, 321 second memory modules 4 ₆ 5, 322 sixth memory module 4 _7, 323 seventh memory module 4 _8, 324 eighth memory module 5 IO 6 recording medium 7 memory interface unit 8 ₁ first memory interface unit 8 ₂ 2nd memory interface unit 9 ₁ 1st memory interface 9 ₂ 2nd memory interface 9 ₃ 3rd memory interface 9 ₄ 4th memory interface 9 ₅ 5th memory interface 9 ₆ 6th memory interface 10 Register 11 BCT 12 Number discriminator 13 ABPT 14 Address discriminator 15 Mounting address buffer 16 First selector 17 First address decoder 18 Second selector 19 Second address decoder 20 First read / write selector signal register 21 First 1 write address register 22 first write enable register 23 first write data register 20 second read / write selector signal register 25 second write address register 26 second write enable register 27 second write data register 28 Second selector 29 Main memory output arbitration unit 30 Initial setting information unit 31 First card 32 Second card 40 Diagnostic unit 315 First left stack 316 First right stack 325 Second left Tack 326 Second Light Stack

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[Procedure amendment]

[Submission date] April 12, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

6. A memory control device for causing a processor to access a storage device on which a plurality of memory modules including at least one memory element can be mounted in an interleaved manner, and an interface for accessing the memory module. A plurality of memory interfaces, and two other memory interfaces to be interleaved are connected under the memory interface to form an interleave hierarchy serving as a path for accessing the memory module from the processor; , From the highest hierarchy to the lowest hierarchy, the memory interface is equally selected for each hierarchy, and the two memory modules connected to the memory interface of the lowest hierarchy are equally selected. A memory controller having a system controller for determining a memory module to be accessed by the processor.

7. A memory module having a storage capacity equal to the smallest memory module among the memory modules, and a storage capacity obtained by dividing the memory module by the number of memory modules capable of mounting the unit as a block. When the value given as the initial value is the number of memory modules that can be mounted for each of the blocks, the system control device determines that the storage area remains in the subordinate memory interface for each of the interleaved layers Check whether any memory module is connected or not, and if a memory module with a remaining storage area is connected to both memory interfaces, divide the number of allocated blocks of the corresponding memory module by 2 Storage space in only one of the memory interfaces If the memory module with the remaining area is connected,
The unit is configured by holding the number of allocated blocks of the corresponding memory module as it is and assigning the same number of blocks as the number of allocated blocks calculated for each memory module from each memory module. 7. The memory control device according to claim 6 , wherein a processor accesses the storage device for each unit.

Wherein said system controller is out of the bit line address specified by the processor, using the least significant bits not used in order,
Wherein the memory controller according to claim 6 or 7, wherein selecting the memory modules with the upper layer of interleaved hierarchy towards the lower layer respectively selecting the memory interface.

Wherein said system controller includes a bank control table number internal bank is written into each memory module the memory module has, with reference to the bank control table storage area in the memory module any of claims 6-8 having a number determination unit to find the bit indicating the bank number of the memory device to be accessed by the processor from among said line address with determining whether there remains 1
The memory control device according to claim 1.

Wherein said system controller, said address bit position table number of bits row and column addresses are written respectively in the memory device, by referring to the address bit position table, from among the line address The memory control device according to any one of claims 6 to 9 , further comprising: an address determining unit that finds out a bit indicating a row address and a column address of a memory element accessed by the processor.

11. A memory module comprising at least one memory device into a plurality mountable storage device, a recording medium on which a program for executing a memory control method for accessing an interleaved from the processor to a computer system is recorded It comprises a plurality of memory interfaces which are interfaces for accessing the memory module, and connects two other memory interfaces to be interleaved under the memory interface, thereby allowing the processor to execute the memory module. Forming an interleave layer that serves as a path for accessing the memory interface. From the highest layer to the lowest layer of the interleave layer, the memory interface is uniformly selected for each layer, and A recording medium in which a program for determining a memory module to be accessed by the processor by equally selecting two memory modules connected to a memory interface is recorded.

12. Of the memory module, the storage capacity is a unit equal storage capacity with minimal memory module, the memory capacity by dividing the unit memory the number of modules that can be implemented as a block, the memory modules implemented When the value given as the initial value is the number of memory modules that can be mounted for each of the interleaved layers, the memory module whose storage area remains in the subordinate memory interface is connected to each of the interleaved layers. If a memory module having a storage area remaining is connected to both of the memory interfaces, the number of allocated blocks of the corresponding memory module is divided by two, and one of the memory interfaces Memory memory that only has a storage area If you Yuru is connected,
The unit is configured by holding the number of allocated blocks of the corresponding memory module as it is and assigning the same number of blocks as the number of allocated blocks calculated for each memory module from each memory module. A program for causing a processor to access the storage device for each unit is recorded.
12. The recording medium according to item 11 .

13. Of the bit line address specified by the processor, using the least significant bits not used in order, with each selecting the memory interface toward the lower hierarchy from the upper layer of the interleaving hierarchy recording medium for a program is recorded according to claim 11 or 12, wherein for selecting the memory module.

14. The number of internal banks of the memory module is written as a bank control table for each memory module, and it is determined whether or not a storage area remains in the memory module by referring to the bank control table. recording medium program according to any one of claims 11 to 13 is recorded for finding a bit indicating the bank number of the memory device to be accessed by the processor from among said line address with.

15. The row of the writing as a memory row address and a column, respectively the address bit position table the number of bits of the address of the device, a memory device to be accessed by the processor from among said line address by referring to the address bit position table recording medium according to any one of claims 11 to 14 program is recorded for finding a bit indicating an address and a column address.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Deleted

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Deleted

Claims (21)

[Claims] 1. A memory control method for interleaving access from a processor to a storage device on which a plurality of memory modules including at least one memory element can be mounted, wherein the interface is an interface for accessing the memory module. A plurality of memory interfaces, and two other memory interfaces to be interleaved are connected under the memory interface to form an interleave hierarchy serving as a path for accessing the memory module from the processor; From the highest level to the lowest level, the memory interface is equally selected for each layer, and the two memory modules connected to the lowest level memory interface are equally selected. Memory control method for determining a memory module which the processor accesses in. 2. A memory module having a storage capacity equal to the smallest memory module among the memory modules, and a storage capacity obtained by dividing the memory module by the number of memory modules capable of mounting the unit as a block. When the value given as the initial value is the number of memory modules that can be mounted for each of the interleaved layers, the memory module whose storage area remains in the subordinate memory interface is connected to each of the interleaved layers. If a memory module having a storage area remaining is connected to both of the memory interfaces, the number of allocated blocks of the corresponding memory module is divided by two, and one of the memory interfaces Memory module that has a storage area only If Lumpur is connected,
The unit is configured by holding the number of allocated blocks of the corresponding memory module as it is and assigning the same number of blocks as the number of allocated blocks calculated for each memory module from each memory module. 2. The memory control method according to claim 1, wherein the processor accesses the storage device for each unit. 3. The memory interface is selected from an upper layer to a lower layer of the interleave layer by using the least significant bits of the line address designated by the processor in order from the least significant bit. 3. The memory control method according to claim 1, wherein the memory module is selected. 4. The number of internal banks of the memory module is written as a bank control table for each memory module, and it is determined whether or not a storage area remains in the memory module by referring to the bank control table. 4. The memory control method according to claim 1, wherein a bit indicating a bank number of a memory element accessed by a processor is found out of the line address. 5. The row number of a memory element to be accessed by a processor from the line address by writing the number of bits of a row address and a column address of the memory element as an address bit position table and referring to the address bit position table. 5. The memory control method according to claim 1, wherein bits indicating an address and a column address are found. 6. The memory control method according to claim 1, wherein the memory module has one or two sides. 7. The memory control method according to claim 1, wherein, when m is an integer equal to or greater than 0, the memory element has 2 ^m internal banks. 8. A memory control device for causing a processor to access a storage device on which a plurality of memory modules each including at least one memory element can be mounted in an interleaved manner, and is an interface for accessing the memory module. A plurality of memory interfaces, and two other memory interfaces to be interleaved are connected under the memory interface to form an interleave hierarchy serving as a path for accessing the memory module from the processor; , From the highest hierarchy to the lowest hierarchy, the memory interface is equally selected for each hierarchy, and the two memory modules connected to the memory interface of the lowest hierarchy are equally selected. Memory controller having a system controller for determining the memory module which the processor accesses between. 9. A memory module having a storage capacity equal to the smallest memory module among the memory modules as a unit, and a storage capacity obtained by dividing the memory module by the number of memory modules capable of mounting the unit as a block. When the value given as the initial value is the number of memory modules that can be mounted for each of the blocks, the system control device determines that the storage area remains in the subordinate memory interface for each of the interleaved layers Check whether any memory module is connected or not, and if a memory module with a remaining storage area is connected to both memory interfaces, divide the number of allocated blocks of the corresponding memory module by 2 Storage space in only one of the memory interfaces If the memory module is left is connected,
The unit is configured by retaining the number of allocated blocks of the corresponding memory module as it is and allocating the same number of blocks as the number of allocated blocks calculated for each memory module from each memory module. 9. The memory control device according to claim 8, wherein a processor accesses the storage device for each unit. 10. The system control device according to claim 1, further comprising: using a least significant bit that is not used among the bits of the line address designated by the processor.
The memory control device according to claim 8, wherein the memory interface is selected while selecting the memory interface from a higher hierarchy to a lower hierarchy of the interleave hierarchy. 11. The system control device according to claim 1, further comprising: a bank control table in which the number of internal banks of the memory module is written for each memory module; and a memory area in the memory module with reference to the bank control table. The memory control according to any one of claims 8 to 10, further comprising: a number determination unit that determines whether or not there is a remaining address and finds a bit indicating a bank number of a memory element accessed by a processor from the line address. apparatus. 12. The system controller refers to an address bit position table in which the bit numbers of a row address and a column address of the memory element are written, respectively, and refers to the address bit position table. 12. An address discriminator for finding a bit indicating a row address and a column address of a memory element accessed by a processor.
The memory control device according to claim 1. 13. The memory control device according to claim 8, wherein the memory module has one or two sides. 14. The memory control device according to claim 8, wherein when m is an integer equal to or greater than 0, the memory element has 2 ^m internal banks. 15. A recording medium storing a program for causing a computer system to execute a memory control method for interleaving access from a processor to a storage device capable of mounting a plurality of memory modules including at least one memory element. It comprises a plurality of memory interfaces which are interfaces for accessing the memory module, and connects two other memory interfaces to be interleaved under the memory interface, thereby allowing the processor to execute the memory module. Forming an interleave layer that serves as a path for accessing the memory interface. From the highest layer to the lowest layer of the interleave layer, the memory interface is uniformly selected for each layer, and Recording medium on which a program is recorded for the processor by selecting evenly two memory modules connected to the memory interface determines a memory module to be accessed. 16. The memory module mounted as a unit, wherein the memory module has a storage capacity equal to the smallest memory module among the memory modules, and a storage capacity divided by the number of memory modules capable of mounting the unit is a block. When the value given as the initial value is the number of memory modules that can be mounted for each of the interleaved layers, the memory module whose storage area remains in the subordinate memory interface is connected to each of the interleaved layers. If a memory module having a storage area remaining is connected to both of the memory interfaces, the number of allocated blocks of the corresponding memory module is divided by two, and one of the memory interfaces Memory memory that only has a storage area If you Yuru is connected,
The unit is configured by holding the number of allocated blocks of the corresponding memory module as it is and assigning the same number of blocks as the number of allocated blocks calculated for each memory module from each memory module. 16. The recording medium according to claim 15, wherein a program for causing a processor to access the storage device for each unit is recorded. 17. A method for selecting the memory interface from an upper layer to a lower layer of the interleave layer by sequentially using a least significant bit among unused bits of a line address specified by the processor. 17. The recording medium according to claim 15, wherein a program for selecting the memory module is recorded. 18. The number of internal banks of the memory module is written as a bank control table for each memory module, and it is determined whether or not a storage area remains in the memory module by referring to the bank control table. 18. The recording medium according to claim 15, wherein a program for finding a bit indicating a bank number of a memory element accessed by a processor from the line address is recorded. 19. The row number of the memory element accessed by a processor from the line address by writing the number of bits of the row address and the column address of the memory element as an address bit position table and referring to the address bit position table. 19. The recording medium according to claim 15, wherein a program for finding a bit indicating an address and a column address is recorded. 20. The recording medium according to claim 15, wherein the memory module has one or two sides. 21. The recording medium according to claim 15, wherein, when m is an integer equal to or greater than 0, the memory element has 2 ^m internal banks.