JPH11330950A - Logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the logic circuit which may have a small charging and discharging current, for example, even when one of input signals is 1 or 0 for a relatively long period and the other vibrates in certain short cycles. SOLUTION: The logic circuit is provided with input terminals 1 and 2 for signals A and B. The input terminal 1 is connected to a node 15 through an N channel transistor(TR) 4 and the input terminal 2 is connected to the gate of an N channel TR 5 through the gate of the TR 4 and a NOT circuit 13. The drain of the TR 5 is connected to the node 15 and the source is connected to a ground level 9. The signal state of the node 15 is outputted directly from an output terminal 11 and also outputted from an output terminal 10 through a NOT circuit 6. The output of the NOT circuit 6 is connected to the gate of a P channel TR 7, the source of the TR 7 is connected to a source voltage 8, and the drain is connected to the node 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic circuit used for digital signal processing.

[0002]

2. Description of the Related Art FIG. 26 is a circuit diagram of a conventional two-input NAND circuit. Two signals are input from the input terminals 71 and 72 to a logical NOT circuit. The input terminal 71 is connected to the gate of the P-channel transistor 73 and the gate of the N-channel transistor 75. On the other hand, the input terminal 72
Are connected to the gate of the P-channel transistor 74 and the gate of the N-channel transistor 76. The source of the transistor 73 is connected to the power supply voltage 77, and the drain is connected to the output terminal 79. Transistor 74 has a source connected to power supply voltage 77 and a drain connected to output terminal 79.
It is connected to the. The drain of the transistor 75 is connected to the output terminal 79, and the source is connected to the drain of the transistor 76. The source of the transistor 76 is connected to the ground level 78.

When the signals input from the input terminals 71 and 72 are both at a high level (hereinafter referred to as "1"), the transistors 73 and 74 are both turned off.
Since the transistors 75 and 76 are both turned on, the state of the output terminal 79 is at a low level (hereinafter referred to as “0”).
On the other hand, except when the signals input from the input terminals 71 and 72 satisfy the above condition 1, the transistors 73 and
74 turns on, and the transistors 75 and 7
Since at least one of the terminals 6 is turned off, the state of the output terminal 79 becomes 1.

FIG. 27 is a circuit diagram of a conventional NAND circuit for a logical product of three or more inputs. Input terminals 81, 82 ...
-Three or more multi-signals from 83 are input to the logical product negation circuit. The input terminal 81 is connected to the gate of the P-channel transistor 84 and the gate of the N-channel transistor 87. The input terminal 82 is a P-channel transistor 85
And the gate of the N-channel transistor 88. The same configuration is adopted for each input. Finally, the input terminal 83 is connected to the gate of the P-channel transistor 86 and the gate of the N-channel transistor 89.

The source of the transistor 84 is a power supply voltage 90
And the drain is connected to the output terminal 92.
The source of the transistor 85 is connected to the power supply voltage 90, and the drain is connected to the output terminal 92. Similarly, the source of the P-channel transistor provided for each input is connected to the power supply voltage 90, and the drain is the output terminal 92.
It is connected to the. The source of the transistor 86 is connected to the power supply voltage 90, and the drain is connected to the output terminal 92.

The drain of the transistor 87 is connected to the output terminal 9
2 and the source is connected to the source of the transistor 88. Similarly, N-channel transistors provided for each input are connected in series. The source of the transistor 89 is at the ground level 91.
It is connected to the.

Thus, the input terminals 81, 82... 8
When the signals inputted from 3 are all 1, the transistors 84, 85... 86 are all turned off and the transistors 87, 88... 89 are all turned on, so that the state of the output terminal 92 is 0. On the other hand, the input terminal 8
83, except when the signals input from 1, 82... 83 are all 1 as in the above condition.
86 turn on and at least one of the transistors 87, 88... 89 turns off, so that the state of the output terminal 92 becomes 1.

FIG. 28 is a circuit diagram of a conventional two-input NOR circuit. Two signals are input from the input terminals 101 and 102 to the NOT circuit of the logical sum. The input terminal 101 is connected to the gate of the P-channel transistor 103 and the gate of the N-channel transistor 105. On the other hand, the input terminal 102 is connected to the gate of the P-channel transistor 104 and the gate of the N-channel transistor 106. The source of the transistor 104 is connected to the power supply voltage 107, and the drain is connected to the ground level 108 of the source of the transistor 103. Transistor 1
03 is connected to the output terminal 109. The drain of the transistor 105 is connected to the output terminal 109, and the source is connected to the ground level 108. On the other hand, the drain of the transistor 106 is connected to the output terminal 109, and the source is connected to the ground level 108.

When the signals input from the input terminals 101 and 102 are both 0, the transistor 1
03 and 104 are both turned on, and the transistors 105 and 1
Since both 06 are turned off, the state of the output terminal 109 becomes 1. On the other hand, except when the signals input from the input terminals 101 and 102 are both 1 as described above, at least one of the transistors 103 and 104 is turned off,
Since at least one of the transistors 105 and 106 is turned on, the state of the output terminal 109 becomes 0.

FIG. 29 is a circuit diagram of a conventional NOR circuit of a logical sum of three or more inputs. Input terminals 111, 112
... Three or more multi-signals from 113 are input to the logical NOT circuit. The input terminal 111 is connected to the gate of the P-channel transistor 114 and the gate of the N-channel transistor 117. The input terminal 112 is connected to the gate of the P-channel transistor 115 and the gate of the N-channel transistor 118. Similarly, each input has the same configuration, and finally, the input terminal 113 is connected to the gate of the P-channel transistor 116 and the gate of the N-channel transistor 119.

The source of the transistor 116 is the power supply voltage 1
The drain is connected to the source of the next-stage P-channel transistor. Similarly, P-channel transistors provided at respective inputs are connected in series, and the drain of the transistor 115 is connected to the transistor 1
14 sources. The drain of the transistor 114 is connected to the output terminal 122. The drain of the transistor 117 is connected to the output terminal 122, and the source is connected to the ground level 111. The drain of the transistor 118 is connected to the output terminal 122, and the source is connected to the ground level 111. Similarly,
The drain of the N-channel transistor provided for each input is connected to the output terminal 122, the source is connected to the ground level 111, and finally the transistor 119
Is connected to the ground level 111 at the output terminal 122 of the first stage.

Thus, the input terminals 111, 112,.
When the signals input from 113 are all 0, all the transistors 114, 115... 116 are turned on and all the transistors 117, 118. On the other hand, except when the signals input from the input terminals 111, 112... 113 are all 0 as in the above condition, at least one of the transistors 114, 115. 118 ...
Since at least one of the terminals 119 is turned on, the output terminal 122
Is 0.

In the logic circuits shown in FIGS. 26 to 29,
For example, in the logical product NOT circuit shown in FIG.
Is connected to each gate of the two transistors 73 and 75, one input terminal is connected to each gate of the two transistors in each circuit.

[0014]

However, in an actual logic circuit, for example, in a logical product negation circuit shown in FIG. 26, the signal inputs to the input terminals 71 and 72 do not change between 1 and 0 on average. For example, there are cases where a signal input to one input terminal 71 has many 1s and a signal input to the other input terminal 72 vibrates many times in a short cycle. In this case, since the input terminals 71 and 72 are connected to the gates of two transistors, a charge / discharge current flows to the capacitance of each gate when each signal switches between 1 and 0, so that a large amount of current flows. was there.

The present invention solves the above-mentioned problem. As described above, for example, when one of the input signals is in a state of 1 or 0 for a relatively long period and the other vibrates in a short cycle, the charging is performed. It is an object of the present invention to provide a logic circuit that requires a small discharge current.

[0016]

According to a first aspect of the present invention, a first input terminal and a second input terminal are provided.
And a third input terminal to which a signal having a negative relationship with a signal input to the second input terminal is input;
A first N-channel transistor having a source connected to the first input terminal, a gate connected to the second input terminal, and a drain connected to the node; and a source connected to the first voltage and a gate connected to the first voltage. A second N-channel transistor connected to a third input terminal and having a drain connected to the node; a negation circuit for outputting a negation of the signal state of the node; a gate connected to the second voltage at the source and a gate connected to the second voltage A P-channel transistor connected to the output of the NOT circuit and having a drain connected to the node; a first output terminal for leading the output of the NOT circuit; and a second output terminal for leading a signal state of the node. And an output terminal.

According to such a configuration, in the logic circuit, signals having a negative relation to each other are input to the second input terminal and the third input terminal. For example, the first voltage is a ground level, and the second voltage is a power supply voltage. When 0 (ground level) is input to the second input terminal, that is, 1 (power supply voltage) is input to the third input terminal, the first N-channel transistor turns off and the second N-channel transistor turns on. Therefore, since the state of the node is fixed to the ground level, 1 is output from the first output terminal via the negation circuit regardless of the state of the signal input to the first input terminal, while the second is Output terminal outputs 0 directly from the node. On the other hand, when 1 is input to the second input terminal, that is, 0 is input to the third input terminal, the first N-channel transistor is turned on and the second N-channel transistor is turned off. The signal to be transmitted is sent to the node via the first N-channel transistor, and a signal corresponding to the state of the node is output from the output terminal 1 and the output terminal 2. Therefore, when the second input terminal is 0, that is, when the third input terminal is 1, the signal input from the input terminal 1 depends on the capacitance at the source of the first transistor even when the signal vibrates many times in a short cycle. Since only the charge / discharge current flows, the logic circuit consumes low power when the signal input under such conditions is relatively large.

In the second configuration of the present invention, a signal having a negative relationship with the first input terminal, the second input terminal, and the signal input to the second input terminal is input. Third
A first P-channel transistor having a source connected to the first input terminal, a gate connected to the second input terminal, and a drain connected to the node;
A second P-channel transistor having a source connected to the first voltage, a gate connected to the third input terminal and a drain connected to the node, and a negation circuit for outputting a negation of the signal state of the node; An N-channel transistor having a source connected to the second voltage, a gate connected to the output of the NOT circuit, and a drain connected to the node; a first output terminal for leading the output of the NOT circuit; A second output terminal for deriving a signal state of the node.

According to such a configuration, for example, the first voltage is the power supply voltage and the second voltage is the ground level. Contrary to the above configuration, the second input terminal has a value of 1, that is, the third voltage.
When 0 is input to the input terminal of, the first P-channel transistor is turned off and the second P-channel transistor is turned on. Therefore, the state of the node becomes 1 according to the power supply voltage, and 0 is output from the first output terminal via the NOT circuit, while 1 is output directly from the node at the second output terminal.
Is output.

Further, in the third configuration of the present invention, the first
Or the second configuration, the first input signal is directly input to the first input terminal, and the second input signal is directly input to the second input terminal, and is also input via the NOT circuit. The signal is input to the third input terminal.

According to such a configuration, the logic circuit receives two signals. In the case of the first configuration, the first input signal is supplied to the first input terminal and the second input signal is supplied to the second input terminal. The input signal is directly input to the second input terminal, and the second input signal is input to the third input terminal via the NOT circuit. Thus, the first output terminal outputs the negation of the logical product of the first and second input signals, and the second output terminal outputs the logical product of the first and second input terminals. On the other hand, in the second configuration, the first output terminal outputs the NOT of the logical sum of the first and second input signals, and the second output terminal outputs the logical sum of the first and second input signals. Is done.

Further, in the fourth configuration of the present invention, the first
Or the second configuration, the first input signal is directly input to the first input terminal, and the second input signal is input to the second input terminal via a NOT circuit. At the same time, the signal is directly input to the third input terminal.

According to such a configuration, the logic circuit is configured such that a signal input to the second and third input terminals is a signal having a negative relationship with the third configuration. An operation similar to that of the above-described third configuration is performed for the negative of the second signal.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> An embodiment of the present invention will be described below. FIG. 1 is a circuit diagram of a logic circuit according to the first embodiment of the present invention. This logic circuit is a circuit diagram which realizes a logical product circuit of two input signals A and B and a logical product NOT circuit.

Signal A is input from input terminal 1 and signal B is input from input terminal 2. The input terminal 1 is connected to the source of the N-channel transistor 4. On the other hand, the input terminal 2 is connected to the gate of the transistor 4, and the input terminal 2 is further connected to the gate of the N-channel transistor 5 via the NOT circuit 13. The drain of transistor 4 is connected to node 15. The drain of the transistor 5 is connected to the node 15 and the source is connected to the ground level 9.

The negation circuit 6 inputs the signal state of the node 15 and outputs the negation. The source of P-channel transistor 7 is connected to power supply voltage 8, the gate is connected to the output of NOT circuit 6, and the drain is connected to node 15.
An output terminal 1 for deriving an output of the NOT circuit 6
0 and output terminal 11 for deriving the state of node 15
Is provided.

Thus, when the signal B is 0,
Transistor 4 turns off and transistor 5 turns on.
Therefore, the node 15 is at the ground level 9 regardless of the state of the signal A. Therefore, 1 is output from the output terminal 10 and 0 is output from the output terminal 11. At this time, the transistor 7 is off.

On the other hand, when the signal B is 1, the transistor 4 turns on and the transistor 5 turns off. Therefore, the signal A is sent to the node 15 through the transistor 4. For example, when the signal A is 0, 1 is output from the output terminal 10 and 0 is output from the output terminal 11. At this time, the transistor 7 is off. Also,
When the signal A is 1, 0 is output from the output terminal 10 and 1 is output from the output terminal 11. At this time, the transistor 7 is turned on, and the node 15 is stably maintained at 1 by the power supply voltage 8.

As described above, according to the logic circuit of this embodiment, the negation of the logical product of the signal A and the signal B is obtained from the output terminal 10 by the input of the signals A and B, and the signal A and the signal B are obtained from the output terminal 11. AND is obtained. Further, when the signal B is 0, the transistor 4 is off, so that the signal A
Even if this state oscillates many times in a short cycle, the charge / discharge current at the source capacitance of the transistor 4 results in a logic circuit with low power consumption when the period during which such a state occurs is relatively long.

Next, a comparison will be made between the current consumption of the logic circuit of this embodiment and the current consumption of the above-described conventional AND circuit shown in FIG. Here, for simplicity, the source capacitance, the gate capacitance, and the drain capacitance of each transistor are assumed to be the same, and each capacitance is set to 1 as a reference. In addition, each of the NOT circuits 6 and 13 is evaluated by assuming the circuit shown in FIG.

That is, in FIG. 21, the input terminal 61 of the NOT circuit is connected to the gate of a P-channel transistor 62,
It is connected to the gate of the N-channel transistor 63. The source of the transistor 62 is connected to the power supply voltage 64 and the drain is connected to the output terminal 66. The drain of the transistor 63 is connected to the output terminal 66, and the source is connected to the ground level 65. Thus, the negation circuit outputs the negation of the signal input to the input terminal 61 from the output terminal 66.

In the logic circuit shown in FIG. 1, when the load capacitance of the input terminal 1 is calculated according to the above-described standard, when the signal B is 0, the transistor 4 is off, and only the source capacitance of the transistor 4 is obtained. Becomes On the other hand, signal B
Is 1, the transistor 4 is 1 and the transistor 5 is turned off, so that the load capacity is the source capacity of the transistor 4, the drain capacity of the transistor 4, and the transistor 5
, The gate capacitance of each of the two transistors 62 and 63 (see FIG. 21) constituting the NOT circuit 6, and the drain capacitance of the transistor 7, so that the total is 6.
The load capacity of the input terminal 2 is the gate capacity of the transistor 4 and the two transistors 6
Since each gate capacitance is 2, 63 (see FIG. 21), a total of 3 is obtained.

Similarly, in the conventional AND circuit shown in FIG. 26, when the load capacitance is calculated, the load capacitance of the input terminal 71 becomes the gate capacitance of the transistor 73 and the gate capacitance of the transistor 75. Becomes on the other hand,
The load capacitance of the input terminal 72 is 2 because the gate capacitance of the transistor 74 and the gate capacitance of the transistor 76. The above results are summarized in FIG. However, the first
The input and the second input refer to the signal A and the signal B, respectively.
1 and 72.

The sum of the charge / discharge currents at the input terminals when a signal having a waveform as shown in FIG. 23 is input to both circuits is compared. The first input is a signal having a waveform that oscillates 100 times, and the second input is a oscillating signal of the first input.
The signal is 1 for n times out of 00, and is 0 at other times. For example, the first input is a clock input.

At this time, the sum of the charge / discharge currents at the input terminals in the logic circuit of this embodiment shown in FIG. 1 is compared.
The charge / discharge current at the input terminals 1 and 2 in the logic circuit of the present embodiment shown in FIG. (Load capacity of the first input when the second input is 0) ×
(Vibration frequency of the first input when the second input is 0) +
(Load capacity of the first input when the second input is 1) ×
(The number of vibrations of the first input when the second input is 1) +
(Load capacity of the second input) x (Number of vibrations of the second input)
= 1 · (100−n) + 6 · n + 3 · 1 = 5n + 103

In addition, the above-mentioned conventional logical NOT circuit (FIG. 2)
The charge / discharge current at the input terminals 71 and 72 in 6) is calculated by the following equation. (Load capacity of first input) x (Number of vibrations of first input)
+ (Load capacity of second input) × (Vibration frequency of second input) = 2 · 100 + 2.1 = 202

FIG. 24 is a graph comparing the values of the above-mentioned equations for each value of n. As shown in FIG. 24, the charge / discharge current is constant irrespective of the value of n in the above-described conventional AND circuit (FIG. 26), but in the logic circuit of this embodiment (FIG. 1), the charge / discharge current is constant. The current decreases as the value of n decreases. When n is 19 or less, the charge / discharge current of the logic circuit of the present embodiment (FIG. 1) is smaller than that of the conventional AND circuit of the related art (FIG. 26). Then, when n is 20, the charge and discharge currents of both are almost the same, and
Is larger, the charge / discharge current of the circuit is larger than that of the above-mentioned conventional AND circuit (FIG. 26). However, since it is assumed that the source capacitance, the gate capacitance, the drain capacitance of the transistor coincide, etc., when these capacitances change, the charge / discharge current of both of them changes.

Therefore, in the logic circuit of this embodiment (FIG. 1), the first signal vibrates many times in a short cycle, and the period when the second signal is 0 extends for a relatively long time. Under the conditions, the logic circuit of the present embodiment (FIG. 1) has a smaller charge / discharge current and lower power consumption than the above-described conventional AND circuit (FIG. 26). In other words, the logical product and the logical product negation circuit of the present embodiment operate with low power consumption when the second signal is often 0 and the number of vibrations of the first input is large. Note that this effect of low power consumption is due to the fact that the load capacity of the first signal is small when the second signal is 0.

<Second Embodiment> Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram of a logic circuit according to a second embodiment of the present invention. In FIG. 2, the same parts as those in FIG. However, the insertion position of the NOT circuit 13 is different from that of the logic circuit of the first embodiment (FIG. 1), and the input terminal 2 is directly connected to the gate of the transistor 5; The gate of 4 is NOT circuit 1
3 are connected. It is assumed that the signal B is input from the input terminal 2.

Therefore, the signal B input to the input terminal 2
The bar is processed as a negation of the signal B of the logic circuit of the first embodiment (FIG. 1) in the logic circuit of the present embodiment. Accordingly, if the negation of the signal B bar is defined as the signal B, in the logic circuit of the present embodiment, the negation of the logical product of the signal A and the signal B input from the input terminal 1 is output from the output terminal 10, and the signal is output from the output terminal 11. The logical product of A and signal B is output.
In this circuit, similarly to the first embodiment, when the period during which the signal B bar input from the input terminal 2 is 1 is relatively long, the transistor 4 is turned off and the transistor 5 is turned on. Therefore, when the signal A input from the input terminal 1 oscillates many times in a short cycle, there is an effect that the charge / discharge current is reduced.

<Third Embodiment> Next, a third embodiment of the present invention will be described. FIG. 3 is a circuit diagram of a logic circuit showing a third embodiment of the present invention. In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals. In the present embodiment, three input terminals 1, 2, and 3 are provided, and a signal A is input from the input terminal 1. Next, the signal B is input from the input terminal 2. A signal B bar having a negative relationship with the signal B is input from the input terminal 3. The input terminal 2 is connected to the gate of the N-channel transistor 4, and the input terminal 3 is connected to the gate of the N-channel transistor 5.

Thus, the first embodiment (FIG. 1)
Or the same operation as the logic circuit in the second embodiment (FIG. 2), the output terminal 10 outputs the negation of the logical product of the signal A and the signal B, and the output terminal 11 outputs the logical product of the signal A and the signal B. The product is output. Therefore, similarly to the first embodiment, when the signal B is 0 for a relatively long period and the signal A oscillates many times in a short cycle, there is an effect of reducing power consumption.

In this embodiment, the input signal A is input terminal 1
, And the second input signal B is directly input to the input terminal 2 and the input signal B is input to the input terminal 3 via the NOT circuit. 1) can be realized. Also, the first input signal A
Is input directly to the input terminal 1, the second input signal B bar is input to the input terminal 2 via the NOT circuit, and the second input signal B bar is input directly to the input terminal 3. Thereby, the second embodiment (FIG. 2) can be realized.

<Fourth Embodiment> Next, a fourth embodiment of the present invention will be described. FIG. 4 shows the first type shown in FIG.
FIG. 13 is a circuit diagram of a logic circuit for obtaining a negation of a logical product of three inputs using the logic circuit 20 of the embodiment. In this embodiment, two of the three inputs are input to the logic circuit 20, and the signal output from the output terminal 11 in FIG. 1 is input to one of the logical product NOT circuits 21 in the next stage. The other one of the three inputs is input to the other end of the AND circuit 21.

Thus, the negation of the logical product of the three inputs is output from the logical product negation circuit 21. In the present embodiment, if one input of the logic circuit 20 is a signal that oscillates many times in a short cycle and the other is a signal that has a sufficiently long period of 0 in comparison with the oscillation, FIG. The charge / discharge current is smaller and the power consumption is lower than in the case of using the conventional multi-input logical NOT circuit as shown in FIG.

<Fifth Embodiment> Next, a fifth embodiment of the present invention will be described. FIG. 5 shows the first type shown in FIG.
FIG. 9 is a circuit diagram of a three-input AND circuit using the logic circuit 20 of the embodiment. In the present embodiment, the signal output from the output terminal 11 in the logic circuit 20 to which two of the three inputs are input is input to one of the AND circuits 22 in the next stage. The other one of the three inputs is input to the other end of the AND circuit 22. As a result, the logical product of the three inputs is output from the logical product circuit 22. When the signal A oscillates many times in a short cycle, the effect of reducing the charge / discharge current is obtained.

<Sixth Embodiment> Next, a sixth embodiment of the present invention will be described. FIG. 6 shows the first type shown in FIG.
FIG. 9 is a circuit diagram of a multi-input logical product and a logical product negation circuit using the logic circuit 20 of the embodiment. In this embodiment, the multi-input AND circuit 23 uses the above-described conventional multi-input AND circuit shown in FIG. The AND circuit 23 can be realized by further adding a NOT circuit (FIG. 21) to the output stage of the conventional multi-input AND circuit (FIG. 27).

The signal output from the AND circuit 23 is input to one of the logic circuits 20. The other input signal is input to the other of the logic circuits 20. Since the logical product and the logical product negated output are obtained from the logic circuit 20, the multi-input logical product and the logical product negated output are obtained as the whole circuit shown in FIG. In particular, logic circuit 2
When a signal input to 0 oscillates many times in a short period like a clock and the signal output from the AND circuit 23 has a relatively long period of 0, the logic circuit reduces power consumption. effective.

<Seventh Embodiment> Next, a seventh embodiment of the present invention will be described. FIG. 7 shows the first type shown in FIG.
FIG. 13 is a circuit diagram of a logic circuit for obtaining a negation of a logical product of three inputs using the logic circuit 20 of the embodiment. In the present embodiment, in the logic circuit 20, the signal output from the output terminal 10 shown in FIG.
Is input to The other input of the NAND circuit 24 receives the remaining one signal. As a result, the negation of the logical product of the three inputs is output from the logical product negation circuit 24. At this time, if one input of the logic circuit 20 is a signal that oscillates many times in a short cycle and the other input is a signal that is relatively 0 during a relatively long period, the power consumption is low.

<Eighth Embodiment> Next, an eighth embodiment of the present invention will be described. FIG. 8 shows the first type shown in FIG.
FIG. 10 is a circuit diagram of a logic circuit for obtaining a logical product of three inputs using the logic circuit 20 of the embodiment. Two signals of the three inputs are input to the logic circuit 20, and the output terminal 1 of the logic circuit 20
0 (see FIG. 1) is input to the AND circuit 24 of the next stage via the NOT circuit. Then, the other one signal is input to the other input of the AND circuit 24. As a result, a logical product of three inputs is output.

<Ninth Embodiment> Next, a ninth embodiment of the present invention will be described. FIG. 9 shows the second type shown in FIG.
A logical product of multiple inputs and a logical product negation circuit are realized by using the logical circuit 26 of the embodiment. First, except for one of the multiple inputs, it is input to the above-described conventional multiple-input AND circuit 25 shown in FIG. Then, the output of the NAND circuit 25 is input to the input terminal 2 of the logic circuit 26 (see FIG. 2). The other input terminal 1 (see FIG. 2) of the logic circuit 26 receives the remaining one of the multiple inputs. Since the logical product and the negation of the logical product are output from the logical circuit 26, the logical circuit of the present embodiment can output the logical product of multiple inputs and the negative of the logical product.

<Tenth Embodiment> Next, a tenth embodiment of the present invention will be described.
Embodiment 0 will be described. FIG. 10 realizes a multi-input logical product and a logical product NOT circuit using the logic circuit 27 of the third embodiment shown in FIG. First, a multi-input logical product and a logical product negative circuit 25 are inputted, and signals having a negative relation outputted from the logical circuit 25 are inputted to the input terminal 2 and the input terminal 3 (see FIG. 3) of the logical circuit 27. Is done. Then, the remaining one of the multiple inputs is input to the input terminal 1 of the logic circuit 27 (see FIG. 3). As a result, the logical product and the negation of the logical product are output from the logic circuit 27. The logic circuit 27 used in the present embodiment is different from the logic circuits 20 and 26 (see FIGS. 1 and 9) in FIG.
As shown in FIG.

<Eleventh Embodiment> Next, the first embodiment of the present invention will be described.
One embodiment will be described. FIG. 11 shows the first embodiment of the present invention.
FIG. 2 is a circuit diagram of a logic circuit according to the first embodiment. This logic circuit is a circuit diagram of a logic circuit that realizes a logical sum of two input signals A and B and a NOT circuit of the logical sum.

The signal A is input from the input terminal 31, and the signal B is input from the input terminal 32. The input terminal 31 is connected to the source of the P-channel transistor 34. The input terminal 32 is connected to the gate of the transistor 34, and the input terminal 2 is further connected to the gate of the P-channel transistor 35 via the NOT circuit 43. The drain of transistor 34 is connected to node 45. Transistor 35 has its source connected to power supply voltage 38 and its drain connected to node 45. The negation circuit 36 inputs the signal state of the node 45 and outputs the negation. The drain of the P-channel transistor 37 is connected to the ground level 39, the gate is connected to the output of the NOT circuit 36, and the drain is connected to the node 45. An output terminal 40 for deriving the output of the NOT circuit 36 and an output terminal 41 for deriving the signal state of the node 45 are provided.

Thus, when the signal B is 1,
The transistor 34 turns off and the transistor 35 turns on. Therefore, the power supply voltage 38 is led to 1 at the node 45 regardless of the state of the signal A. Therefore, 0 is output from the output terminal 40, and 1 is output from the output terminal 41. At this time, the transistor 37 is off.

When the signal B is 0, the transistor 34 turns on and the transistor 35 turns off. Therefore, the signal A is sent to the node 45 through the transistor 34. For example, when the signal A is 1, 0 is output from the output terminal 40 and 1 is output from the output terminal 41. At this time, the transistor 37 is off. When the signal A is 0, 1 is output from the output terminal 40 and 0 is output from the output terminal 41. At this time, the transistor 37 is turned on, and the node 45 is stably kept at 0 by the ground level 39.

As described above, according to the logic circuit of the present embodiment, when the signals A and B are inputted, the logical sum of the signal A and the signal B is obtained from the output terminal 40, and the signal A and the signal B are obtained from the output terminal 41. The logical sum is obtained. Further, when the signal B is 1, since the transistor 7 is off, the signal A
Even when the state of FIG. 7 performs a large number of oscillations in a short cycle, the charge / discharge current is generated by the source capacitance of the transistor 37. Therefore, when the period of such a state is relatively long, the logic circuit consumes low power. .

Next, a comparison will be made between the current consumption of the logic circuit of this embodiment and that of the above-mentioned conventional OR circuit shown in FIG. Also in this case, the evaluation is performed using the same assumptions and criteria as in the first embodiment. That is, the source capacitance, the gate capacitance, and the drain capacitance of each transistor are set to be the same, and each capacitance is set to 1 as a reference. In addition, each of the NOT circuits 6 and 13 is evaluated by assuming the circuit shown in FIG.

When the load capacitance of the input terminal 31 shown in FIG. 11 is calculated according to the above-described standard, when the signal B is 0, the transistor 34 is turned on, the transistor 35 is turned off, and the source capacitance of the transistor 34 is turned off. , The drain capacitance of the transistor 34, the drain capacitance of the transistor 35, the gate capacitance of the two transistors 62 and 63 (see FIG. 21) constituting the NOT circuit 36, and the drain capacitance of the transistor 37, so that a total of 6 is obtained. .

Further, when the signal B is 1, the transistor 34 is off, and is 1 because only the source capacitance of the transistor 34 is present. Further, the load capacitance of the input terminal 32 is 3 in total because it is the gate capacitance of the transistor 34 and the gate capacitance of the two transistors 62 and 63 (see FIG. 21) constituting the NOT circuit 43.

Similarly, in the above-mentioned conventional OR circuit shown in FIG. 28, when the load capacitance is calculated, the input terminal 101 is obtained.
Is the gate capacitance of the transistor 103 and the gate capacitance of the transistor 105, so that the total load capacitance becomes 2.
On the other hand, the load capacitance of the input terminal 102 is
And the gate capacitance of the transistor 106, so that the total is 2. The above results are summarized in FIG. However, the first input and the second input refer to the signal A and the signal B, and in the above-described conventional OR NOT circuit (FIG. 26), refer to the signals input to the input terminals 101 and 102, respectively.

The sum of the charge / discharge currents at each input terminal when a signal having a waveform as shown in FIG. 23 is input to both of these circuits is compared. As described above, the first input is a signal having a waveform that oscillates 100 times, and the second input is the first signal.
The signal is evaluated as a signal that is 1 for n times out of 100 times of the input vibration and is 0 otherwise.

At this time, the sum of the charge / discharge currents at the input terminals 31 and 32 in the logic circuit of this embodiment shown in FIG. 11 is compared. The charge / discharge current at the input terminals 1 and 2 in the logic circuit of the present embodiment shown in FIG. 11 is expressed by the following equation, with the current obtained by charging or discharging once with one capacity being 1 as a reference value. (Load capacity of the first input when the second input is 0) ×
(Vibration frequency of the first input when the second input is 0) +
(Load capacity of the first input when the second input is 1) ×
(The number of vibrations of the first input when the second input is 1) +
(Load capacity of the second input) x (Number of vibrations of the second input)
= 6 (100-n) + 1.n + 3.1 = -5n + 60
3

Also, the above-described conventional OR NOT circuit (FIG. 2)
The charge / discharge current at the input terminals 71 and 72 in 6) is calculated by the following equation. (Load capacity of first input) x (Number of vibrations of first input)
+ (Load capacity of second input) × (Vibration frequency of second input) = 2 · 100 + 2.1 = 202

FIG. 25 is a comparison of the values of the above-mentioned equations for each value of n. In the above conventional OR circuit (FIG. 28), the charge / discharge current decreases as the value of n increases. When n is 80 or less, the charge / discharge current is larger than that of the above-described conventional OR circuit (FIG. 28). When n is 80, the charge / discharge currents of the two are almost the same, and when n is larger than that, the charge / discharge current of the logic circuit of this embodiment is smaller than that of the above-mentioned conventional OR circuit (FIG. 28). ing. However, the charge / discharge current of both transistors varies depending on the source capacity, gate capacity, drain capacity, and the like of the transistor.

Therefore, in the logic circuit of this embodiment (FIG. 1), the first signal oscillates many times in a short cycle, and the period in which one of the second signals is 1 is long. Then, the current consumption of the logic circuit of this embodiment (FIG. 11) is smaller than that of the above-described conventional NOT circuit of logical sum (FIG. 28), and the power consumption is lower. That is, the logical sum and the logical negation circuit of the present embodiment operate with low power consumption when the second signal is often 1 and the number of vibrations of the second input is large. Note that the effect of this low current consumption is that the second signal B
Is 1 when the load capacity of the first signal A is small.

<Twelfth Embodiment> Next, the first embodiment of the present invention will be described.
A second embodiment will be described. FIG. 12 shows the first embodiment of the present invention.
FIG. 11 is a circuit diagram of a logic circuit according to a second embodiment. In FIG. 12, the same portions as those in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted. However, the insertion position of the NOT circuit 43 is different from the logic circuit of the eleventh embodiment (FIG. 11), and in this embodiment, the input terminal 32 and the gate of the transistor 35 are directly connected. , The input terminal 32 and the gate of the transistor 34 are connected via a NOT circuit 34.

Therefore, the signal B bar input to the input terminal 32 is processed by the logic circuit of the present embodiment as the negation of the signal B of the logic circuit of the first embodiment (FIG. 1).
Therefore, if the negation of the signal B bar is signal B, in the logic circuit of this embodiment, the signal A and the signal B
Is output, and the logical sum of the signal A and the signal B is output from the output terminal 41. In this circuit, as in the first embodiment, the period in which the signal B bar input from the input terminal 32 is 1 is relatively long and the transistor 34 is turned off and the transistor 35 is turned on. When the signal A input from the input terminal 31 oscillates many times in a short cycle, there is an effect that the charge / discharge current is reduced.

<Thirteenth Embodiment> Next, a thirteenth embodiment of the present invention will be described.
A third embodiment will be described. FIG. 13 shows the first embodiment of the present invention.
FIG. 13 is a circuit diagram of a logic circuit according to a third embodiment. In FIG. 13, the same parts as those in FIG. 11 are denoted by the same reference numerals. In the present embodiment, three input terminals 31, 3
2 and 33 are provided, and the signal A is input from the input terminal 31. Next, the signal B is input from the input terminal 32. A signal B having a negative relationship with the signal B from the input terminal 33
A bar is entered. The input terminal 32 is connected to the gate of an N-channel transistor 34, and the input terminal 33 is connected to the gate of an N-channel transistor 35.

Thus, the first embodiment (FIG. 1)
And the same operation as the logic circuit in the second embodiment (FIG. 2), the output terminal 30 outputs the negation of the logical sum of the signal A and the signal B, and the output terminal 41 outputs the logic of the signal A and the signal B. The sum is output. Therefore, similarly to the first embodiment, when the signal B is 0 for a relatively long period and the signal A oscillates many times in a short cycle, there is an effect of reducing power consumption.

In this embodiment, the input signal A is applied to the input terminal 3
1, the second input signal B is directly input to the input terminal 32, and the input signal B is input to the input terminal 33 via the NOT circuit. 1) can be realized. Further, the first input signal A is directly input to the input terminal 41, the second input signal B is input to the input terminal 42 via the NOT circuit, and the second input signal B is directly input to the third terminal. The above-described second embodiment (FIG. 2) can be realized by inputting an input signal of the second embodiment.

<Fourteenth Embodiment> Next, a first embodiment of the present invention will be described.
Fourth embodiment will be described. FIG. 14 is a circuit diagram of a logic circuit for obtaining the negation of the logical sum of three inputs by using the logic circuit 50 of the first embodiment shown in FIG. In this embodiment, two of the three inputs are input to the logic circuit 50, and the signal output from the output terminal 41 in FIG. 1 is input to one of the logical sum NOT circuits 51 in the next stage. The other one of the three inputs is input to the other end of the OR circuit 51.

As a result, the negation of the logical sum of the three inputs is output from the logical negation circuit 51. In the present embodiment, when one input of the logic circuit 50 is a signal that oscillates many times in a short cycle and the other is a signal that has a sufficiently long period of 0 in comparison with the oscillation, FIG. The charging / discharging current is smaller and the power consumption is lower than in the case of using the above-described conventional multi-input logical NOT circuit shown in FIG.

<Fifteenth Embodiment> Next, a fifteenth embodiment of the present invention will be described.
A fifth embodiment will be described. FIG. 15 is a circuit diagram of a three-input OR circuit using the logic circuit 50 of the first embodiment shown in FIG. In this embodiment, in the logic circuit 50 to which two of the three inputs are inputted, the output terminal 4
1 is output to the next-stage OR circuit 52.
Is input to one of The other one of the three inputs is input to the other end of the OR circuit 52. As a result, the logical sum of the three inputs is output from the logical sum circuit 52. When the signal A oscillates many times in a short cycle, the effect of reducing the charge / discharge current is obtained.

<Sixteenth Embodiment> Next, the first embodiment of the present invention will be described.
A sixth embodiment will be described. FIG. 16 is a circuit diagram of a multi-input logical sum and a logical sum negation circuit using the logic circuit 50 of the first embodiment shown in FIG. In this embodiment, the multi-input OR circuit 53 uses the above-mentioned conventional multi-input OR circuit shown in FIG. The OR circuit 53 can be realized by adding a NOT circuit (FIG. 21) to the output stage of the conventional multi-input NOT circuit (FIG. 27).

Then, the signal output from the OR circuit 53 is input to one of the logic circuits 50. One input signal is input to the other of the logic circuit 52. Then, since the logical circuit 50 obtains the logical sum and the logical negation output, the multi-input logical sum and the logical negation output are obtained as the entire circuit shown in FIG. In particular, when the signal input to the logic circuit 50 oscillates many times in a short cycle like a clock and the signal output from the OR circuit 53 is 0 for a relatively long time, the logic circuit reduces the signal. This has the effect of consuming power.

<Seventeenth Embodiment> Next, the first embodiment of the present invention will be described.
A seventh embodiment will be described. FIG. 17 is a circuit diagram of a logic circuit for obtaining the negation of the logical sum of three inputs using the logic circuit 50 of the eleventh embodiment shown in FIG. In this embodiment, the output terminal 4 shown in FIG.
The signal output from 0 is input to the OR circuit 54 via the NOT circuit. The other input of the OR circuit 54 receives the remaining one signal. Thus, the negation of the logical sum of the three inputs is output from the logical negation circuit 54. At this time, when one input of the logic circuit 50 is a signal that oscillates many times in a short cycle and the other input is a signal that is relatively 0 during a relatively long period, the power consumption is low.

<Eighteenth Embodiment> Next, the first embodiment of the present invention will be described.
Eighth embodiment will be described. FIG. 18 is a circuit diagram of a logic circuit for obtaining a logical sum of three inputs using the logic circuit 50 of the eleventh embodiment shown in FIG. Two of the three inputs are input to the logic circuit 50, and the negation of the signal output from the output terminal 40 (see FIG. 11) of the logic circuit 50 is input to the OR circuit 54 in the next stage. The other input of the OR circuit 54 receives the other signal. As a result, a logical sum of three inputs is output.

<Nineteenth Embodiment> Next, a first embodiment of the present invention will be described.
A ninth embodiment will be described. FIG. 19 realizes a multi-input logical sum and a logical NOT circuit using the logic circuit 56 of the second embodiment shown in FIG. First, except for one of the multiple inputs, it is input to the above-mentioned conventional multiple-input NOR circuit 55 shown in FIG. The output of the OR circuit 55 is connected to the input terminal 2 of the logic circuit 56 (FIG. 1).
2). The other input terminal 1 (see FIG. 12) of the logic circuit 56 receives the remaining one of the multiple inputs. Since the logical sum and the negation of the logical sum are output from the logical circuit 56, the logical circuit of the present embodiment can output the multi-input logical sum and the negation of the logical sum.

<Twentieth Embodiment> Next, a second embodiment of the present invention will be described.
Embodiment 0 will be described. FIG. 20 realizes a multi-input logical sum and a logical sum negation circuit by using the logic circuit 57 of the third embodiment shown in FIG. First, signals having a negative relationship with each other which are input to the multi-input logical sum and logical sum NOT circuit 55 and output from the logical circuit 55 are input terminals 22 and 33 of the logical circuit 57 (see FIG. 13).
Is input to Then, the remaining one of the multiple inputs is input to the input terminal 1 of the logic circuit 57 (see FIG. 13).
As a result, the logical sum and the negation of the logical sum are output from the logic circuit 57. Logic circuit 5 used in this embodiment
As compared with the logic circuits 50 and 56 (see FIGS. 11 and 12), the number 7 has one less negation circuit as shown in FIG.

[0081]

As described above, in the logic circuit according to the first aspect, when the input state of the second input terminal is 0, that is, when the input state of the third input terminal is 1, the first N Since the channel transistor is turned off and the second N-channel transistor is turned on, the state of the node becomes the first voltage. Therefore, even if a signal input that frequently repeats in a short cycle is provided at the first input terminal, the first input terminal becomes the first voltage. , Only the charge / discharge current at the source of the N-channel transistor is used. Therefore, when the signal input under such conditions is relatively large, the logic circuit consumes low power.

In the logic circuit according to the second aspect, contrary to the above condition, when the signal state of the second input terminal becomes 0, that is, when the signal state of the third input terminal becomes 0, the first state is obtained.
Is turned off and the second P-channel transistor is turned on, so that the state of the node becomes the first voltage. Therefore, even if the first input terminal vibrates many times in a short period, the first P-channel transistor is turned off. Only the charge / discharge current at the source, the logic circuit consumes less power when the signal input under such conditions is relatively large.

According to the logic circuit of the third aspect, the first and second input signals are provided. In the configuration of the logic circuit of the first aspect, the first input signal is supplied from the first output terminal. AND of the logical product of the second input signal and the second input signal is output.
And outputs the logical product of the first input signal and the second input signal. In the configuration of the logic circuit according to claim 2, the first output terminal outputs the negation of the first and second logical sums, and the second output terminal outputs the logical sum of the first and second input signals. Is done.

According to the logic circuit of the fourth aspect, the first input signal is input to the input terminal, and the second input signal is input to the second input terminal via the NOT circuit. , The second input signal is directly input to the third input signal, so that the logic circuit described in claim 3 is processed as a signal having a negative relationship with the second input signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a logic circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a logic circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a logic circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a logic circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of a logic circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram of a logic circuit according to a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram of a logic circuit according to a seventh embodiment of the present invention.

FIG. 8 is a circuit diagram of a logic circuit according to an eighth embodiment of the present invention.

FIG. 9 is a circuit diagram of a logic circuit according to a ninth embodiment of the present invention.

FIG. 10 is a circuit diagram of a logic circuit according to a tenth embodiment of the present invention.

FIG. 11 is a circuit diagram of a logic circuit according to an eleventh embodiment of the present invention.

FIG. 12 is a circuit diagram of a logic circuit according to a twelfth embodiment of the present invention.

FIG. 13 is a circuit diagram of a logic circuit according to a thirteenth embodiment of the present invention.

FIG. 14 is a circuit diagram of a logic circuit according to a fourteenth embodiment of the present invention.

FIG. 15 is a circuit diagram of a logic circuit according to a fifteenth embodiment of the present invention.

FIG. 16 is a circuit diagram of a logic circuit according to a sixteenth embodiment of the present invention.

FIG. 17 is a circuit diagram of a logic circuit according to a seventeenth embodiment of the present invention.

FIG. 18 is a circuit diagram of a logic circuit according to an eighteenth embodiment of the present invention.

FIG. 19 is a circuit diagram of a logic circuit according to a nineteenth embodiment of the present invention.

FIG. 20 is a circuit diagram of a logic circuit according to a twentieth embodiment of the present invention.

FIG. 21 is a circuit diagram of a NOT circuit of the logic circuit.

FIG. 22 is a table summarizing the load capacitance of each circuit.

FIG. 23 shows input waveforms to each circuit.

FIG. 24 is a graph comparing charge and discharge currents of a logical product negation circuit;

FIG. 25 is a graph comparing the charge / discharge currents of the OR circuit.

FIG. 26 is a circuit diagram of a conventional NAND circuit of a logical product.

FIG. 27 is a circuit diagram of a conventional multi-input NAND circuit.

FIG. 28 is a circuit diagram of a conventional logical OR NOT circuit.

FIG. 29 is a circuit diagram of a conventional multi-input logical NOT circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Input terminal 3 Input terminal 4 N-channel transistor 5 N-channel transistor 6 Negation circuit 7 P-channel transistor 8 Power supply voltage 9 Ground level 10 Output terminal 11 Output terminal 13 Negation circuit 15 Node 20 Logic circuit of the first embodiment DESCRIPTION OF SYMBOLS 21 AND circuit NOT circuit 22 AND circuit 24 AND circuit NOT circuit 26 Logic circuit of 2nd embodiment 27 Logic circuit of 3rd embodiment 31 Input terminal 32 Input terminal 33 Input terminal 34 N-channel transistor 35 N-channel Transistor 36 Negation circuit 37 P-channel transistor 38 Power supply voltage 39 Ground level 40 Output terminal 41 Output terminal 43 Negation circuit 45 Node 50 Logic circuit of first embodiment 51 Logical product negation circuit 52 Logical product circuit 54 Logical product negation circuit 56 Second fruit Logic circuit of the embodiment 57 Logic circuit of the third embodiment

Claims (4)

[Claims] A first input terminal; a second input terminal;
A third input terminal to which a signal having a negative relationship with the signal input to the second input terminal is input, a source connected to the first input terminal, and a gate connected to the second input terminal A first N-channel transistor having a drain connected to the node, a second N-channel transistor having a source connected to the first voltage, a gate connected to the third input terminal, and a drain connected to the node. A channel transistor, a negation circuit that outputs negation of the signal state of the node, a p-channel transistor having a source connected to the second voltage, a gate connected to the output of the negation circuit, and a drain connected to the node , A first output terminal for deriving an output of the negation circuit, and a second output terminal for deriving a signal state of the node. 2. A first input terminal, a second input terminal,
A third input terminal to which a signal having a negative relationship with the signal input to the second input terminal is input, a source connected to the first input terminal, and a gate connected to the second input terminal A first P-channel transistor having a drain connected to the node and a second P-channel transistor having a source connected to the first voltage, a gate connected to the third input terminal, and a drain connected to the node. A channel transistor, a negation circuit that outputs negation of the signal state of the node, an n-channel transistor having a source connected to the second voltage, a gate connected to the output of the negation circuit, and a drain connected to the node , A first output terminal for deriving an output of the negation circuit, and a second output terminal for deriving a signal state of the node. 3. A first input signal is directly input to the first input terminal, a second input signal is directly input to the second input terminal, and the third input signal is input via a NOT circuit. The logic circuit according to claim 1, wherein the logic circuit is input to a terminal. 4. A first input signal is directly input to said first input terminal, and a second input signal is input to said second input terminal via a NOT circuit and to a third input terminal. The logic circuit according to claim 1, wherein は is directly input.