JPH11330304A - Semiconductor plastic package - Google Patents

Semiconductor plastic package

Info

Publication number
JPH11330304A
JPH11330304A JP14520898A JP14520898A JPH11330304A JP H11330304 A JPH11330304 A JP H11330304A JP 14520898 A JP14520898 A JP 14520898A JP 14520898 A JP14520898 A JP 14520898A JP H11330304 A JPH11330304 A JP H11330304A
Authority
JP
Japan
Prior art keywords
semiconductor chip
metal
printed wiring
wiring board
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14520898A
Other languages
Japanese (ja)
Other versions
JP3985342B2 (en
Inventor
Morio Take
杜夫 岳
Nobuyuki Ikeguchi
信之 池口
Toshihiko Kobayashi
敏彦 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Gas Chemical Co Inc
Original Assignee
Mitsubishi Gas Chemical Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Gas Chemical Co Inc filed Critical Mitsubishi Gas Chemical Co Inc
Priority to JP14520898A priority Critical patent/JP3985342B2/en
Priority to US09/237,840 priority patent/US6097089A/en
Priority to TW088101289A priority patent/TW401725B/en
Priority to EP99300654A priority patent/EP0933813A2/en
Priority to KR1019990002682A priority patent/KR19990068179A/en
Publication of JPH11330304A publication Critical patent/JPH11330304A/en
Priority to US09/583,148 priority patent/US6265767B1/en
Application granted granted Critical
Publication of JP3985342B2 publication Critical patent/JP3985342B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

Abstract

PROBLEM TO BE SOLVED: To enable a semiconductor plastic package to be improved in heat dissipating properties and restrained from absorbing moisture through the underside of a chip, by a method wherein a semiconductor chip is fixed with thermally conductive adhesive agent to a metal foil which serves as a semiconductor chip mount where projections are brought into contact, and metal conical truncated projections are brought into contact with a metal foil on the opposite side. SOLUTION: A semiconductor plastic package has a structure where a metal plate (a) which is excellent in heat dissipating properties and provided with truncated conical projections (c) formed on its front and rear is arranged at the center in the thickness direction of a printed wiring board, the metal projections (c) are brought into direct contact with a front and a rear metal foil or bonded to them through the intermediary of thermally conductive adhesive agent, a semiconductor chip is fixed to the metal foil where the metal projections (c) are brought into contact, the semiconductor chip is connected to peripheral circuit conductors with bonding wires, and the semiconductor chip is sealed up with resin together with the bonding wires and bonding pads. A front and a rear circuit conductor and through-holes plated for continuity are insulated with thermosetting resin composition.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップを少
なくとも1個小型プリント配線板に搭載した形の、新規
な半導体プラスチックパッケージに関する。特に、マイ
クロプロセッサー、マイクロコントローラー、ASIC、グ
ラフィック等の比較的高ワットで、多端子高密度の半導
体プラスチックパッケージに適している。本半導体プラ
スチックパッケージは、ソルダーボールを用いてマザー
ボードプリント配線板に実装して電子機器として使用さ
れる。
The present invention relates to a novel semiconductor plastic package in which at least one semiconductor chip is mounted on a small printed wiring board. In particular, it is suitable for relatively high wattage, multi-terminal, high-density semiconductor plastic packages such as microprocessors, microcontrollers, ASICs, and graphics. This semiconductor plastic package is mounted on a motherboard printed wiring board using solder balls and used as an electronic device.

【0002】[0002]

【従来の技術】従来、半導体プラスチックパッケージと
して、プラスチックボールグリッドアレイ(P-BGA)やプ
ラスチックランドグリッドアレイ(P-LGA)等の、プラス
チックプリント配線板の上面に半導体チップを固定し、
このチップをプリント配線板上面に形成された導体回路
にワイヤボンディングで結合し、プリント配線板の下面
にはソルダーボールを用いて、マザーボードプリント配
線板と接続するための導体パッドを形成し、表裏回路導
体をメッキされたスルーホールで接続し、半導体チップ
を樹脂封止している構造の半導体プラスチックパッケー
ジは公知である。本公知構造において、半導体から発生
する熱をマザーボードプリント配線板に拡散させるた
め、半導体チップを固定するための上面の金属箔から下
面に接続するメッキされた熱拡散スルーホールが形成す
ることも知られている。
2. Description of the Related Art Conventionally, a semiconductor chip is fixed on the upper surface of a plastic printed wiring board such as a plastic ball grid array (P-BGA) or a plastic land grid array (P-LGA) as a semiconductor plastic package.
This chip is bonded to the conductor circuit formed on the upper surface of the printed wiring board by wire bonding, and the lower surface of the printed wiring board is formed with conductor pads for connection to the motherboard printed wiring board using solder balls. 2. Description of the Related Art A semiconductor plastic package having a structure in which conductors are connected by plated through holes and a semiconductor chip is sealed with a resin is known. In the known structure, it is also known that a plated heat diffusion through hole connecting from the upper metal foil to the lower surface for fixing the semiconductor chip is formed in order to diffuse heat generated from the semiconductor to the motherboard printed wiring board. ing.

【0003】該スルーホールを通して、水分が半導体固
定に使われている銀粉入り樹脂接着剤に吸湿され、マザ
ーボードへの実装時の加熱により、また、半導体部品を
マザーボードから取り外す際の加熱により、層間フクレ
を生じる危険性があり、これはポップコーン現象と呼ば
れている。このポップコーン現象が発生した場合、パッ
ケージは使用不能となることが多く、この現象を大幅に
改善する必要がある。また、半導体の高機能化、高密度
化は、ますます発熱量の増大を意味し、熱放散用のため
の半導体チップ直下のスルーホールのみでは熱の放散は
不十分となってきている。
Through the through holes, moisture is absorbed by the resin adhesive containing silver powder used for fixing the semiconductor, and is heated by mounting at the time of mounting on the motherboard and by heating at the time of removing the semiconductor parts from the motherboard. This is called the popcorn phenomenon. When this popcorn phenomenon occurs, the package often becomes unusable, and it is necessary to greatly improve this phenomenon. In addition, higher functionality and higher density of semiconductors mean more and more heat generation, and heat dissipation is insufficient with only through holes directly below the semiconductor chip for heat dissipation.

【0004】[0004]

【発明が解決しようとする課題】本発明は、以上の問題
点を改善した半導体プラスチックパッケージを提供す
る。
SUMMARY OF THE INVENTION The present invention provides a semiconductor plastic package which solves the above problems.

【0005】[0005]

【課題を解決するための手段】本発明は、プリント配線
板の厚さ方向のほぼ中央に、プリント配線板とほぼ同じ
大きさの金属板を配置し、プリント配線板の片面に、少
なくとも1個の半導体チップを熱伝導性接着剤で固定
し、該金属板と表面の信号伝播回路導体とを多官能性シ
アン酸エステル樹脂組成物等で絶縁し、そのプリント配
線板表面の信号伝播回路導体と半導体チップとをワイヤ
ボンディングで接続し、少なくとも該回路導体を、プリ
ント配線板の反対面に形成された回路導体もしくは該ハ
ンダボールでの接続用導体パッドに、金属板と樹脂組成
物で絶縁されたスルーホール導体で結線し、少なくと
も、半導体チップ、ワイヤ、ボンディングパッドを樹脂
封止している構造の半導体プラスチックパッケージにお
いて、該プリント配線板の一部を構成する金属板に複数
個の円錐台形の金属突起を、半導体チップを直接固定す
る金属箔と直接接触するか、熱伝導性接着剤を介して接
合するように形成し、該突起が接触している表面の半導
体チップ搭載部となる金属箔上に熱伝導性接着剤で半導
体チップを固定し、半導体チップ固定面の反対面にも複
数個の金属円錐台形突起を裏面の金属箔と直接接触する
か、接合するように形成している構造の半導体プラスチ
ックパッケージを提供する。本発明の半導体プラスチッ
クパッケージは、半導体チップから発生した熱は、熱伝
導性接着剤を通して円錐台形金属突起部から金属板に伝
導し、反対面の金属円錐台形突起からハンダボールを通
じてマザーボードプリント配線板に逃げる構造を有して
いる。本発明によれば、熱放散性に優れ、半導体チップ
の下面からの吸湿がなく、吸湿後の耐熱性、すなわちポ
ップコーン現象が大幅に改善されるとともに、プレッシ
ャークッカー後の電気絶縁性、耐マイグレーション性等
に優れ、加えて大量生産性にも適しており、経済性の改
善された、新規な構造の半導体プラスチックパッケージ
が提供される。
According to the present invention, a metal plate having substantially the same size as a printed wiring board is disposed substantially at the center in the thickness direction of the printed wiring board, and at least one metal plate is provided on one surface of the printed wiring board. Is fixed with a heat conductive adhesive, the metal plate and the signal transmission circuit conductor on the surface are insulated with a polyfunctional cyanate ester resin composition or the like, and the signal transmission circuit conductor on the surface of the printed wiring board is A semiconductor chip was connected by wire bonding, and at least the circuit conductor was insulated with a metal plate and a resin composition by a circuit conductor formed on the opposite surface of the printed wiring board or a conductor pad for connection with the solder ball. In a semiconductor plastic package having a structure in which at least a semiconductor chip, a wire, and a bonding pad are sealed with a resin, the printed wiring is connected by a through-hole conductor. A plurality of truncated cone-shaped metal protrusions are formed on a metal plate constituting a part of the metal plate so as to directly contact with a metal foil for directly fixing a semiconductor chip or to be joined via a heat conductive adhesive; The semiconductor chip is fixed with a thermally conductive adhesive on the metal foil that will be the semiconductor chip mounting part on the surface with which it is in contact, and a plurality of metal truncated conical protrusions are also formed on the back of the metal foil on the opposite side of the semiconductor chip fixing surface The present invention provides a semiconductor plastic package having a structure that is formed to be in direct contact with or bonded to a semiconductor plastic package. In the semiconductor plastic package of the present invention, the heat generated from the semiconductor chip is conducted to the metal plate from the truncated conical metal protrusion through the heat conductive adhesive and from the metal truncated conical protrusion on the opposite surface to the motherboard printed wiring board through the solder ball. It has an escape structure. ADVANTAGE OF THE INVENTION According to this invention, it is excellent in heat dissipation, there is no moisture absorption from the lower surface of a semiconductor chip, heat resistance after moisture absorption, that is, a popcorn phenomenon is largely improved, electrical insulation after pressure cooker, and migration resistance. The present invention provides a semiconductor plastic package having a novel structure, which is excellent in the above-mentioned characteristics, is suitable for mass productivity, and has improved economic efficiency.

【0006】[0006]

【発明の実施の形態】本発明の半導体プラスチックパッ
ケージは、プリント配線板の厚み方向のほぼ中央に熱放
散性の良好な、表裏に円錐台形の突起を形成した金属板
を配置し、金属突起を表裏の金属箔に直接接触させる
か、熱伝導性接着剤を介して接合させ、表面の円錐台形
突起が接触する金属箔上には、熱伝導性接着剤で半導体
チップを固定し、該半導体チップをワイヤボンディング
で周囲の回路導体と接続し、少なくとも半導体チップ、
ボンディングワイヤ、ボンディングパッドを樹脂封止し
ており、裏面の円錐台形突起と同じように接続した金属
箔にはハンダボールを接合し、ハンダボールがマザーボ
ードプリント配線板と接合した形態となっており、表裏
の回路導体および導通用のメッキされたスルーホール
は、熱硬化性樹脂組成物で絶縁されている構造を有す
る。。
BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor plastic package according to the present invention is provided with a metal plate having good heat dissipation and a truncated conical projection formed on the front and back sides at substantially the center in the thickness direction of the printed wiring board. The semiconductor chip is directly contacted with the front and back metal foils or bonded via a heat conductive adhesive, and the semiconductor chip is fixed with the heat conductive adhesive on the metal foil to which the truncated conical protrusion on the surface contacts. Is connected to the surrounding circuit conductors by wire bonding, and at least a semiconductor chip,
Bonding wires and bonding pads are sealed with resin, solder balls are bonded to the metal foil connected in the same way as the truncated conical protrusions on the back surface, and the solder balls are bonded to the motherboard printed wiring board, The front and back circuit conductors and the plated through holes for conduction have a structure insulated by the thermosetting resin composition. .

【0007】公知のスルーホールを有する金属芯プリン
ト配線板の上面に半導体チップを固定する方法において
は、従来のP-BGAパッケージと同様に、半導体チップか
らの熱は直下の熱放散用スルーホールに落として熱放散
せざるを得ず、ポップコーン現象は改善できない。本発
明は、まず金属芯とする金属板をあらかじめ公知のエッ
チング等の方法で、半導体チップを固定する位置に、複
数個の円錐台形の突起を形成する。また、同時に、或い
は後で表裏の導通スルーホールを形成可能なように、ス
ルーホールを形成しようとする位置にスルーホール径よ
り大きめのクリアランスホール又はスリット孔を、公知
のエッチング法、打ち抜き法、ドリル、レーザー等で金
属芯に形成する。
In a known method of fixing a semiconductor chip on the upper surface of a metal-core printed wiring board having a through hole, heat from the semiconductor chip is transferred to a heat-dissipating through hole immediately below, similarly to a conventional P-BGA package. It has to drop heat to dissipate heat, and the popcorn phenomenon cannot be improved. According to the present invention, first, a plurality of truncated cone-shaped protrusions are formed at positions where a semiconductor chip is fixed by a known method such as etching a metal plate serving as a metal core. Also, a clearance hole or a slit hole larger than the diameter of the through hole is formed at a position where the through hole is to be formed by a known etching method, a punching method, , Formed on the metal core by laser or the like.

【0008】該円錐台形突起とクリアランスホールまた
はスリット孔が形成された金属板の表面には、公知の方
法で酸化処理、微細凹凸形成、皮膜形成等の接着性や電
気絶縁性向上のための表面処理を必要に応じて施す。該
表面処理され、複数個の円錐台形突起部が両面に形成さ
れ、クリアランスホール又はスリット孔が形成された金
属板の上に、該円錐台形金属突起部あるいは熱伝導性接
着剤が付着した突起部が僅かに露出するようにして、す
べて熱硬化性樹脂組成物で全面絶縁部を形成する。熱硬
化性樹脂組成物による絶縁部の形成は、半硬化状態の熱
硬化性樹脂組成物を基材含浸、乾燥したプリプレグ、樹
脂シート、樹脂付き金属箔、或いは塗布樹脂層を用いて
なされる。絶縁部の高さは、積層成形後に、表面の半導
体チップを固定する金属箔部に円錐台形金属突起部ある
いは熱伝導性接着剤が付着した突起部が接触するように
し、半導体チップから発生した熱は、この搭載部分から
熱伝導して内層金属板の円錐台形突起部分を通り、金属
板に伝達し、反対面の金属円錐台形突起部分を通ってハ
ンダボール用パッドに伝導し、ハンダボールで接合した
マザーボードプリント配線板に拡散する。表裏には、ク
リアランスホール又はスリット孔を十分埋め込むことが
できる樹脂量、樹脂流れを有するプリプレグ、樹脂シー
ト、樹脂付き金属箔、塗布樹脂層等を配置する。必要に
より金属箔、片面金属箔張積層板、片面回路形成両面金
属箔張積層板、又は片面回路形成多層板を配置し、加
熱、加圧下、好ましくは真空下に積層成形して一体化す
る。
The surface of the metal plate on which the truncated conical protrusions and the clearance holes or slit holes are formed is a surface for improving adhesion and electrical insulation such as oxidation treatment, formation of fine irregularities, and film formation by a known method. Perform processing as needed. The surface treatment, a plurality of truncated cone-shaped protrusions are formed on both surfaces, and the truncated cone-shaped metal protrusions or protrusions having a thermally conductive adhesive adhered to a metal plate on which clearance holes or slit holes are formed. Is formed, and the entire surface is formed of a thermosetting resin composition. The formation of the insulating portion using the thermosetting resin composition is performed using a prepreg, a resin sheet, a resin-coated metal foil, or a coated resin layer in which a semi-cured thermosetting resin composition is impregnated with a base material and dried. The height of the insulating portion is set such that, after lamination molding, the truncated cone-shaped metal projection or the projection to which the heat conductive adhesive is attached is in contact with the metal foil portion for fixing the semiconductor chip on the surface, and the heat generated from the semiconductor chip is Is conducted from this mounting part, passes through the truncated cone-shaped protrusion of the inner layer metal plate, transmits to the metal plate, conducts to the solder ball pad through the metal truncated cone-shaped protrusion on the opposite surface, and joins with the solder ball Spread on the printed circuit board. On the front and back, a prepreg, a resin sheet, a resin-coated metal foil, a coating resin layer, and the like having a resin amount and a resin flow capable of sufficiently filling the clearance hole or the slit hole are arranged. If necessary, a metal foil, a single-sided metal foil-clad laminate, a single-sided circuit-formed double-sided metal foil-clad laminate, or a single-sided circuit-formed multilayer board is placed, and laminated and integrated under heat and pressure, preferably under vacuum.

【0009】金属板の側面については、熱硬化性樹脂組
成物で埋め込まれている形、露出している形、いずれの
形でも良いが、錆を生じない点では周囲を樹脂で埋め込
んで金属面の露出しない構造の方が好ましい。また、サ
ブトラクティブ法によるスルーホールプリント配線板の
形成のためには、積層成形時に、表裏の最外層に、プリ
ント配線板よりやや大きめの金属箔を配置して、加熱、
加圧下に積層成形することにより、外層回路形成用の金
属箔で表裏が覆われた金属板入り金属箔張積層板が形成
される。
Regarding the side surface of the metal plate, any of a shape embedded in the thermosetting resin composition and an exposed shape may be used. Is preferred. In addition, in order to form a through-hole printed wiring board by the subtractive method, a metal foil slightly larger than the printed wiring board is arranged on the outermost layer on the front and back sides during lamination molding, and heating,
By laminating and molding under pressure, a metal foil-clad laminate with a metal plate covered on both sides with a metal foil for forming an outer layer circuit is formed.

【0010】表裏層に金属箔を使用しないで積層成形す
る場合、公知のアディティブ法にて回路を形成し、プリ
ント配線板を作る。
In the case of laminating and molding without using a metal foil for the front and back layers, a circuit is formed by a known additive method to produce a printed wiring board.

【0011】上記サブトラクティブ法、セミアディティ
ブ法で作成した板の、半導体を固定する部分以外の箇所
に表裏の回路を導通するスルーホール用孔をドリル等を
用いて、公知の方法にて小径の孔をあける。
In a plate made by the above-described subtractive method or semi-additive method, a through-hole for conducting a circuit on the front and back is formed in a portion other than a portion where a semiconductor is fixed by a drill or the like by a known method. Drill holes.

【0012】表裏回路導通用のスルーホール用孔は、樹
脂の埋め込まれた金属板クリアランスホール又はスリッ
ト孔のほぼ中央に、金属板と接触しないように形成す
る。必要によりデスミア処理を施し、次いで無電解メッ
キや電解メッキによりスルーホール内部の金属層を形成
して、メッキされたスルーホールを形成するとともに、
フルアディティブ法では、同時に表裏にワイヤボンディ
ング用端子、回路、ソルダーボール用パッド等を形成す
る。
The through hole for conducting the front and back circuits is formed substantially at the center of the metal plate clearance hole or slit hole in which the resin is embedded so as not to contact the metal plate. Apply desmear treatment as necessary, then form a metal layer inside the through hole by electroless plating or electrolytic plating, and form a plated through hole,
In the full-additive method, wire bonding terminals, circuits, solder ball pads, and the like are simultaneously formed on the front and back surfaces.

【0013】セミアディティブ法では、スルーホールを
メッキすると同時に、表裏も全面メキされ、その後、公
知の方法にて上下に回路を形成する。
In the semi-additive method, both the front and back surfaces are plated at the same time as plating the through holes, and thereafter, circuits are formed on the upper and lower sides by a known method.

【0014】表裏の回路を形成後、貴金属メッキを、少
なくともワイヤボンディングパッド表面に形成してプリ
ント配線板を完成させる。この場合、貴金属メッキの必
要のない箇所は、事前にメッキレジストで被覆してお
く。または、メッキ後に、必要により公知の熱硬化性樹
脂組成物、或いは光選択熱硬化性樹脂組成物で、少なく
とも半導体チップ搭載部、ボンディングパッド部、反対
面のハンダボール接着用パッド部以外の表面に皮膜を形
成する。
After forming the front and back circuits, noble metal plating is formed on at least the surface of the wire bonding pad to complete the printed wiring board. In this case, a portion that does not require noble metal plating is covered with a plating resist in advance. Or, after plating, if necessary, a known thermosetting resin composition, or a photoselective thermosetting resin composition, at least on the semiconductor chip mounting portion, the bonding pad portion, and the surface other than the solder ball bonding pad portion on the opposite surface. Form a film.

【0015】該プリント配線板の、半導体チップを搭載
する金属箔の上に、半導体チップを、熱伝導性接着剤を
用いて固定し、さらに半導体チップとプリント配線板回
路のボンディングパッドとをワイヤボンディング法で接
続し、少なくとも、半導体チップ、ボンディングワイ
ヤ、及びボンディングパッドを公知の封止樹脂で封止す
る。
The semiconductor chip is fixed on the metal foil of the printed wiring board on which the semiconductor chip is mounted by using a heat conductive adhesive, and the semiconductor chip and the bonding pads of the printed wiring board circuit are wire-bonded. Then, at least the semiconductor chip, the bonding wires, and the bonding pads are sealed with a known sealing resin.

【0016】半導体チップと反対面のソルダーボール接
続用導体パッドに、ソルダーボールを接続してP-BGA を
作り、マザーボードプリント配線板上の回路にソルダー
ボールを重ね、ボールを熱熔融してマザーボードとプリ
ント配線板とを接続する。あるいは、パッケージにソル
ダーボールをつけずにP-LGA を作り、マザーボードプリ
ント配線板に実装する時に、マザーボードプリント配線
板面に形成されたソルダーボール接続用導体パッドとP-
LGA 用のソルダーボール用導体パッドとを、ソルダーボ
ールを加熱熔融してマザーボードとプリント配線板とを
接続する。
A P-BGA is formed by connecting a solder ball to a solder ball connecting conductor pad on the opposite side of the semiconductor chip, and the solder ball is superimposed on a circuit on a motherboard printed wiring board. Connect to the printed wiring board. Alternatively, when making a P-LGA without attaching solder balls to the package and mounting it on the motherboard printed wiring board, the solder ball connection conductor pads formed on the motherboard printed wiring board surface and the P-LGA
The mother board and the printed wiring board are connected by heating and melting the solder ball conductor pads for the LGA and the solder balls.

【0017】本発明に用いる金属板は、特に限定しない
が、高弾性率、高熱伝導性で、厚さ30〜500μmのもの
が好適である。具体的には、純銅、無酸素銅、その他、
銅が95重量%以上のFe,Sn,P,Cr,Zr,Zn等との合金が好適
に使用される。また、合金の表面を銅メッキした金属板
等も使用できる。
Although the metal plate used in the present invention is not particularly limited, a metal plate having a high elastic modulus, a high thermal conductivity and a thickness of 30 to 500 μm is preferable. Specifically, pure copper, oxygen-free copper, and others,
An alloy of 95% by weight or more of copper with Fe, Sn, P, Cr, Zr, Zn, or the like is preferably used. Also, a metal plate or the like in which the surface of the alloy is plated with copper can be used.

【0018】本発明の金属円錐台形突起部の高さは、特
に限定はないが、50〜150μmが好適である。また、プ
リプレグ、樹脂シート、樹脂付き金属箔、塗布樹脂等の
絶縁層の厚さは、金属円錐台形突起の高さよりやや低
め、好ましくは5〜15μm低めとし、積層成形後に表層
金属箔と接続させる。あるいは、円錐台形の上に熱伝導
性接着剤を付着させ、積層成形時に外層の金属箔と溶融
接続させて、信頼性を向上させる。円錐台形の大きさ
は、特に限定しないが、一般には、底部の径が0.1〜5μ
m、上部の径が0〜1μmとする。熱伝導性接着剤として
は、公知のものが使用できる。具体的には、銀ペース
ト、銅ペースト、ハンダペースト、錫・銀・銅系等一般
に公知の鉛フリーハンダが挙げられる。
The height of the metal truncated conical projection of the present invention is not particularly limited, but is preferably 50 to 150 μm. In addition, the thickness of the insulating layer of the prepreg, the resin sheet, the metal foil with resin, the coating resin, etc., is slightly lower than the height of the metal truncated cone-shaped projection, preferably 5 to 15 μm lower, and connected to the surface metal foil after lamination molding. . Alternatively, a thermally conductive adhesive is adhered onto the truncated cone, and is melt-connected to the outer metal foil during lamination molding to improve reliability. The size of the truncated cone is not particularly limited, but generally, the diameter of the bottom is 0.1 to 5 μm.
m, the diameter of the upper part is 0 to 1 μm. Known materials can be used as the heat conductive adhesive. Specifically, a generally known lead-free solder such as a silver paste, a copper paste, a solder paste, and a tin / silver / copper-based solder may be used.

【0019】金属円錐台形突起部形成範囲は、半導体チ
ップ面積以下、一般的には5〜20mm角以内とし、半導体
チップ固定箇所の下に存在するようにする。
The range of formation of the metal truncated conical protrusion is set to be equal to or less than the area of the semiconductor chip, generally within a range of 5 to 20 mm square, and to be present below the semiconductor chip fixing portion.

【0020】本発明で使用される熱硬化性樹脂組成物の
樹脂としては、一般に公知の熱硬化性樹脂が使用され
る。具体的には、エポキシ樹脂、多官能性シアン酸エス
テル樹脂、多官能性マレイミド−シアン酸エステル樹
脂、多官能性マレイミド樹脂、不飽和基含有ポリフェニ
レンエーテル樹脂等が挙げられる。これらを1種或いは
2種類以上を組み合わせて使用する。耐熱性、耐湿性、
耐マイグレーション性、吸湿後の電気的特性等の点から
多官能性シアン酸エステル樹脂組成物が好適である。
As the resin of the thermosetting resin composition used in the present invention, generally known thermosetting resins are used. Specific examples include an epoxy resin, a polyfunctional cyanate ester resin, a polyfunctional maleimide-cyanate ester resin, a polyfunctional maleimide resin, and a polyphenylene ether resin having an unsaturated group. These are used alone or in combination of two or more. Heat resistance, moisture resistance,
A polyfunctional cyanate resin composition is preferred in terms of migration resistance, electrical properties after moisture absorption, and the like.

【0021】本発明の好適な熱硬化性樹脂分である多官
能性シアン酸エステル化合物とは、分子内に2個以上の
シアナト基を有する化合物である。具体的に例示する
と、1,3-又は1,4-ジシアナトベンゼン、1,3,5-トリシア
ナトベンゼン、1,3-、1,4-、1,6-、1,8-、2,6-又は2,7-
ジシアナトナフタレン、1,3,6-トリシアナトナフタレ
ン、4,4-ジシアナトビフェニル、ビス(4-ジシアナトフ
ェニル)メタン、2,2-ビス(4-シアナトフェニル)プロ
パン、2,2-ビス(3,5-ジブロモ-4- シアナトフェニル)
プロパン、ビス(4-シアナトフェニル)エーテル、ビス
(4-シアナトフェニル)チオエーテル、ビス(4-シアナ
トフェニル)スルホン、トリス(4-シアナトフェニル)
ホスファイト、トリス(4-シアナトフェニル)ホスフェ
ート、およびノボラックとハロゲン化シアンとの反応に
より得られるシアネート類などである。
The polyfunctional cyanate compound which is a preferred thermosetting resin component of the present invention is a compound having two or more cyanato groups in a molecule. Specific examples include 1,3- or 1,4-dicyanatobenzene, 1,3,5-tricyanatobenzene, 1,3-, 1,4-, 1,6-, 1,8-, 2 , 6- or 2,7-
Dicyanatonaphthalene, 1,3,6-tricyanatonaphthalene, 4,4-dicyanatobiphenyl, bis (4-dicyanatophenyl) methane, 2,2-bis (4-cyanatophenyl) propane, 2,2- Bis (3,5-dibromo-4-cyanatophenyl)
Propane, bis (4-cyanatophenyl) ether, bis (4-cyanatophenyl) thioether, bis (4-cyanatophenyl) sulfone, tris (4-cyanatophenyl)
Phosphite, tris (4-cyanatophenyl) phosphate, and cyanates obtained by reacting novolak with cyanogen halide.

【0022】これらのほかに特公昭41-1928、同43-1846
8、同44-4791、同45-11712、同46-41112、同47-26853及
び特開昭51-63149号公報等に記載の多官能性シアン酸エ
ステル化合物類も用いられ得る。また、これら多官能性
シアン酸エステル化合物のシアナト基の三量化によって
形成されるトリアジン環を有する分子量400〜6,000のプ
レポリマーも使用できる。このプレポリマーは、上記の
多官能性シアン酸エステルモノマーを、例えば鉱酸、ル
イス酸等の酸類;ナトリウムアルコラート等、第三級ア
ミン類等の塩基;炭酸ナトリウム等の塩類等を触媒とし
て重合させることにより得られる。このプレポリマー中
には一部未反応のモノマーも含まれており、モノマーと
プレポリマーとの混合物の形態をしており、このような
原料は本発明の用途に好適に使用される。一般には有機
溶剤に溶解させて使用する。
In addition to these, Japanese Patent Publication Nos. 41-1928 and 43-1846
8, polyfunctional cyanate compounds described in JP-A-44-4791, JP-A-45-11712, JP-A-46-41112, JP-A-47-26853 and JP-A-51-63149 can also be used. Further, a prepolymer having a molecular weight of 400 to 6,000 and having a triazine ring formed by trimerization of a cyanato group of the polyfunctional cyanate compound can also be used. This prepolymer is obtained by polymerizing the above-mentioned polyfunctional cyanate ester monomer using, for example, an acid such as a mineral acid or a Lewis acid; a base such as a sodium alcoholate or a tertiary amine; a salt such as sodium carbonate as a catalyst. It can be obtained by: The prepolymer also contains some unreacted monomers and is in the form of a mixture of the monomer and the prepolymer, and such a raw material is suitably used for the purpose of the present invention. Generally, it is used after being dissolved in an organic solvent.

【0023】エポキシ樹脂としては、一般に公知のもの
が使用できる。具体的には、液状或いは固形のビスフェ
ノールA型エポキシ樹脂、ビスフェノールF型エポキシ
樹脂、フェノールノボラック型エポキシ樹脂、クレゾー
ルノボラック型エポキシ樹脂、脂環式エポキシ樹脂;ブ
タジエン、ペンタジエン、ビニルシクロヘキセン、ジシ
クロペンチルエーテル等の二重結合をエポキシ化したポ
リエポキシ化合物類;ポリオール、水酸基含有シリコン
樹脂類とエピハロヒドリンとの反応によって得られるポ
リグリシジル化合物類等が挙げられる。これらを1種或
いは2種類以上が組み合わせて使用する。
As the epoxy resin, a generally known epoxy resin can be used. Specifically, liquid or solid bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, alicyclic epoxy resin; butadiene, pentadiene, vinylcyclohexene, dicyclopentyl ether, etc. And polyglycidyl compounds obtained by reacting a polyol, a hydroxyl group-containing silicone resin with epihalohydrin, and the like. These may be used alone or in combination of two or more.

【0024】ポリイミド樹脂としては、一般に公知のも
のが使用され得る。具体的には、多官能性マレイミド類
とポリアミン類との反応物、特公昭57-005406 に記載の
末端三重結合のポリイミド類が挙げられる。
As the polyimide resin, generally known ones can be used. Specific examples include a reaction product of a polyfunctional maleimide and a polyamine, and a polyimide having a terminal triple bond described in JP-B-57-005406.

【0025】これらの熱硬化性樹脂は、単独でも使用さ
れるが、特性のバランスを考え、適宜組み合わせて使用
するのが良い。
These thermosetting resins can be used alone, but it is preferable to use them in an appropriate combination in consideration of the balance of properties.

【0026】本発明の熱硬化性樹脂組成物には、組成物
本来の特性が損なわれない範囲で、所望に応じて種々の
添加物を配合することができる。これらの添加物として
は、不飽和ポリエステル等の重合性二重結合含有モノマ
ー類及びそのプレポリマー類;ポリブタジエン、エポキ
シ化ブタジエン、マレイン化ブタジエン、ブタジエン−
アクリロニトリル共重合体、ポリクロロプレン、ブタジ
エン−スチレン共重合体、ポリイソプレン、ブチルゴ
ム、フッ素ゴム、天然ゴム等の低分子量液状〜高分子量
のエラスティックなゴム類;ポリエチレン、ポリプロピ
レン、ポリブテン、ポリ-4- メチルペンテン、ポリスチ
レン、AS樹脂、ABS 樹脂、MBS 樹脂、スチレン−イソプ
レンゴム、ポリエチレン−プロピレン共重合体、4-フッ
化エチレン-6- フッ化エチレン共重合体類;ポリカーボ
ネート、ポリフェニレンエーテル、ポリスルホン、ポリ
エステル、ポリフェニレンサルファイド等の高分子量プ
レポリマー若しくはオリゴマー;ポリウレタン等が例示
され、適宜使用される。また、その他、公知の無機或い
は有機の充填剤、染料、顔料、増粘剤、滑剤、消泡剤、
分散剤、レベリング剤、光増感剤、難燃剤、光沢剤、重
合禁止剤、チキソ性付与剤等の各種添加剤が、所望に応
じて適宜組み合わせて用いられる。必要により、反応基
を有する化合物は硬化剤、触媒が適宜配合される。
Various additives can be added to the thermosetting resin composition of the present invention, if desired, as long as the inherent properties of the composition are not impaired. These additives include polymerizable double bond-containing monomers such as unsaturated polyesters and prepolymers thereof; polybutadiene, epoxidized butadiene, maleated butadiene, butadiene-
Low molecular weight liquid to high molecular weight elastic rubbers such as acrylonitrile copolymer, polychloroprene, butadiene-styrene copolymer, polyisoprene, butyl rubber, fluororubber, and natural rubber; polyethylene, polypropylene, polybutene, poly-4- Methylpentene, polystyrene, AS resin, ABS resin, MBS resin, styrene-isoprene rubber, polyethylene-propylene copolymer, 4-fluoroethylene-6-fluoroethylene copolymers; polycarbonate, polyphenylene ether, polysulfone, polyester And high molecular weight prepolymers or oligomers such as polyphenylene sulfide; and polyurethane. In addition, other known inorganic or organic fillers, dyes, pigments, thickeners, lubricants, defoamers,
Various additives such as a dispersant, a leveling agent, a photosensitizer, a flame retardant, a brightener, a polymerization inhibitor, and a thixotropy-imparting agent are used in an appropriate combination as required. If necessary, the compound having a reactive group is appropriately blended with a curing agent and a catalyst.

【0027】本発明の熱硬化性樹脂組成物は、それ自体
は加熱により硬化するが硬化速度が遅く、作業性、経済
性等に劣るため使用した熱硬化性樹脂に対して公知の熱
硬化触媒を用い得る。使用量は、熱硬化性樹脂100重量
部に対して0.005〜10重量部、好ましくは0.01〜5重量部
である。
The thermosetting resin composition of the present invention can be cured by heating itself, but has a low curing rate and is inferior in workability and economic efficiency. Can be used. The amount used is 0.005 to 10 parts by weight, preferably 0.01 to 5 parts by weight, per 100 parts by weight of the thermosetting resin.

【0028】プリプレグの補強基材として使用するもの
は、一般に公知の無機或いは有機の織布、不織布が使用
される。具体的には、Eガラス、Sガラス、Dガラス等
の公知のガラス繊維布、全芳香族ポリアミド繊維布、液
晶ポリエステル繊維布等が挙げられる。これらは、混抄
でも良い。また、ポリイミドフィルム等のフィルムの表
裏に熱硬化性樹脂組成物を塗布、加熱して半硬化状態に
したものも使用できる。
As the reinforcing base material of the prepreg, generally known inorganic or organic woven or nonwoven fabric is used. Specific examples include known glass fiber cloths such as E glass, S glass, and D glass, wholly aromatic polyamide fiber cloths, and liquid crystal polyester fiber cloths. These may be mixed. Alternatively, a thermosetting resin composition applied to the front and back of a film such as a polyimide film and heated to a semi-cured state can be used.

【0029】最外層の金属箔としては、一般に公知のも
のが使用できる。好適には厚さ3〜100μmの銅箔、ニッ
ケル箔等が使用される。
As the outermost metal foil, generally known ones can be used. Preferably, a copper foil, a nickel foil or the like having a thickness of 3 to 100 μm is used.

【0030】金属板に形成するクリアランスホール径又
はスリット幅は、表裏導通用スルーホール径よりやや大
きめに形成する。具体的には、該スルーホール壁と金属
板クリアランスホール又はスリット孔壁とは50μm以上
の距離が、熱硬化性樹脂組成物で絶縁されていることが
好ましい。表裏導通用スルーホール径については、特に
限定はないが、50〜300μmが好適である。
The diameter of the clearance hole or the width of the slit formed in the metal plate is slightly larger than the diameter of the through hole for front / back conduction. Specifically, it is preferable that a distance of 50 μm or more between the through hole wall and the metal plate clearance hole or slit hole wall is insulated by the thermosetting resin composition. The diameter of the through-hole for front / back conduction is not particularly limited, but is preferably 50 to 300 µm.

【0031】本発明のプリント配線板用プリプレグを作
成する場合、基材に熱硬化性樹脂組成物を含浸、乾燥
し、半硬化状態の積層材料とする。また基材を使用しな
い半硬化状態とした樹脂シートも使用できる。或いは塗
料も使用できる。この場合、半硬化状態の程度により、
ハイフロー化、ローフロー化、或いはノーフロー化す
る。ノーフローとした場合には、加熱、加圧して積層成
形した時、樹脂の流れ出しが100μm以下、好ましくは5
0μm以下とする。また、この際、金属板、金属箔とは
接着し、ボイドの発生しないことが肝要である。プリプ
レグを作成する温度は一般的には100〜180℃である。時
間は5〜60分であり、目的とするフローの程度により、
適宜選択する。
When preparing a prepreg for a printed wiring board of the present invention, a substrate is impregnated with a thermosetting resin composition and dried to obtain a semi-cured laminated material. Also, a resin sheet in a semi-cured state without using a base material can be used. Alternatively, paints can be used. In this case, depending on the degree of the semi-cured state,
High flow, low flow, or no flow. In the case of no flow, when lamination molding is performed by heating and pressing, the flow of the resin is 100 μm or less, preferably 5 μm or less.
0 μm or less. At this time, it is important that the metal plate and the metal foil adhere to each other and no void is generated. The temperature at which the prepreg is made is generally between 100 and 180 ° C. The time is 5-60 minutes, depending on the degree of the desired flow
Select as appropriate.

【0032】本発明の金属芯の入った半導体プラスチッ
クパッケージを作成する方法は特に限定しないが、例え
ば図1および図2に示す以下の方法による。 (1)内層となる金属板a全面を液状エッチングレジス
トbで被覆し、加熱して溶剤を除去した後、半導体チッ
プを固定する箇所、反対面の金属円錐台形突起を形成す
る範囲のレジスト、及びクリアランスホール部以外のレ
ジスト全部を残し、 (2)エッチングにて金属板を所定厚み溶解した後、 (3)再びエッチングレジストを、表裏の突起として残
す部分に、小径の円形状として残す。 (4)上下から同一圧力のエッチング液でエッチングし
て、表裏面の円錐台形の突起c、及びクリアランスホー
ルdを形成してから、エッチングレジストを除去し、金
属板全面を化学表面処理する。 (5)表裏に、プリプレグ(図2のf)、樹脂シート、
樹脂付き金属箔、或いは塗布樹脂層を配置し、必要によ
り金属箔eを配置する。この場合、円錐台形の突起の先
端が、金属箔の厚みよりやや薄めに残るよう絶縁層を形
成する。 (6)加熱、加圧、真空下に積層成形した後、 (7)所定の位置にドリル等でスルーホールgを内層金
属板に接触しないようにあけ、スルーホールを金属メッ
キする。 (8)半導体チップkの搭載部、ワイヤボンディングパ
ッド、及び反対面のボールパッド部を除いてメッキレジ
ストlで被覆し、ニッケル、金メッキを施してから、半
導体チップを銀ペーストhで接着固定し、ワイヤボンデ
ィングしてから、樹脂封止jを行い、反対面のボールパ
ッド部にはハンダボールmを接合して、半導体プラスチ
ックパッケージとする。
The method of producing the semiconductor plastic package having the metal core of the present invention is not particularly limited. For example, the following method shown in FIGS. 1 and 2 is used. (1) After covering the entire surface of the metal plate a serving as the inner layer with the liquid etching resist b and removing the solvent by heating, the resist in a range where the semiconductor chip is fixed, the frustum of the metal cone on the opposite surface is formed, and (2) After the metal plate is melted to a predetermined thickness by etching, (3) the etching resist is left again as a small-diameter circular shape at the portions to be left as projections on the front and back surfaces. (4) Etching is performed from above and below with an etching solution having the same pressure to form a truncated cone-shaped projection c and a clearance hole d on the front and back surfaces, then remove the etching resist, and chemically treat the entire surface of the metal plate. (5) A prepreg (f in FIG. 2), a resin sheet,
A metal foil with resin or a coating resin layer is arranged, and a metal foil e is arranged as necessary. In this case, the insulating layer is formed such that the tips of the truncated cone-shaped protrusions remain slightly thinner than the thickness of the metal foil. (6) After laminating under heat, pressure, and vacuum, (7) A through hole g is drilled at a predetermined position with a drill or the like so as not to contact the inner metal plate, and the through hole is metal-plated. (8) Except for the mounting portion of the semiconductor chip k, the wire bonding pad, and the ball pad portion on the opposite surface, the semiconductor chip is covered with a plating resist 1 and plated with nickel and gold, and the semiconductor chip is bonded and fixed with a silver paste h. After wire bonding, resin sealing j is performed, and a solder ball m is bonded to the ball pad portion on the opposite surface to form a semiconductor plastic package.

【0033】[0033]

【実施例】以下に実施例、比較例で本発明を具体的に説
明する。尚、特に断らない限り、『部』は重量部を表
す。 実施例1 2,2-ビス(4-シアナトフェニル)プロパン900部、ビス
(4-マレイミドフェニル)メタン100部を150℃に熔融さ
せ、攪拌しながら4時間反応させ、プレポリマーを得
た。これをメチルエチルケトンとジメチルホルムアミド
の混合溶剤に溶解した。これにビスフェノールA型エポ
キシ樹脂(商品名:エピコート1001、油化シェルエポキ
シ〈株〉製)400部、クレゾールノボラック型エポキシ
樹脂(商品名:ESCN-220F 、住友化学工業〈株〉製)60
0部を加え、均一に溶解混合した。更に触媒としてオク
チル酸亜鉛0.4部を加え、溶解混合し、これに無機充填
剤(商品名:焼成タルクBST-200 、日本タルク〈株〉
製)500部を加え、均一攪拌混合してワニスAを得た。
このワニスを厚さ100μmのガラス織布に含浸、乾燥し
て、ゲル化時間(at170℃)50秒、170 ℃、20kgf/cm2、5
分間での樹脂流れ10mmとなるように作成した、絶縁層
の厚さ107μmの半硬化状態のプリプレグBを得た。
The present invention will be specifically described below with reference to examples and comparative examples. Unless otherwise specified, “parts” indicates parts by weight. Example 1 900 parts of 2,2-bis (4-cyanatophenyl) propane and 100 parts of bis (4-maleimidophenyl) methane were melted at 150 ° C. and reacted with stirring for 4 hours to obtain a prepolymer. This was dissolved in a mixed solvent of methyl ethyl ketone and dimethylformamide. 400 parts of bisphenol A type epoxy resin (trade name: Epicoat 1001, Yuka Shell Epoxy Co., Ltd.) and cresol novolak type epoxy resin (trade name: ESCN-220F, Sumitomo Chemical Co., Ltd.) 60
0 parts were added and uniformly dissolved and mixed. Further, 0.4 part of zinc octylate is added as a catalyst, dissolved and mixed, and an inorganic filler (trade name: calcined talc BST-200, Nippon Talc Co., Ltd.) is added.
Varnish A was obtained by mixing uniformly with stirring.
This varnish is impregnated into a glass woven cloth having a thickness of 100 μm, dried, and gelled (at 170 ° C.) for 50 seconds, 170 ° C., 20 kgf / cm 2 , 5 kg
A semi-cured prepreg B having an insulating layer thickness of 107 μm was prepared so that the resin flow per minute was 10 mm.

【0034】一方、内層金属板となる厚さ350μmのCu:
99.9 %、Fe:0.07 %、P:0.03%の合金板を用意し、上
下に液状エッチングレジストを25μm塗布、乾燥し、表
裏面には大きさ50mm角のパッケージとなる面積におい
て、のクリアランスホール部を除いて全てレジストが残
るように紫外線を照射して、1 %炭酸ナトリウム溶液で
クリアランスホール部分のレジストを溶解除去し、上下
からエッチングにて上下約65μm金属板を溶解した。エ
ッチングレジストを溶解除去後、再び液状のエッチング
レジストを付着させ、金属板上下の中央13mm角内に、幅
2mm間隔に、径300μmの円形のレジストが残るように
作成したネガフィルムを被せ、紫外線を照射後、未露光
の部分を1 %炭酸ナトリウム溶液で溶解除去し、両側か
らエッチングして、表裏面に高さ114μm、底部径620μ
m、上部径74μmの円錐台形の突起をそれぞれ25個作成
すると同時に、孔径0.6mmφのクリアランスホールを
あけた。金属板全面に黒色酸化銅処理を施し、この表裏
面に上記プリプレグBを置き、上下に12μmの電解銅箔
を配置して、200℃、20kgf/cm2 、30mmHg以下の真空下
で2時間積層成形し、一体化した。クリアランスホール
箇所は、クリアランスホール部の金属に接触しないよう
に、中央に孔径0.25mmのスルーホールをドリルにてあ
け、銅メッキを無電解、電解メッキで行い、孔内に17μ
mの銅メッキ層を形成した。表裏にエッチングレジスト
を付着してからポジフィルムを重ねて露光、現像し、表
裏回路を形成し、半導体チップ搭載部、ボンディングパ
ッド部及びボールパッド部以外にメッキレジストを形成
し、ニッケル、金メッキを施してプリント配線板を完成
した。表面の半導体チップ搭載部である円錐台形突起が
表面金属箔と接触している部分に、大きさ13mm角の半
導体チップを銀ペーストで接着固定した後、ワイヤボン
ディングを行い、次いでシリカ入りエポキシ封止用コン
パウンドを用い、半導体チップ、ワイヤ及びボンディン
グパッドを樹脂封止し、ハンダボールを接合して半導体
パッケージを作成した。この半導体プラスチックパッケ
ージをエポキシ樹脂マザーボードプリント配線板にハン
ダボールを熔融させて接合した。評価結果を表1に示
す。
On the other hand, a 350 μm-thick Cu:
Prepare a 99.9%, Fe: 0.07%, P: 0.03% alloy plate, apply 25μm of liquid etching resist on the upper and lower sides, and dry it. On the front and back sides, a clearance hole of 50mm square package area Irradiation was carried out so that all the resist except for the resist remained, the resist in the clearance hole portion was dissolved and removed with a 1% sodium carbonate solution, and the upper and lower metal plates of about 65 μm were dissolved by etching from above and below. After dissolving and removing the etching resist, a liquid etching resist is adhered again, and a width of
At 2 mm intervals, cover the negative film created so that a circular resist with a diameter of 300 μm remains, irradiate with ultraviolet light, dissolve and remove the unexposed parts with 1% sodium carbonate solution, etch from both sides, and apply on both sides Height 114μm, bottom diameter 620μ
m and 25 truncated conical projections each having an upper diameter of 74 μm were formed, and a clearance hole having a hole diameter of 0.6 mmφ was formed. Apply black copper oxide treatment on the entire surface of the metal plate, place the above prepreg B on the front and back surfaces, place 12 μm electrolytic copper foil on the top and bottom, and laminate at 200 ° C, 20 kgf / cm 2 , 30 mmHg or less vacuum for 2 hours Molded and integrated. Drill a 0.25mm diameter through hole in the center of the clearance hole so that it does not come into contact with the metal in the clearance hole, perform copper plating by electroless or electrolytic plating, and place 17μ in the hole.
m of the copper plating layer was formed. Attaching an etching resist on the front and back, overlaying a positive film, exposing and developing, forming a front and back circuit, forming a plating resist other than the semiconductor chip mounting part, bonding pad part and ball pad part, applying nickel and gold plating To complete the printed wiring board. A 13 mm square semiconductor chip is bonded and fixed with a silver paste on the surface where the truncated conical protrusion that is the semiconductor chip mounting part is in contact with the surface metal foil, wire bonding is performed, and then silica-filled epoxy sealing The semiconductor chip, wires, and bonding pads were resin-sealed using a compound for soldering, and solder balls were joined to form a semiconductor package. This semiconductor plastic package was bonded to an epoxy resin motherboard printed wiring board by melting solder balls. Table 1 shows the evaluation results.

【0035】実施例2 実施例1において、両面の円錐台形突起の高さを109μ
mとし、この台形上に銀ペーストを、高さ5μm付着さ
せ、プリプレグBを上下におき、その両外側に12μmの
電解銅箔を配置し、200℃、20kgf/cm2、30mmHg以下の真
空下で2時間積層成形して一体化した。後は同様にして
プリント配線板を作成し、半導体チップを接着、ワイヤ
ボンディングを行い、樹脂封止して半導体プラスチック
パッケージを得た。これを同様にエポキシ樹脂マザーボ
ードプリント配線板に接合した。評価結果を表1に示
す。
Example 2 In Example 1, the height of the truncated conical projections on both sides was 109 μm.
m, silver paste was deposited on this trapezoid, 5 μm in height, prepreg B was placed on the top and bottom, and 12 μm electrolytic copper foil was placed on both outer sides, 200 ° C., 20 kgf / cm 2 , and a vacuum of 30 mmHg or less. For 2 hours. Thereafter, a printed wiring board was prepared in the same manner, a semiconductor chip was bonded, wire-bonded, and resin-sealed to obtain a semiconductor plastic package. This was similarly joined to an epoxy resin motherboard printed wiring board. Table 1 shows the evaluation results.

【0036】比較例1 実施例1のプリプレグBを2枚使用し、上下に12μmの
電解銅箔を配置し、200℃、20kgf/cm2 、30mmHg以下の
真空下に2時間積層成形し、両面銅張積層板を得た。所
定の位置に孔径0.25mmφのスルーホールをドリルであ
け、デスミア処理後に銅メッキを施した。この板の上下
に公知の方法で回路を形成し、メッキレジストで被覆
後、ニッケル、金メッキを施した。これは半導体チップ
を搭載する箇所に放熱用のスルーホールが形成されてお
り、この上に銀ペーストで半導体チップを接着し、ワイ
ヤボンディング後、エポキシ封止用コンパウンドで実施
例1と同様に樹脂封止し、ハンダボールを接合した(図
3)。同様にマザーボードに接合した。評価結果を表1
に示す。
COMPARATIVE EXAMPLE 1 Two prepregs B of Example 1 were used, and 12 μm electrolytic copper foil was placed on the upper and lower sides, and laminated and molded at 200 ° C., 20 kgf / cm 2 , and a vacuum of 30 mmHg or less for 2 hours. A copper-clad laminate was obtained. A through hole having a hole diameter of 0.25 mmφ was drilled at a predetermined position, and copper plating was performed after desmear treatment. Circuits were formed on and under the plate by a known method, and were covered with a plating resist and then plated with nickel and gold. This has a through hole for heat dissipation formed at the place where the semiconductor chip is mounted. The semiconductor chip is adhered on this with a silver paste, and after wire bonding, it is sealed with a resin for epoxy sealing in the same manner as in Example 1. Then, the solder balls were joined (FIG. 3). Similarly joined to the motherboard. Table 1 shows the evaluation results.
Shown in

【0037】比較例2 エポキシ樹脂(商品名:エピコート5045)700部、及び
エポキシ樹脂(商品名:ESCN220F)300部、ジシアンジ
アミド35部、2-エチル-4- メチルイミダゾール1部をメ
チルエチルケトンとジメチルホルムアミドの混合溶剤に
均一溶解させ、これを厚さ100μmのガラス織布に含
浸、乾燥させて、ゲル化時間(at170℃)10秒、樹脂流れ
98μmのノーフロープリプレグ (プリプレグC)、ゲル
化時間150秒、樹脂流れ18mmのハイフロープリプレグ
(プリプレグD)を作成した。プリプレグDを2枚使用
し、190℃、20kgf/cm2 、30mmHg以下の真空下で2時間積
層成形し、両面銅張積層板を作成した。後は比較例1と
同様にしてプリント配線板を作成し、半導体チップ搭載
部分をザグリマシーンにてくり抜き、裏面に厚さ200μ
mの銅板を、上記ノーフロープリプレグCを打ち抜いた
ものを使用して、加熱、加圧下に同様に接着させ、放熱
板付きプリント配線板を作成した。これはややソリが発
生した。この放熱板に直接銀ペーストで半導体チップを
接着させ、ワイヤボンディングで接続後、液状エポキシ
樹脂で封止した (図4)。同様にマザーボードプリント
配線板に接合した。評価結果を表1に示す。
COMPARATIVE EXAMPLE 2 700 parts of an epoxy resin (trade name: Epicoat 5045), 300 parts of an epoxy resin (trade name: ESCN220F), 35 parts of dicyandiamide, and 1 part of 2-ethyl-4-methylimidazole were prepared by mixing methyl ethyl ketone and dimethylformamide. Uniformly dissolved in a mixed solvent, impregnated in a glass woven cloth with a thickness of 100 μm and dried, gelling time (at 170 ° C) for 10 seconds, resin flow
High flow prepreg with 98μm no-flow prepreg (prepreg C), gel time 150 seconds, resin flow 18mm
(Prepreg D) was prepared. Two prepregs D were laminated and molded at 190 ° C., 20 kgf / cm 2 and a vacuum of 30 mmHg or less for 2 hours to prepare a double-sided copper-clad laminate. Thereafter, a printed wiring board was prepared in the same manner as in Comparative Example 1, and the semiconductor chip mounting portion was cut out with a counterbore machine, and a thickness of 200 μm was formed on the back surface.
Using a punched-out Noflow prepreg C, a copper plate having a thickness of m was bonded in the same manner under heat and pressure to produce a printed wiring board with a heat sink. This slightly warped. A semiconductor chip was directly bonded to the heat sink with a silver paste, connected by wire bonding, and sealed with a liquid epoxy resin (FIG. 4). Similarly, it was joined to a motherboard printed wiring board. Table 1 shows the evaluation results.

【0038】 表 1 項 目 実 施 例 比 較 例 1 2 1 2 吸湿後の耐熱性1) 常 態 異常なし 異常なし 異常なし 異常なし 24hrs. 異常なし 異常なし 異常なし 異常なし 48hrs. 異常なし 異常なし 異常なし 異常なし 72hrs. 異常なし 異常なし 異常なし 異常なし 96hrs. 異常なし 異常なし 異常なし 一部剥離 120hrs. 異常なし 異常なし 一部剥離 一部剥離 144hrs. 異常なし 異常なし 一部剥離 一部剥離 168hrs. 異常なし 異常なし 一部剥離 一部剥離 吸湿後の耐熱性2) 常 態 異常なし 異常なし 異常なし 異常なし 24hrs. 異常なし 異常なし 一部剥離 一部剥離 48hrs. 異常なし 異常なし 剥離大 剥離大 72hrs. 異常なし 異常なし ワイヤ切れ ワイヤ切れ 96hrs. 異常なし 異常なし ワイヤ切れ ワイヤ切れ 120hrs. 異常なし 異常なし ワイヤ切れ ワイヤ切れ 144hrs. 異常なし 異常なし − − 168hrs. 異常なし 異常なし − − ガラス転移温度(℃) 234 234 234 160Table 1 Item Example Comparison Example 1 2 1 2 Heat resistance after moisture absorption 1) Normal No abnormality No abnormality No abnormality No abnormality No abnormality 24hrs. No abnormality No abnormality No abnormality No abnormality 48hrs. No abnormality No abnormality No abnormalities No abnormalities 72hrs. No abnormalities No abnormalities No abnormalities No abnormalities No abnormalities 96hrs. No abnormalities No abnormalities No abnormalities Partial peeling 120hrs. No abnormalities No abnormalities Partial peeling partial peeling 144hrs. No abnormalities No abnormalities Partial peeling Partial peeling 168hrs No abnormalities No abnormalities Partial peeling Partial peeling Heat resistance after moisture absorption 2) Normal No abnormalities No abnormalities No abnormalities No abnormalities No abnormalities 24hrs. No abnormalities No abnormalities Partial peeling Partial peeling 48hrs. No abnormalities No abnormalities Large peeling Large peeling large 72hrs. No abnormalities No abnormalities Wire breaks Wires 96hrs. No abnormalities No abnormalities Wire breaks Wires 120hrs. No abnormalities No abnormalities Wire breaks Wires 144hrs. No abnormalities No abnormalities -. 168Hrs No problem No - - Glass transition temperature (℃) 234 234 234 160

【0039】 表 1(続) 項 目 実 施 例 比 較 例 1 2 1 2 プレッシャークッカー 処理後の絶縁抵抗値 (Ω) 常 態 5×1014 5×1014 6×1014 5×1014 200hrs. 7×1012 6×1012 5×1012 5×108 500hrs. 6×1011 5×1011 3×1011 <108 700hrs. 5×1010 7×1010 5×1010 − 1000hrs. 2×1010 2×1010 1×1010 − 耐マイグレーション 性 (Ω) 常 態 6×1013 5×1013 5×1013 4×1013 200hrs. 5×1011 6×1011 4×1011 3×109 500hrs. 4×1011 4×1011 4×1011 <108 700hrs. 1×1011 2×1011 1×1011 − 1000hrs. 9×1010 1×1011 8×1010 − 放熱性(℃) 36 35 56 48 表面金属箔との接触 良好 非常に良好 − −[0039] Table 1 (Continued) Item implementation example comparisons Example 1 2 1 2 pressure cooker treatment after the insulation resistance (Omega) normal state 5 × 10 14 5 × 10 14 6 × 10 14 5 × 10 14 200hrs 7 × 10 12 6 × 10 12 5 × 10 12 5 × 10 8 500hrs. 6 × 10 11 5 × 10 11 3 × 10 11 <10 8 700hrs. 5 × 10 10 7 × 10 10 5 × 10 10 −1000hrs . 2 × 10 10 2 × 10 10 1 × 10 10 -. migration resistance (Omega) normal state 6 × 10 13 5 × 10 13 5 × 10 13 4 × 10 13 200hrs 5 × 10 11 6 × 10 11 4 × 10 11 3 × 10 9 500 hrs. 4 × 10 11 4 × 10 11 4 × 10 11 <10 8 700 hrs. 1 × 10 11 2 × 10 11 1 × 10 11 −1000 hrs. 9 × 10 10 1 × 10 11 8 × 10 10 -Heat dissipation (° C) 36 35 56 48 Good Contact with surface metal foil Very good--

【0040】<測定方法> 1)吸湿後の耐熱性1) JEDEC STANDARD TEST METHOD A113-A LEVEL3:30℃・60
%RHで所定時間処理後、220 ℃リフローソルダー3 サイ
クル後の基板の異常の有無について、断面観察及び電気
的チェックによって確認した。 2)吸湿後の耐熱性2) JEDEC STANDARD TEST METHOD A113-A LEVEL2:85℃・60
%RHで所定時間(Max.168hrs.)処理後、220℃リフロー
ソルダー3サイクル後の基板の異常の有無を断面観察及
び電気的チェックによって確認した。 3)ガラス転移温度 DMA 法にて測定した。 4)プレッシャークッカー処理後の絶縁抵抗値 端子間(ライン/スペース=70/70μm)の櫛形パターン
を作成し、この上に、それぞれ使用したプリプレグ、又
は樹脂層を形成し、加熱硬化させたものを、121℃・2気
圧で所定時間処理した後、25℃・60%RHで2時間後処理
を行い、500VDCを印加60秒後に、その端子間の絶縁抵抗
値を測定した。 5)耐マイグレーション性 上記4)の試験片を85℃・85%RH、50VDC 印加して端子
間の絶縁抵抗値を測定した。 6)放熱性 パッケージを同一マザーボードプリント配線板にハンダ
ボールで接着させ、1000時間連続使用してから、パッケ
ージの温度を測定した。 7)表面金属との接触 円錐台形突起部の断面を観察した。
<Measurement method> 1) Heat resistance after moisture absorption 1) JEDEC STANDARD TEST METHOD A113-A LEVEL3: 30 ° C, 60
After the treatment at% RH for a predetermined time, the presence or absence of abnormality in the substrate after three cycles of reflow soldering at 220 ° C was confirmed by cross-sectional observation and electrical check. 2) Heat resistance after moisture absorption 2) JEDEC STANDARD TEST METHOD A113-A LEVEL2: 85 ℃ ・ 60
After treatment at% RH for a predetermined time (Max. 168 hrs.), The presence or absence of abnormality in the substrate after three cycles of reflow soldering at 220 ° C. was confirmed by cross-sectional observation and electrical check. 3) Glass transition temperature Measured by the DMA method. 4) Insulation resistance after pressure cooker treatment A comb-shaped pattern was created between terminals (line / space = 70/70 μm), and the prepreg or resin layer used was formed on each of these patterns, and the resultant was cured by heating. After treatment at 121 ° C. and 2 atm for a predetermined time, post-treatment was performed at 25 ° C. and 60% RH for 2 hours, and after applying 500 VDC for 60 seconds, the insulation resistance value between the terminals was measured. 5) Migration resistance The test piece of the above 4) was applied at 85 ° C. and 85% RH at 50 VDC, and the insulation resistance between the terminals was measured. 6) Heat dissipation The package was adhered to the same motherboard printed wiring board with solder balls and used continuously for 1000 hours, and then the temperature of the package was measured. 7) Contact with surface metal The cross section of the truncated cone was observed.

【0041】[0041]

【発明の効果】本発明は、プリント配線板の厚さ方向の
ほぼ中央部に、プリント配線板とほぼ同じ大きさの金属
板を配置し、プリント配線板の片面に、少なくとも1 個
の半導体チップを熱伝導性接着剤で固定し、該金属板と
表面の回路とを多官能性シアン酸エステルのような熱硬
化性樹脂組成物で絶縁し、そのプリント配線板表面に形
成された回路導体と半導体チップとをワイヤボンディン
グで接続し、少なくとも該表面のプリント配線板上の信
号伝播回路導体と、プリント配線板の反対面に形成され
た回路導体もしくは該ハンダボールでの接続用導体パッ
ドとを、金属板と樹脂組成物で絶縁されたスルーホール
導体で結線し、少なくとも半導体チップ、ワイヤ、ボン
ディングパッドを樹脂封止している構造の半導体プラス
チックパッケージであって、該プリント配線板の一部を
構成する金属板の、半導体チップを直接固定する金属箔
裏側部分に、複数個の円錐台形の金属突起を形成し、こ
の先端部分を、半導体チップ搭載用金属箔と接触させ
る。好適には円錐台形上に熱伝導性接着剤を付着させ、
積層成形時に接着剤を溶融させて金属芯と表面の金属箔
を接合する。半導体チップを熱伝導性接着剤でこの半導
体搭載部に固定し、半導体チップから発生した熱をこの
金属板円錐台形突起部を通り、内層金属板に伝導し、金
属板裏側の円錐台形突起を通じて下側の金属箔に接続し
たハンダボールに逃がし、マザーボードプリント配線板
に拡散する構造とした半導体プラスチックパッケージを
提供する。本発明は半導体プラスチックパッケージを上
記構成とすることにより、熱放散性に優れ、半導体チッ
プの下面からの吸湿がなく、吸湿後の耐熱性、すなわち
ポップコーン現象が大幅に改善でき、加えて大量生産性
にも適しており、経済性の改善された、新規な構造の半
導体プラスチックパッケージを提供する。
According to the present invention, a metal plate having substantially the same size as a printed wiring board is disposed substantially at the center in the thickness direction of the printed wiring board, and at least one semiconductor chip is provided on one surface of the printed wiring board. Is fixed with a heat conductive adhesive, the metal plate and the circuit on the surface are insulated with a thermosetting resin composition such as a polyfunctional cyanate ester, and the circuit conductor formed on the surface of the printed wiring board and Connecting the semiconductor chip by wire bonding, at least a signal propagation circuit conductor on the printed wiring board on the surface, and a circuit conductor formed on the opposite surface of the printed wiring board or a connection conductor pad with the solder ball, A semiconductor plastic package having a structure in which at least a semiconductor chip, a wire, and a bonding pad are resin-sealed by connecting with a metal plate and a through-hole conductor insulated by a resin composition. A plurality of truncated-cone-shaped metal projections are formed on a metal plate constituting a part of the printed wiring board, on a metal foil back side for directly fixing a semiconductor chip. Contact with metal foil. Preferably, a heat conductive adhesive is deposited on the truncated cone,
At the time of lamination molding, the adhesive is melted to join the metal core and the surface metal foil. The semiconductor chip is fixed to this semiconductor mounting portion with a heat conductive adhesive, and the heat generated from the semiconductor chip passes through this metal plate frustoconical projection to the inner layer metal plate, and passes through the truncated conical projection on the back side of the metal plate. Provided is a semiconductor plastic package having a structure that escapes to a solder ball connected to a side metal foil and diffuses into a motherboard printed wiring board. According to the present invention, the semiconductor plastic package having the above-described configuration has excellent heat dissipation, does not absorb moisture from the lower surface of the semiconductor chip, and can significantly improve the heat resistance after moisture absorption, that is, the popcorn phenomenon, and can further improve mass productivity. The present invention provides a semiconductor plastic package having a novel structure, which is also suitable for an automobile and has improved economy.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施例1の半導体プラスチックパッケージの製
造工程図である。
FIG. 1 is a manufacturing process diagram of a semiconductor plastic package according to a first embodiment.

【図2】実施例1の半導体プラスチックパッケージの製
造工程図である。
FIG. 2 is a manufacturing process diagram of the semiconductor plastic package of the first embodiment.

【図3】比較例1の半導体プラスチックパッケージの製
造工程図である。
FIG. 3 is a manufacturing process diagram of the semiconductor plastic package of Comparative Example 1.

【図4】比較例2の半導体プラスチックパッケージの製
造工程図である。
FIG. 4 is a manufacturing process diagram of a semiconductor plastic package of Comparative Example 2.

【符号の説明】[Explanation of symbols]

a 金属板 b エッチングレジスト c 金属円錐台形突起 d クリアランスホール e 金属箔 f プリプレグB g 表裏回路導通用スルーホール h 銀ペースト i ボンディングワイヤ j 封止樹脂 k 半導体チップ l メッキレジスト m ハンダボール n 放熱用スルーホール o プリプレグC a Metal plate b Etching resist c Metal frustoconical projection d Clearance hole e Metal foil f Pre-preg B g Through-hole for front and back circuit conduction h Silver paste i Bonding wire j Sealing resin k Semiconductor chip l Plating resist m Solder ball n Heat radiation through Hall o Prepreg C

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 プリント配線板の厚さ方向のほぼ中央部
に、プリント配線板とほぼ同じ大きさの金属板を配置
し、プリント配線板の片面に少なくとも1個の半導体チ
ップを熱伝導性接着剤で固定し、該金属板とプリント配
線板表面の信号伝播回路導体とを熱硬化性樹脂組成物で
絶縁し、該回路導体と半導体チップとをワイヤボンディ
ングで接続し、少なくともプリント配線板表面上の該回
路導体と、プリント配線板の反対面に形成された回路導
体もしくは該パッケージを外部とハンダボールで接続す
るために形成された回路導体パッドとを、金属板と樹脂
組成物で絶縁されたスルーホール導体で結線し、少なく
とも半導体チップ、ワイヤ、ボンディングパッドを樹脂
封止している構造の半導体プラスチックパッケージにお
いて、 該プリント配線板の一部を構成する金属板に複数個の円
錐台形の金属突起を、半導体チップを直接固定する金属
箔と接触させ、必要により熱伝導性接着剤で該突起部を
金属箔に接触させ、該突起が接触している表面の半導体
チップ搭載用金属箔上に熱伝導性接着剤で半導体チップ
を固定し、半導体チップ固定面の反対面にも複数個の金
属円錐台形突起を裏面の金属箔と同じように接続するよ
うに形成していることを特徴とする半導体プラスチック
パッケージ。
1. A metal plate having substantially the same size as a printed wiring board is disposed at a substantially central portion in a thickness direction of the printed wiring board, and at least one semiconductor chip is thermally conductively bonded to one surface of the printed wiring board. The metal plate and the signal transmission circuit conductor on the surface of the printed wiring board are insulated with a thermosetting resin composition, and the circuit conductor and the semiconductor chip are connected by wire bonding. The circuit conductor and the circuit conductor formed on the opposite surface of the printed wiring board or the circuit conductor pad formed for connecting the package to the outside with solder balls were insulated by a metal plate and a resin composition. In a semiconductor plastic package having a structure in which at least a semiconductor chip, a wire, and a bonding pad are resin-sealed by connecting through a through-hole conductor, A plurality of truncated cone-shaped metal projections are brought into contact with a metal foil directly fixing a semiconductor chip on a metal plate constituting a part of the plate, and the projections are brought into contact with the metal foil with a heat conductive adhesive as necessary, The semiconductor chip is fixed with a heat conductive adhesive on the semiconductor chip mounting metal foil on the surface where the projections are in contact, and a plurality of metal truncated cone-shaped projections are also formed on the back surface of the metal foil on the opposite side of the semiconductor chip fixing surface A semiconductor plastic package formed so as to be connected in the same manner as described above.
【請求項2】 該金属板が、銅95重量%以上の銅合金、
或いは純銅である請求項1記載の半導体プラスチックパ
ッケージ。
2. The method according to claim 1, wherein the metal plate is a copper alloy containing 95% by weight or more of copper.
2. The semiconductor plastic package according to claim 1, wherein the semiconductor plastic package is pure copper.
【請求項3】 該絶縁樹脂組成物が、多官能性シアン酸
エステル、該シアン酸エステルプレポリマーを必須成分
とする熱硬化性樹脂組成物である請求項1または2記載
の半導体プラスチックパッケージ。
3. The semiconductor plastic package according to claim 1, wherein the insulating resin composition is a thermosetting resin composition containing a polyfunctional cyanate ester and the cyanate ester prepolymer as essential components.
JP14520898A 1919-04-03 1998-05-12 Semiconductor plastic package Expired - Fee Related JP3985342B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP14520898A JP3985342B2 (en) 1998-05-12 1998-05-12 Semiconductor plastic package
US09/237,840 US6097089A (en) 1998-01-28 1999-01-27 Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
TW088101289A TW401725B (en) 1998-01-28 1999-01-28 Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
EP99300654A EP0933813A2 (en) 1998-01-28 1999-01-28 Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
KR1019990002682A KR19990068179A (en) 1998-01-28 1999-01-28 Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package
US09/583,148 US6265767B1 (en) 1919-04-03 2000-05-30 Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14520898A JP3985342B2 (en) 1998-05-12 1998-05-12 Semiconductor plastic package

Publications (2)

Publication Number Publication Date
JPH11330304A true JPH11330304A (en) 1999-11-30
JP3985342B2 JP3985342B2 (en) 2007-10-03

Family

ID=15379900

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14520898A Expired - Fee Related JP3985342B2 (en) 1919-04-03 1998-05-12 Semiconductor plastic package

Country Status (1)

Country Link
JP (1) JP3985342B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020025106A (en) * 2012-02-07 2020-02-13 株式会社ニコン Imaging unit and imaging apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020025106A (en) * 2012-02-07 2020-02-13 株式会社ニコン Imaging unit and imaging apparatus

Also Published As

Publication number Publication date
JP3985342B2 (en) 2007-10-03

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