JPH11326948A - Active matrix substrate and electrooptic panel equipped with same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent dieleetric breakdowns of various kinds of wires, elements, etc., during and after the manufacture by using a protection pattern with respect to in an active matrix substrate for a liquid crystal panel etc. SOLUTION: Each pixel is provided with a positive stagger type TFT (thin film transistor) for pixel driving. The protection pattern 16 made of a semiconductor film includes at least some of 1st protection pattern parts 16a which are arrayed on the substrate 10 in a pixel display region 11 along scanning lines and 2nd protection pattern parts 16b which are arrayed at a display region edge part, has the resistance prescribed by the density of impurities of ion injection into a semiconductor film, and is so constituted that static electricity accumulated on the scanning lines 12 are made to be easier to flow than on data lines 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter referred to as "T") for driving various wirings on a substrate such as a glass substrate.
FT) and the like, and belongs to the technical field of an active matrix substrate for an electro-optical panel such as a liquid crystal panel on which a liquid crystal panel or the like is formed.
It belongs to the technical field of an active matrix substrate having a function of preventing electrostatic breakdown at T or the like. The invention further provides:
It belongs to the technical field of an electro-optical panel having this.

[0002]

2. Description of the Related Art Conventionally, an active matrix substrate constituting an electro-optical panel such as a liquid crystal panel of a TFT active matrix driving type or an EL (electroluminescence) panel has various wirings and T-type substrates on a glass substrate or a quartz substrate.
An FT, an insulating film and the like are formed. In this case, static electricity is generated during the manufacture of the active matrix substrate. When high-voltage static electricity is generated, for example, TF for liquid crystal panel
In the case of a T active matrix substrate, the gate wiring (scanning line), the source wiring (data line), the TFT, the interlayer insulating film between the wiring and the element, and the like may be electrostatically damaged.
Here, when a certain wiring is charged with the electric charge Q, the voltage is V = Q / C (where C: capacitance), and therefore, if the capacitance C of the wiring increases, the voltage decreases. Moreover, even if such static electricity is generated between wirings that are electrically short-circuited with each other, no voltage is naturally applied. Therefore, as a countermeasure against electrostatic breakdown, there are electrically short-circuited wiring portions that may cause electrostatic breakdown, a voltage V at the time of generation of static electricity is reduced by increasing a capacitance C of the wiring, a charge generated on the substrate. However, it is possible to consider a method of making a structure in which the wiring portion is hardly charged.

Therefore, conventionally, a TF which is not a driver built-in type is used.
In the case of a T-active matrix substrate, Japanese Patent Laid-Open No.
As disclosed in JP-A-116573, JP-A-63-106788, etc., short-circuiting or short-circuiting between wires to which a high voltage, which is commonly called a short ring or a guard ring, may be applied. There has been proposed a conductive pattern wiring that connects with a large resistance and increases the capacitance of the wiring. Alternatively, a large-capacity, large-area dummy pattern is formed in the substrate to reduce the amount of generated static electricity charged to the wiring / elements without being electrically connected to the wiring. In some cases, a conductive protection pattern wiring for preventing the occurrence may be provided. In the present specification, these are collectively referred to simply as “protection patterns”.

However, in order to prevent electrostatic breakdown during actual manufacturing, there is a basic requirement that such a protective pattern be provided at an early stage of the manufacturing process. There is also a basic requirement that the protective pattern must be cut and removed so that the liquid crystal panel can operate normally at the latest during the electrical inspection stage during the manufacturing process when the LCD panel is short-circuited and at the latest after the manufacturing process. is there. For example, an inverted stagger type TFT
In the case of a TFT active matrix substrate provided in each pixel, the protection pattern is formed from a film made of a metal or a semiconductor constituting a scanning line (gate wiring) located at a relatively lower layer formed at an early stage of manufacturing, Before the TFT active matrix substrate is connected to a driving circuit, preferably, the driving element and various wirings are cut and removed before electrical inspection is performed.

As a protection pattern of the type proposed to meet such two basic requirements, Japanese Patent Laid-Open No. 2-24 / 1990
229, JP-A-7-181516, and JP-A-7-175086. That is, along the edge of the board outside the mounting terminals, all the data lines and the scanning lines are configured to be short-circuited via the mounting terminals. Then, the individual active matrix substrate is separated from the substrate along a separation line called a scribe line (in this specification,
At the time of polishing (hereinafter simply referred to as "panel chamfering" in the specification of the present application) at the time of polishing the panel end surface after cutting (hereinafter simply referred to as "substrate cutting"), each wiring is separated from this protection pattern. Be separated. In this way, the cutting and removing of the protection pattern can be delayed until each wiring is cut off by the protection pattern, so that electrostatic breakdown in the latter half of the assembly process can be prevented. Further, as an application of the first type, as disclosed in Japanese Patent Application Laid-Open Nos. Hei 4-301519 and Hei 8-101397, a method of forming a TFT between adjacent TFT active matrix substrates provided on a large substrate is disclosed. There is also a protection pattern wired in a zigzag manner across a substrate cutting line so that a short circuit of the protection pattern is eliminated by cutting with a single substrate cutting line.

However, when applying the above-mentioned method to a TFT active matrix substrate for a liquid crystal panel or the like with a built-in driver, a large number of TFTs and wirings constituting a driver portion are provided with scanning lines (gate wirings). It is formed around the image display area from an interlayer insulating film or the like, such as a film made of the same metal or semiconductor as the above, or a metal film such as Al (aluminum) same as the data line (source wiring). For this reason, for example, it is practically possible to form the above-described first protection pattern from the same metal or semiconductor film as the scanning line or the same metal film as the data line from the driver portion of the substrate to the edge side. Impossible. That is, in any of the above-described first formats, the scanning lines and the data lines provided in the image display area on the center side of the substrate when viewed two-dimensionally are connected. It is impossible to route a wiring for a protection pattern that extends over a driver portion provided in a peripheral area such as a line drive circuit to the edge of the substrate. In addition, this method has a problem in that the protection pattern is cut and removed during the manufacturing, so that it is ineffective for electrostatic breakdown in the subsequent manufacturing steps.

As means for solving these problems, Japanese Patent Application Laid-Open No. 63-085586 and Japanese Patent Application Laid-Open No. 2-06
As disclosed in JP-A-1618, JP-A-6-273778, JP-A-8-179360,
When a voltage is applied through the data line and the scanning line, the pixel can be lit to some extent or the data line, the scanning line,
Materials having a high resistance to a certain extent that can be electrically inspected such as TFTs, for example, Si (silicon), ITO (indium.
Data line, even if it is composed of high resistance material such as tin oxide) or mainly composed of low resistance material.
There has been proposed a type in which a high-resistance material or a high-resistance non-linear element is separately sandwiched between a scanning line and the like. According to the second type of protection pattern, it is not necessary to cut and remove the protection pattern until after the electrical inspection step in the course of manufacturing, so that electrostatic breakdown can be prevented from occurring before the manufacturing step. By leaving the protection pattern even on the product, it is possible to omit the cutting and removing step and also to prevent electrostatic breakdown at the product stage. In particular, Japanese Patent Application Laid-Open No. 63-085586 discloses a technique in which a protection pattern is formed on an active matrix substrate using silicon as a high resistance material, and the resistance value is adjusted by the line width of the protection pattern. I have.

[0008]

However, in the case where a protection pattern for connecting the wirings with a certain resistance is formed by a silicon film, the protection pattern can be inspected or even finally completed as a product. In order to prevent the inspection or the original operation from being hindered without cutting and removing, and to have a sufficient electrostatic breakdown prevention function, the resistance value applied between the wirings is determined within a narrow range, and the silicon film As long as the specific resistance and the film thickness are constant, the degree of freedom in the shape and line width is extremely low.

Further, if the capacitance of the protection pattern overlapping with the wiring becomes large, the protection pattern may cause the drive signal delay of the wiring and hinder the operation of the active matrix substrate. The shape of the protection pattern is significantly restricted, and the function of preventing electrostatic breakdown must be insufficient.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has an active matrix substrate for an electro-optical panel such as a liquid crystal panel capable of preventing electrostatic breakdown in various wirings and TFTs, and an electro-optical substrate having the same. The task is to provide a panel.

[0011]

According to a first aspect of the present invention, there is provided an active matrix substrate including a plurality of pixel electrodes formed in a matrix and connected to the plurality of pixel electrodes. A plurality of first protection patterns having a thin film transistor, a data line and a scanning line connected to the thin film transistor, and arranged along the plurality of scanning lines in an image display area in which the pixel electrode is formed; And at least one of a second protection pattern portion arranged along the periphery of the image display region. The protection pattern is a protection pattern for preventing electrostatic breakdown, which is ion-implanted into the semiconductor film. It is characterized by being.

According to the first aspect of the present invention, the first protection pattern portion formed of a semiconductor film such as a polysilicon film is arranged on the substrate along a plurality of scanning lines in the image display area. Have been. The second protection pattern portion, also formed of a semiconductor film, is arranged along the outer periphery of the display area and is connected to the first protection pattern portion. Since the specific resistance of the protection pattern including the first and second protection pattern portions is defined by the concentration of the impurity ion-implanted into the semiconductor film, the resistance value can be adjusted without changing the line width and shape. is there.

Further, the resistance of the protection pattern is defined by the concentration of impurities implanted into the semiconductor film.

In the case of the positive stagger type, both the first interlayer insulating film and the second interlayer insulating film are interposed between the protection pattern formed of these semiconductor films and the data lines, and thus the data line is interposed therebetween. The capacitance is relatively small, and even if the area of the intersection with the data line is relatively large, the driving of the data line is hardly practically delayed by the parasitic capacitance. A protection pattern can be formed. For this reason, the static electricity generated on the substrate is easily charged by the protection pattern, and the electric capacity of the protection pattern is also increased. Prepare.

As a result, it is possible to reduce the probability that the various thin films constituting the TFT, the data lines, the scanning lines, the interlayer insulating films and the like become defective due to electrostatic breakdown. Furthermore, since the resistance of the protection pattern itself is defined by the concentration of the impurity to be ion-implanted, a desired resistance can be easily obtained as compared with the case where the resistance is defined by the line width. In addition to this, the ion implantation process is used as a manufacturing process of a positive stagger type TFT, and since this ion implantation process is performed at the early stage of manufacturing where the possibility of electrostatic breakdown is low, the ion implantation process for the protection pattern is not performed. It is sufficient to perform the implantation at the same stage as the ion implantation process for the TFT.

Furthermore, even if the first protection pattern portion is provided in the image display area, the semiconductor layer made of polysilicon or the like basically transmits light, so that the transmittance of the active matrix substrate hardly decreases. At the same time, in the voltage state of the active matrix substrate during normal operation, current hardly flows through the first interlayer insulating film interposed between the scanning line and the first protection pattern portion. Therefore, the protection pattern including the first protection pattern portion is:
Since it can be left after the completion of the active matrix substrate, there is no need to cut and remove it during manufacturing. In other words, the step of cutting and removing the protection pattern can be omitted, and furthermore, it is useful for preventing electrostatic breakdown in various wirings and TFTs after completion.

As described above, according to the active matrix substrate of the first aspect, the insulating film interposed between the semiconductor layer and the data line and the positive staggered T type called ion implantation.
By maximizing the inherent properties of FT manufacturing, electrostatic damage during and after manufacturing can be prevented very efficiently. Further, the step of forming the protection pattern can be performed relatively easily, and the presence of the protection pattern does not hinder the electrical inspection or cause image deterioration during normal operation, which is very advantageous.

According to a second aspect of the present invention, in the active matrix substrate, at least one of the first and second protection pattern portions is more likely to cause dielectric breakdown due to static electricity accumulated in the scanning lines than the second interlayer insulating film. The method may further include an electrostatic path portion that overlaps or is disposed close to the scan line via the first interlayer insulating film so as to occur in the first interlayer insulating film, and the first interlayer film is thinner than the second interlayer film. It is characterized by the following.

According to the active matrix substrate of the second aspect, the static electricity path portion included in the first protection pattern portion is overlapped with or close to the scanning line via the first interlayer insulating film. The dielectric breakdown due to the static electricity accumulated in the scanning line in the static electricity passage portion occurs before the data line. The first interlayer insulating film interposed between the first protection pattern portion and the scanning line is a positive stagger type TFT.
In general, the thickness is not more than 1000 angstroms, and is generally thinner than the second interlayer film having a thickness of not less than 3000 angstroms. Therefore, it is not generally necessary to change the structure or add a new process to make the first interlayer film thinner than the second interlayer film. By simply arranging them so as to overlap with or close to the scanning lines via the interface, it is possible to easily obtain the configuration in which the static electricity accumulated in the scanning lines flows more easily into the first protection pattern portion than the data lines as described above. As described above, by utilizing the difference between the film thicknesses of the first interlayer insulating film and the second interlayer insulating film and the order of film formation, a configuration for reliably preventing electrostatic breakdown during and after manufacturing can be easily obtained. .

The active matrix substrate according to a third aspect of the present invention is the active matrix substrate according to the second aspect, wherein the static electricity passage portion is at least partially removed from other portions of the protection pattern except for the static electricity passage. Also, the semiconductor device is characterized in that the impurity concentration is low and the resistance is high.

According to the third aspect of the present invention, the electrostatic path portion is formed at least partially with a lower impurity concentration and a higher resistance than other portions of the protection pattern. Also, when the protection pattern and the scanning line are conducted, it is possible to prevent the failure due to conduction between the protection pattern and the scanning line, and to further reduce the coupling capacitance between the scanning line and the first protection pattern portion.
Moreover, it is relatively easy to increase the resistance of the static electricity passage portion by the ion implantation process.

According to a fourth aspect of the present invention, in the active matrix substrate according to the first aspect, the first protection pattern portion is connected to the scanning line such that static electricity accumulated in the scanning line flows. And a static electricity passage portion having a lower concentration of the impurity and a higher resistance than other portions of the protection pattern.

According to the active matrix substrate of the fourth aspect, the static electricity passage portion included in the protection pattern portion is connected to the scanning line through the contact hole opened in the first interlayer film. The charged charges flow into the protection pattern. In addition, since the static electricity path portion is formed at least partially with a lower impurity concentration and higher resistance than other portions of the protection pattern, the delay of the scanning line signal is small and the original operation is not hindered.

According to a fifth aspect of the present invention, in the active matrix substrate according to any one of the first to fourth aspects, the protection pattern is arranged along an edge of the substrate. A third protection pattern portion, wherein the first and second protection pattern portions are connected to the third protection pattern portion.

According to the active matrix substrate described in claim 5, the third protection pattern portion is arranged along the edge of the active matrix substrate, and the third protection pattern portion has the first and second protection patterns. Since the pattern portion is connected, the electric capacity of the protection pattern increases according to the capacitance of the third protection pattern portion provided using the area along the edge of the substrate, and the function of preventing electrostatic breakdown is improved. I do. In addition, when a plurality of active matrix substrates are formed on a large-sized substrate, if the third protection pattern is connected between adjacent active matrix substrates, the electrostatic discharge prevention function is further enhanced due to the increase in capacitance. improves.
The third protection pattern may be formed of a semiconductor film like the first protection pattern and the second protection pattern, or may be formed of a conductor film on which a scanning line, a data line, or a pixel electrode is formed. .

According to a sixth aspect of the present invention, in the active matrix substrate according to any one of the first to fifth aspects, the second protection pattern includes a plurality of scanning lines and data lines. One or both of them are connected via a contact hole opened in an interlayer insulating film near an intersection with the wiring.

According to the active matrix substrate of the present invention, when the protection pattern portion is connected to a scanning line, the protection pattern portion is formed through a contact hole opened in the first interlayer film.
Further, when connected to the data line, it is connected to at least one of the scanning line and the data line through a contact hole opened in the first interlayer film and the second interlayer film, and the connected wiring is charged. The charge flows into the second protection pattern. Thus, it is possible to prevent the electrostatic breakdown of the interlayer insulating film or the active matrix element due to the electrostatic charge on the data line, and the second protection pattern is formed at least partially with a low impurity concentration and high resistance. Therefore, the resistance between the wirings is formed to such an extent that the original operation of the active matrix substrate is not hindered, and the original operation is not hindered.

The active matrix substrate according to claim 7 is the active matrix substrate according to any one of claims 1 to 6, wherein the first protection pattern includes the plurality of data lines and the image display area. In the above, the first and second interlayer insulating films are connected to each other through contact holes opened in the first and second interlayer insulating films.

According to the active matrix substrate described in claim 7, the protection pattern portion is formed by the first interlayer film and the second interlayer film.
The data lines are connected to the plurality of data lines through contact holes opened in the interlayer film, and the electric charges charged in the connected data lines flow into the first protection pattern. Thereby, it is possible to prevent the electrostatic breakdown of the interlayer insulating film or the active matrix element due to the electrification of the data line, and to form the first protection pattern at least partially with a low impurity concentration and a high resistance. Therefore, the resistance between the wirings is formed to such an extent that the original operation of the active matrix substrate is not disturbed, and the original operation is not disturbed.

An active matrix substrate according to an eighth aspect of the present invention is the active matrix substrate according to the fifth to seventh aspects, wherein a driver for supplying a scanning signal and a data signal to the plurality of scanning lines and data lines, respectively. A circuit and a mounting terminal unit for supplying a signal to the driver circuit are further provided around the image display area, the third protection pattern unit is arranged so as to bypass the driver circuit, and It is characterized in that it includes a portion formed so that a terminal is also connected.

According to the active matrix substrate of the eighth aspect, the driver circuit is provided around the image display area, and further includes a drive IC for supplying various signals and power for driving the driver circuit. A mounting terminal portion for connection is provided. Then, a third protection pattern portion connected to the first protection pattern or the second protection pattern and connected to an edge of the substrate bypassing the driver circuit is formed, and the mounting terminal portion is formed by the third protection pattern. Is also connected.

Therefore, the capacity of the third protection pattern can be increased by utilizing the space on the board between the driver circuit and the edge of the board, and the capacity of the entire protection pattern is increased, thereby further improving the electrostatic discharge protection function. Enhanced.

According to a ninth aspect of the present invention, in the active matrix substrate according to the fifth to eighth aspects, the third protection pattern is used when the active matrix substrate is cut or the cut end surface is polished after the cutting. The third protection pattern portion is at least partially formed at a position where the third protection pattern portion is cut off when the substrate is cut or the panel is chamfered so that an interconnected state is eliminated.

According to the active matrix substrate of the ninth aspect, the third protection pattern portion is at least partially cut off when cutting the substrate or chamfering the panel. Then, the interconnection state of the plurality of scanning lines and data lines by the third protection pattern is eliminated. Therefore, if the third protection pattern is not separated, an electrical inspection after manufacturing, a lighting operation after being commercialized into an electro-optical panel, or the like, may be caused by a short circuit by the third protection pattern or connection with a predetermined resistance. Even if the resistance of the third protection pattern is set low enough to prevent normal operation, the third protection pattern is cut off during substrate cutting or panel chamfering, so that no problem occurs. That is, by reducing the resistance of the protection pattern during manufacture to this level, the function of preventing electrostatic breakdown during manufacture can be further enhanced. And this third
Separation of the protection pattern can be performed relatively easily without increasing the number of steps by a substrate cutting step or a cut end surface polishing treatment step.

According to a tenth aspect, in the active matrix substrate according to the ninth aspect, the third protection pattern portion is separated from the active matrix substrate when the substrate is cut. And a portion extending zigzag along one substrate cutting line between the active matrix substrate and another adjacent active matrix substrate.

According to the active matrix substrate of the tenth aspect, the third protection pattern portion includes a portion extending zigzag along one substrate cutting line between the adjacent active matrix substrates. With respect to the matrix substrate, the third protection pattern portion can be separated at a time only by a substrate cutting process along one substrate cutting line. As described above, the third protection pattern portion can be cut and removed relatively easily without increasing the number of steps by the substrate cutting step.

An eleventh aspect of the present invention provides an electro-optical panel including the active matrix substrate according to any one of the first to tenth aspects, and a counter substrate disposed to face the active matrix substrate. It is characterized by.

According to the electro-optical panel according to the eleventh aspect, the defective product rate due to electrostatic breakdown during and after manufacturing is significantly low. Further, the electrical inspection is performed with high accuracy and high reliability, and the original function of the electro-optical panel is hardly or not impaired by the presence of the protection pattern, and the cost is reduced. I have.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of Active Matrix Substrate) First, as an embodiment of the active matrix substrate of the present invention, the configuration of an active matrix substrate for a liquid crystal panel will be described with reference to FIGS. I do. The plan view of FIG. 1 shows a state in which a plurality of active matrix substrates 1 of the present embodiment are formed in a matrix on a single large glass substrate. The active matrix substrate 1 in this state is subjected to a substrate cutting step of separating the substrate along a substrate cutting line indicated by a dotted line in the drawing, and further, a panel chamfering step is performed as necessary, so that each active matrix substrate is separated. It is a substrate. FIG. 2 shows FIG.
A pixel electrode in each pixel portion in the image display area of
It is the enlarged view which expanded and showed the structure of FT, various wiring, etc. FIG. 3 is a sectional view taken along line AA ′ of FIG.
(A) is an example of the protection pattern, BB ′ in FIG. 2.
FIG. 4B is a cross-sectional view of another example of the protection pattern taken along line BB ′ of FIG.

In FIG. 1, an active matrix substrate 1 includes a substrate 10 made of a glass substrate, a quartz substrate, or the like. A pixel electrode for driving a liquid crystal and a pixel electrode for driving a liquid crystal are provided on an image display area 11 located on the center side of the substrate 10. A plurality of pixel portions each including a TFT (see FIG. 2) are formed in a matrix. The active matrix substrate 1 includes a plurality of scanning lines (gate lines) 12 connected to the gates of TFTs in a plurality of pixel portions and a plurality of data lines (source lines) 13 connected to the sources of the TFTs. The scanning line 12 and the data line 13 are TAB (tape automated) provided along a substrate cutting line shown by a dotted line in the figure.
Each of the terminals is connected to a plurality of mounting terminals 19 such as bonding pads.

In the present embodiment, the active matrix substrate 1 further includes a plurality of first protection pattern portions 16a arranged on the substrate 10 along a plurality of scanning lines 12 in the image display area 11, and a plurality of first protection pattern portions 16a. A second protection pattern portion 16b interconnecting the protection pattern portion 16a around the image display area 11 and a second protection pattern portion 16b are provided along the edge of the substrate 10 to connect a plurality of mounting terminals to each other and via a connection wiring 16d. The protection pattern 16 includes a third protection pattern portion 16c connected to the first and second protection pattern portions. The protection patterns 16a and 16b are made of a polysilicon film as an example of a semiconductor film forming a TFT in the pixel portion. On the other hand, the protection pattern portions 16c and 16d may be made of the same polysilicon film. For example, the protection pattern portions 16c and 16d may be made of the same film as the scanning line 12, and may be connected to the protection patterns 16a and 16b through contact holes opened in the first interlayer film. It may be electrically connected.

As shown in FIG. 2, in the image display area 11, pixel portions including the TFT 30 and the pixel electrode 26 are formed in a matrix. The TFT 30 has the scanning line 12
(Gate electrode wiring) Polysilicon film 3 disposed opposite to the gate insulating film and functioning as a channel formation region
Including 1.

As shown in FIG. 3, the TFT 30 includes a polysilicon film 31 as an example of a semiconductor film and a gate insulating film 3.
3, a scanning line 12 (gate electrode wiring) including a gate electrode film such as low-resistance polysilicon, a second interlayer insulating film 42, and a data including a source electrode film such as a metal film such as Al. The lines 13 are stacked on the substrate 10 in this order, and are configured as a positive stagger type pixel driving TFT 30. A relay film 2 such as a metal film of Al or the like is provided on the drain of the TFT 30 through a contact hole.
5, and the pixel electrode 26 is connected. The pixel electrode 26 is made of, for example, an ITO (Indium Tin Oxide) film.

Here, a specific manufacturing process of the positive stagger type TFT 30 will be described. That is, first, the polysilicon film 31 is formed by, for example, forming an a-Si (amorphous silicon) film on the substrate 10 and then performing an annealing process to crystallize the film to a thickness of about 500 to 2,000 angstroms. At this time, an n-channel TFT
In the case of 30, Sb (antimony), As (arsenic),
An impurity (dopant) of a group V element such as P (phosphorus) is ion-implanted into the contact portions of the source / drain electrodes.
In the case of a p-channel type TFT 30, an II such as B (boron), Ga (gallium), or In (indium) is used.
An impurity (dopant) of a group I element is ion-implanted into the contact portion of the source / drain electrode. In particular, when the TFT 30 is an n-channel TFT having an LDD (Lightly Doped Drain) structure, the P-type polysilicon film 31 has a V region such as P in a part of the source region and the drain region adjacent to the channel side, respectively. A low-concentration doped region is formed by ion-implanting an impurity of a group element at a low concentration. Similarly, a high-concentration doped region is formed by ion-implanting an impurity of a group V element such as P at a high concentration. In the case of forming the p-channel TFT 30, an impurity of a group III element such as B is ion-implanted into the n-type polysilicon film 31 to form a source region and a drain region. Thus L
In the case of the DD structure, there is obtained an advantage that off-state current can be reduced and operation reliability can be improved. The TFT 30 is an LD
A TFT having an offset structure in which the low-concentration doped region in the D structure is a non-doped region may be used, or high-concentration source and drain regions are formed in a self-aligned manner by ion-implanting high-concentration impurities using the gate electrode as a mask. A self-aligned TFT may be used.

As described above, the positive stagger type TFT 30
Is formed using an ion implantation process before the formation of the second interlayer insulating film 42.

As shown in FIG. 2 and FIG. 4 (A) or (B), the first protection pattern portions 16 a are arranged on the substrate 10 along the scanning lines 12. First protection pattern section 16
The resistance of the protection pattern 16 including a is defined by the concentration of an impurity ion-implanted into the polysilicon film. In other words, the higher the concentration of the ion-implanted impurity, the lower the resistance, and the lower the concentration, the higher the resistance.
In particular, the protection pattern 16 is formed by the first protection pattern portion 16a and the electrostatic path portion 1 that protrudes in a corner state below the scanning line 12.
By having 6e, static electricity accumulated in the scanning line 12 is configured to flow more easily than the data line 13.

In the example shown in FIG. 4A, the first protection pattern portion 16a is arranged so as to overlap the scanning line 12 via the first interlayer insulating film 41 in the electrostatic path portion 16e. Here, in particular, the first interlayer insulating film 41 interposed between the first protection pattern portion 16a and the scanning line 12 is generally thin because it is the only gate insulating film in the positive stagger type TFT 30. That is, the first interlayer insulating film 41 is formed to have a thickness of, for example, about 300 to 1000 angstroms, and is interposed between the data line 13 and the scanning line 12 and has a thickness of, for example, about 3000 angstroms. It is formed thinner than 42. Therefore, simply arranging the first protection pattern portion 16a so as to overlap the scanning line 12 with the first interlayer insulating film 41 interposed therebetween causes the static electricity accumulated in the scanning line 12 to be more than the data line 13 by the static electricity. A configuration that easily flows into the protection pattern portion 16a can be easily obtained. For this reason, even if static electricity accumulates in the scanning line 12 (gate electrode film) and a high voltage is generated between the scanning line 12 and the data line 13, the electrostatic breakdown is more likely to occur in the TFT 30 connected between the two and between the two. Previously, electrostatic breakdown occurs between the scanning line 12 and the first protection pattern portion 16a via the first interlayer insulating film 41 and the electrostatic passage portion 16e.

As a result, according to the present embodiment, TF
Various thin films constituting T30, data line 13, scanning line 1
2. It is possible to prevent the interlayer insulating films 41 to 43 from becoming defective due to electrostatic breakdown.

Further, since the resistance of the protection pattern 16 itself is defined by the concentration of the impurity to be ion-implanted, a desired resistance can be easily obtained as compared with the case where the resistance is defined by the line width. Accordingly, the protection path 16 itself and the portion of the first interlayer insulating film 41 between the first protection pattern section 16a and the scanning line 12 are partially made to have a high resistance so that the electrostatic path section 16e does not become defective at the time of electrostatic breakdown. On the other hand, even when the protection pattern 16c is made of a polysilicon film, it is possible to set the resistance sufficiently low.

In addition to this, the ion implantation step is used as a manufacturing step of the positive stagger type TFT 30 as described above, and furthermore, this ion implantation step is performed at the initial stage of manufacturing with a low possibility of electrostatic breakdown, that is, This is performed after the formation of the gate electrode wiring (scanning line 12) and before the formation of the second interlayer insulating film 42 and the source electrode wiring (data line 13).
It is sufficient to perform the same steps as the ion implantation step for 0. This is extremely advantageous in manufacturing.

On the other hand, even before the ion implantation, although the resistance is relatively high, since the protection pattern 16 has already been formed from the polysilicon film, the function of preventing electrostatic breakdown is exhibited to some extent.

Further, at a position where the data line 13 overlaps (intersects) the first protection pattern portion 16a provided in the image display area 11, a portion between the data line 13 and the first protection pattern portion 16a is provided. Are relatively far apart with the first interlayer insulating film 41 and the second interlayer insulating film 42 interposed therebetween, so that the parasitic capacitance of the data line 13 generated with the first protection pattern portion 16a is only slight, The driving of the data line 13 is practically hardly delayed due to the parasitic capacitance.

Furthermore, even if the first protection pattern portion 16a is provided in the image display area 11, the polysilicon film is basically transparent, and the transmittance is not greatly reduced. At the same time, even though high-voltage static electricity from the scanning line 12 may flow in due to electrostatic breakdown (dielectric breakdown), the first protection pattern portion 16a scans in the voltage state of the active matrix substrate 1 during normal operation. First interlayer insulating film 41 interposed between line 12 and first protection pattern portion 16a
And the current hardly flows. Therefore, the first protection pattern portion 16a and the second protection pattern 16b can be left after the completion of the active matrix substrate 1, so that there is no need to cut and remove the same during manufacturing. On the other hand, the lower-resistance protection pattern 16c that needs to be removed in order to perform the original operation is automatically cut when the substrate is cut. That is,
It is not necessary to newly provide a step of cutting and removing the protection pattern 16, and it is also useful for preventing electrostatic damage in various wirings and the TFT 30 after completion.

In the examples shown in FIGS. 3 and 4A, depending on conditions such as the thickness of the first interlayer insulating film 41 (for example, when the first interlayer insulating film 41 is thinner). ,
A similar effect can be obtained by disposing the static electricity passage 16e in proximity to the scanning line 12 instead of below the scanning line 12.

On the other hand, in the example shown in FIG. 4B, the static electricity passage portion 16e 'is provided via a contact hole formed in the first interlayer insulating film 41 so that static electricity accumulated in the scanning line 12' flows in. The protection pattern 16 is connected to the scanning line 12 ′ and has a lower impurity concentration than the other portions of the protection pattern 16 and is formed to have high resistance. With this configuration, the scanning line 1
Even when high voltage static electricity is generated in the 2 ', the static electricity passage 1
A high current can flow into the first protection pattern section 16a via 6e ', and the delay of the drive signal required for the original operation of the panel can be minimized.

In the present embodiment, in particular, as shown in FIG. 1, the third protection pattern portion 16c is arranged along the edge of the substrate 10, and the third protection pattern portion 16c is connected to the third protection pattern portion 16c via the connection wiring 16d. Since the first protection pattern portion 16a and the second protection pattern portion 16b are connected to each other, the protection pattern 16 is provided in accordance with the capacity of the third protection pattern portion 16c provided by using an area along the edge of the substrate 10. Increases the capacity for static electricity. Therefore, the function of the protection pattern 16 for preventing electrostatic breakdown is improved. Moreover, in the present embodiment, a plurality of active matrix substrates 1 are formed on a large-sized substrate, and the third protection patterns 16c are connected between adjacent active matrix substrates 1. Greatly increases, and the capacity increase further improves the electrostatic discharge protection function of each protection pattern 16.

In this embodiment, in particular, as shown in FIG. 1, the plurality of mounting terminals 19 are provided along the edge of the substrate 10 and relatively high-concentration ion implantation is performed.
That is, they are connected to each other by the third protection pattern portion 16c having a lower resistance. Therefore, the scanning line 12 and the data line 13 directly connected to the mounting terminal 19 are connected to the mounting terminal 1.
9 can be connected by a third protection pattern portion 16c with a short circuit or a low resistance. After the protection pattern 16 including the third protection pattern portion 16c is thus formed, the capacitance with respect to the electrostatic charge increases (therefore, the voltage V = Q / C decreases) and the plurality of scanning lines 12 and data lines 13 are formed. Since the connection is made by short-circuiting or by a predetermined resistance, electrostatic breakdown of the scanning line 12, the data line 13, the TFT 30 of the pixel portion, the pixel electrode 26, the interlayer insulating films 41 to 43, and the like can be prevented. Moreover, since the protection pattern 16 is formed relatively early in the manufacturing process as described above, the function of preventing electrostatic breakdown can be made more reliable.

In the present embodiment, the TFT 30 in the first protection pattern portion 16a and each pixel portion disposed in the image display area 11 has the configuration shown in FIG. The configuration of the first protection pattern portion 16a that makes it easier to flow than the data line 13 is not limited to this.

That is, as shown in FIG.
The polysilicon film 31 ′ functioning as a channel formation region of 0 ′ has a double gate structure for improving off-characteristics, and the first protection pattern portion 16 a ′ follows the protruding shape of the polysilicon layer 31 ′. It may be configured to have a shape. Even with this configuration, the same effect as in the above-described case can be obtained.

In this embodiment, the active matrix substrate 1 is not of the type with a built-in driver, but may be configured as an active matrix substrate with a built-in driver.

That is, as shown in FIG. 6, a scanning line driving circuit 14 for supplying a scanning signal to the scanning line 12 and a data line driving circuit 15 for supplying a data signal to the data line 13 are connected to the substrate 10.
It may be provided around the upper image display area. Even with such a configuration, a plurality of first protection pattern portions 16a are provided along a plurality of scanning lines 12, and the plurality of first protection pattern portions 16a are provided.
By connecting the protection pattern portions 16a to each other at the second protection pattern portion 16b around the image display area,
The same electrostatic destruction prevention function as in the above case can be obtained. In this case, the connection wiring 16d connected to the first protection pattern section 16a and the second protection pattern section 16b is provided with a plurality of mounting terminals 19 'for inputting various signals to the scanning line driving circuit 14 and the data line driving circuit 16. Wiring 16 from
Along with d ′, it is connected to a large-capacity section such as the third protection pattern section 16c shown in FIG. 1, and the capacity of the entire protection pattern is secured. Here, in addition to a circuit for directly supplying a data signal during a normal operation of a liquid crystal panel completed by incorporating the active matrix substrate 1, a precharge for raising the data line 13 to a predetermined potential before supplying the data signal is performed. A precharge circuit for supplying a signal, a sampling circuit for sampling an analog image signal and supplying it to the data line 13, an inspection circuit for supplying a predetermined electric signal to the data line 13 at the time of electrical inspection of the circuit and wiring, etc. ,
A circuit related to an operation of supplying an electric signal to the data line is generically referred to as a data line driving circuit 15.

In this embodiment, particularly, as shown in FIG. 1, when the active matrix substrate 1 is cut off at the time of substrate cutting or panel chamfering, the mutual short-circuit between the scanning lines 12 and the data lines 13 due to the protection pattern 16 is eliminated. As described above, the third protection pattern portion 16c having a relatively low resistance is
It is at least partially formed at a position where it is cut off when cutting a substrate or chamfering a panel. Therefore, when cutting the active matrix substrate 1 or chamfering the panel, the mutual short-circuit between the scanning lines 12 and the data lines 13 due to the protection pattern 16 is eliminated. Therefore, if the third protection pattern 16c is not cut off, an electrical inspection after manufacturing, a lighting operation after being manufactured into an electro-optical panel, and the like, may be caused by a short circuit by the protection pattern 16 or a connection with a predetermined resistance. Even if the resistance of the protection pattern 16 is set low enough to prevent normal operation, the third protection pattern 16c is actually cut off without any problem. That is, by reducing the resistance of the protection pattern 16 during manufacture to this level, the function of preventing electrostatic breakdown during manufacture can be further enhanced. Moreover, the third protection pattern 16c can be relatively easily separated by a substrate cutting step or a panel chamfering step without increasing the number of steps.

In the present embodiment, as shown in FIG. 1, since the semiconductor device is configured to be separated along the substrate cutting line indicated by the dotted line, two adjacent active matrix substrates 1 are separated from each other. There is a need for a book substrate cutting line. However, the configuration may be such that one substrate cutting line is sufficient between the adjacent active matrix substrates 1.

That is, as shown in FIG. 7, the third protection pattern portion 16c 'is connected to an adjacent active matrix substrate 1' which is separated from the active matrix substrate 1 'at the time of cutting the substrate. (Shown by dotted line)
May be configured to include a portion that extends in a zigzag along the line. With this configuration, between the adjacent active matrix substrates 1 ′, only the substrate cutting process along one substrate cutting line is performed, and the scanning lines 12 and the data lines 13 are formed.
Can be cut off (cut off) at a time. As described above, the protection pattern can be cut and removed relatively easily without increasing the number of steps by the substrate cutting step. After the substrate is cut, for example, by supplying an electric signal to the scanning line 12 or the data line 13 via the mounting terminal 19 or an inspection terminal (not shown), the scanning line 12 or the data line 13, the TFT 30 of the pixel portion, or the like is provided. An electrical test is performed at

(Second Embodiment of Active Matrix Substrate) Next, a second embodiment of the active matrix substrate will be described with reference to FIG. FIG. 8 is a cross-sectional view (a cross-sectional view of the data line 13 as viewed in the longitudinal direction) at a position where the first protection pattern portion and the data line intersect in the image display area. In FIG. 8, the same components as those in FIG. 3 in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

The planar shape of the active matrix substrate of the second embodiment is the same as that of the first embodiment shown in FIG.

In the second embodiment, as shown in FIG.
3 (see FIG. 1), the plurality of first protection pattern portions 16 a ″ arranged on the substrate 10 are respectively formed on the first interlayer insulating film 41 and the second interlayer insulating film 42 at the locations where the data lines 13 intersect. A plurality of opened contact holes 41
It is connected to the data line 13 via a ′ and 42a ′. The high resistance portion 16g of the first protection pattern portion 16a ″ connected to the data line 13 is formed to have a lower impurity concentration and higher resistance than other portions of the protection pattern.

Accordingly, even if static electricity is generated in the data line 13, the static electricity is generated before the electrostatic breakdown occurs between the scanning line 12 and the data line 13 or the like.
And 42a 'to the first protection pattern portion 16a ". For this reason, various thin films constituting the TFT 30,
The data lines 13, the scanning lines 12, the interlayer insulating films 41 to 43, and the like can be prevented from becoming defective due to electrostatic breakdown.

Further, the resistance of the protection pattern itself can be adjusted by the concentration of the impurity to be ion-implanted, and a desired resistance can be easily obtained as compared with the case where the resistance is defined by the line width. Accordingly, static electricity from the data line 13 is increased while the resistance between the data lines 13 is increased so that the resistance between the data lines does not deteriorate during lighting or electrical inspection. Contact hole 41
a ′ and 42a ′ via the first protection pattern portion 16a ″.
The resistance can be adjusted to the extent that it flows reliably.

Further, the first protection pattern portion 16a ″ has
Although high-voltage static electricity may flow from the data line 13 through the contact holes 41a 'and 42a', the effective current is reduced by the presence of the high-resistance portion 16g in the voltage state during normal operation of the active matrix substrate. It hardly flows. Therefore, the protection pattern is left even after the completion of the active matrix substrate. As described above, according to the second embodiment, it is possible to omit the step of cutting and removing the protection pattern, and it is also useful to prevent electrostatic breakdown in various wirings and TFTs after completion.

In the present embodiment, various modifications are possible as in the case of the first embodiment.

(Embodiment of Liquid Crystal Panel) Next, an embodiment of a liquid crystal panel as an example of the electro-optical panel of the present invention will be described with reference to FIGS. 9 is a plan view of the liquid crystal panel as viewed from the counter substrate side, and FIG. 12 is a cross-sectional view taken along the line HH ′.

As shown in FIGS. 9 and 10, the liquid crystal panel includes an active matrix substrate according to the present invention in which various wirings and elements are formed on a substrate 10;
Opposing substrate 20 made of a glass substrate or the like arranged opposite to
A sealing material 52 for mutually bonding the substrate 10 and the opposing substrate 20 along the contour of the image display area 11, and a liquid crystal 5 sealed between the substrate 10 and the opposing substrate 20 by the sealing material 52.
0 is provided.

The scanning line driving circuit 14, the data line driving circuit 15, the mounting terminals 19, and a plurality of wirings 105 for connecting these are provided outside the sealing material 52. In at least one of the corners of the opposing substrate 20, the TFT array substrate 10 and the opposing substrate 2
Upper and lower conductive material (silver dot) for establishing electrical continuity with 0
106 is provided.

In FIG. 10, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material 52 is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the two substrates 10 and 20 around the periphery thereof, and sets a distance between the two substrates (a gap between the substrates) to a predetermined value. A gap material (spacer) such as glass fiber or glass beads for obtaining a value is mixed.

Since the liquid crystal panel configured as described above includes the above-described active matrix substrate of the present invention, the defective rate due to electrostatic breakdown during and after manufacturing is remarkably low. Moreover, the electrical inspection is performed with high accuracy and the reliability is high.

[0079]

According to the active matrix substrate of the present invention, a protection pattern including a first protection pattern portion provided along a scanning line in an image display area and a third protection pattern portion provided at an edge of the substrate is provided. Since static electricity generated on the substrate flows, it is possible to prevent electrostatic breakdown of various wirings and TFTs in a pixel portion during and after manufacturing. Moreover, by using a protection pattern made of a semiconductor film and capable of adjusting the resistance by ion implantation, it is possible to prevent the protection pattern itself from being defective due to static electricity, and to prevent electrostatic breakdown after manufacturing.

Further, the electro-optical panel of the present invention has a remarkably low defective rate due to electrostatic breakdown, is capable of performing an electrical inspection with high accuracy, and has a protective pattern to provide the original function of the active matrix substrate. Is scarcely or not harmed, and the cost is reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of an active matrix substrate according to a first embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a pixel portion of the active matrix substrate of FIG. 1;

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a cross-sectional view (FIG. 4A) of an example of a pixel portion taken along line BB ′ in FIG. 2 and FIG.
FIG. 4B is a sectional view (FIG. 4B).

FIG. 5 is an enlarged plan view showing a modification of the pixel portion of the active matrix substrate of FIG.

FIG. 6 is a plan view showing a configuration of an active matrix substrate according to a modification of the first embodiment.

FIG. 7 is a plan view showing a configuration of an active matrix substrate according to another modification of the first embodiment.

FIG. 8 is a cross-sectional view at an intersection where a data line and a protection pattern are connected in an active matrix substrate according to a second embodiment of the present invention.

FIG. 9 is a plan view of an embodiment of the liquid crystal panel of the present invention.

FIG. 10 is a sectional view taken along line H-H ′ of FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Active matrix substrate 10 ... Substrate 11 ... Image display area 12 ... Scan line 13 ... Data line 14 ... Scan line drive circuit 15 ... Data line drive circuit 16 ... Protective pattern 19 ... Mounting terminal 20 ... Counter substrate 26 ... Pixel electrode 30 ... TFT in the pixel portion 31... Polysilicon film 41... First interlayer insulating film 41 a. Contact hole 42... Second interlayer insulating film 42 a.

Claims (12)

[Claims] 1. A pixel comprising: a plurality of pixel electrodes formed in a matrix; a thin film transistor connected to the plurality of pixel electrodes; a data line and a scanning line connected to the thin film transistor; At least one of the plurality of first protection pattern portions arranged along the plurality of scanning lines and the second protection pattern portion arranged along the periphery of the image display region in an image display region in which electrodes are formed. Wherein the protection pattern is a protection pattern for preventing electrostatic destruction, which is ion-implanted into the semiconductor film. 2. The active matrix substrate according to claim 1, wherein the protection pattern has a resistance defined by a concentration of an impurity ion-implanted into the semiconductor film. 3. The first or second protection pattern section,
At least one of the scan lines passes through the first interlayer insulating film so that dielectric breakdown due to static electricity accumulated in the scan lines occurs in the first interlayer insulating film before the second interlayer insulating film occurs. 2. The active matrix substrate according to claim 1, further comprising an electrostatic path portion overlapping or disposed in close proximity, and wherein the first interlayer film is thinner than the second interlayer film. 4. The static electricity passage portion, wherein the impurity concentration is lower than that of the other portion of the protection pattern except at least part of the static electricity passage, and is formed to have high resistance. An active matrix substrate according to item 1. 5. The first protection pattern portion is connected to the scanning line in the image display area so that static electricity accumulated in the scanning line flows therein and is at least partially higher than other portions of the protection pattern. The active matrix substrate according to claim 1, further comprising an electrostatic passage having a low impurity concentration and a high resistance. 6. The protection pattern further includes a third protection pattern portion disposed along an edge of the substrate.
The active matrix substrate according to claim 1, wherein the first and second protection pattern portions are connected to the protection pattern portion. 7. The second protection pattern portion is formed so as to connect at least one of the plurality of scanning lines and the data lines to each other through a plurality of contact holes formed in the first interlayer insulating film. In the protection pattern, the impurity concentration is appropriately defined by the ion implantation step at least between each adjacent contact hole so as to provide a predetermined resistance between the plurality of scanning lines and the data lines. The active matrix substrate according to claim 1, wherein the active matrix substrate includes a bent portion. 8. The plurality of data lines in the display region are interconnected by the first protection pattern portion through a plurality of contact holes formed in the first interlayer insulating film and the second interlayer insulating film, respectively. The protection pattern has an appropriate impurity concentration by the ion implantation step at least between each adjacent contact hole so as to provide a predetermined resistance between the plurality of data lines. 8. The active matrix substrate according to claim 1, wherein the active matrix substrate includes a portion defined in (1). 9. A driver circuit for supplying a scanning signal and a data signal to the plurality of scanning lines and data lines, respectively, and a mounting terminal for supplying a signal to the driver circuit are provided around the image display area. 9. The device according to claim 5, wherein the third protection pattern portion includes a portion formed to bypass the driver circuit portion and to connect a mounting terminal portion. 10. Active matrix substrate. 10. The third protection pattern portion is configured such that when the active matrix substrate is cut off at the time of substrate cutting or panel chamfering, the interconnection state of the plurality of scanning lines and data lines by the protection pattern is eliminated. ,
10. The active matrix substrate according to claim 5, wherein the active matrix substrate is formed at least partially at a position where the substrate is cut off when the substrate is cut or the panel is chamfered. 11. The third protection pattern portion is zigzag along one substrate cutting line between the active matrix substrate and another active matrix substrate adjacent to the active matrix substrate which is separated from the active matrix substrate at the time of cutting the substrate. The active matrix substrate according to claim 9, further comprising a portion extending in the direction. 12. An electro-optical panel, comprising: the active matrix substrate according to claim 1; and a counter substrate disposed to face the active matrix substrate.