JPH1131779A - Memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system, wherein a memory chip is mounted in high density, and a mounting operation and repair work are easily performed. SOLUTION: This system comprises a small outline dual inline memory module (SO-DIMM) substrate 111, a memory module 10, and a controller 13. On both surfaces of the SO-DIMM substrate 11, two memory modules 10 are mounted, respectively. Each memory module 10 is mounted on the SO-DIMM substrate 11 by LCC(leadless chip carrier) method. Further, for the memory module 10, four memory bare chips cut out from a semiconductor wafer are COB-mounted on a module substrate without being packaged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory system in which a plurality of memory chips such as a motherboard and a memory board are mounted.

[0002]

2. Description of the Related Art Recent computer equipment has a slot for mounting a memory board inside the equipment so that a memory can be easily added. This slot has S
IMM (Single Inline Memory Module) and DIMM
It is common to mount a standardized memory board such as (Dual Inline Memory Module).

[0003]

However, the external dimensions of memory boards such as SIMMs and DIMMs are predetermined by standards in order to ensure compatibility, and it is necessary to mount memory ICs within the range of these standards. There is. Further, the size of the memory IC is generally determined depending on the type of the package, and the number of memory ICs that can be mounted on the memory board cannot be increased without limit. For this reason, it is common to increase the memory capacity by mounting the memory IC on both sides or mounting the memory IC in two layers.

For example, FIG. 22 is a diagram showing an example in which memory ICs are mounted in a two-tiered manner on a memory substrate. As shown in the figure, if the memory ICs 101 are mounted in two layers, a memory capacity twice as large as that obtained when the memory ICs 101 are not stacked can be obtained. However, since the structure is complicated, manufacturing takes time and trouble. Also increases.

On the other hand, recently, various LSIs such as CPU
Are mounted in a bare state without packaging, and as a mounting method in this case, COB mounting, flip chip mounting, or the like is often used. Since the bare chip has a much smaller outer dimension than the packaged chip, high-density mounting is possible.

However, in COB mounting, since it is necessary to perform the mounting operation while heating by applying a heater to the back side of the chip mounting surface, it is technically difficult to perform double-sided mounting, and the expected memory capacity is obtained. I can't. On the other hand, since each chip is mounted in a bare state, the failure rate of the memory substrate increases, and replacement work (repair work) when a failure occurs is troublesome because the chip is small.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory system which can mount a memory chip at a high density and can easily perform a mounting operation and a repair operation. Is to do.

[0008]

In order to solve the above-mentioned problems, a memory system according to the present invention comprises a plurality of memory chips cut from a semiconductor wafer mounted in a bare chip state without being packaged. Are mounted on a printed wiring board. Therefore, a plurality of memory chips can be easily mounted on each memory module, and the memory capacity of the memory system can be increased. Also, the number of connection terminals can be greatly reduced as compared with the case where the memory chip is directly mounted on a printed wiring board, and the mounting work becomes easier. Further, when a part of the memory chips becomes defective, the repair work can be performed in units of memory modules, so that the entire memory system does not have to be treated as defective, and the yield of products is improved.

In particular, by mounting two memory modules on each side of the printed wiring board, a total of four memory modules can be mounted. For example, when four memory chips are mounted on each memory module, Since 16 memory chips can be mounted in the entire memory system, the overall memory capacity can be increased.

[0010] Further, by mounting the above-described memory modules at positions facing each other with a printed wiring board therebetween, high-density mounting becomes possible as compared with COB mounting, which is difficult to mount on both sides.

Further, in the memory system of the present invention, a noise removing capacitor is mounted in correspondence with the memory module mounted on the printed wiring board, so that a noise countermeasure for a memory chip inside the memory module can be performed. In particular, by providing one capacitor for every two memory chips, the number of capacitors can be reduced.

In the memory system of the present invention, a controller for checking the operation of the memory chip is mounted on a printed wiring board, and even if the capacity of the entire memory system is increased, the controller checks the operation of the processor. There is no increase in burden.

Further, the memory system of the present invention has external connection terminals for exchanging signals with each of the memory chips, and can be easily mounted on a motherboard, a memory board, or the like.

The memory system of the present invention can realize a large-capacity SO-DIMM when a printed wiring board having a shape conforming to the SO-DIMM standard is considered. In addition, when a motherboard of a computer device is considered as a printed wiring board, a memory module can be directly mounted on the motherboard, so that a dedicated memory board is not required and cost can be reduced.

Further, the vertical and horizontal 2
By mounting the memory chips one by one, a module substrate having a memory capacity four times the memory chip can be obtained.
By mounting two rectangular memory chips on the module substrate with the long sides adjacent to each other on the module substrate, the external dimensions of the module substrate can be reduced. By regularly arranging the memory chips on the module substrate in such a state, it is possible to reduce the waste of the mounting space of each memory module and increase the mounting density,
The memory capacity of the entire memory system can be increased.

In the memory system of the present invention, a pad row including a plurality of board pads is formed in at least one row on a module board of each memory module, and memory chips are mounted on both sides of the pad row. By concentrating the substrate pads on the module substrate between the chips, the area occupied by the entire substrate pads can be reduced as compared with the case where the substrate pads are separately formed on both sides of the memory chip.

In particular, a pad row consisting of a plurality of chip pads is formed along the long side of the memory chip, and each pad row is parallel to the pad row consisting of a plurality of substrate pads on the module substrate. By arranging the memory chip, the distance between the chip pad and the substrate pad to be connected becomes substantially constant, so that it is suitable for connection using a bonding wire.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a memory system to which the present invention is applied will be specifically described with reference to the drawings.

FIG. 1 is a view schematically showing a memory system according to the present embodiment. FIG. 1A shows one surface of a substrate and FIG.
(B) has shown the other surface, respectively. 1 is a SO-DIMM (Small Outline Dual Inl).
ine Memory Module), and two rectangular memory modules 10 are mounted on both sides of the SO-DIMM board 11. The above-described SO-DIMM board 11 corresponds to a printed wiring board.

FIG. 2 is an enlarged plan view showing the memory module 10, FIG. 3 is a sectional view taken along line AA 'of FIG. 2, and FIG. 4 is a perspective view of the memory module 10. As shown in FIG. 2, the memory module 10 includes four memory bare chips 1 individually cut out from a semiconductor wafer on a module substrate 2 by COB (Chip O.C.).
n Board) Implemented. Each memory bare chip 1 is, for example, a DRAM having a 4M × 4 bit configuration and a memory capacity of 16M bits. Each of the memory bare chips 1 has a rectangular shape, and is arranged in a central row in parallel with its long side. A plurality of pads 3 are formed.

The module substrate 2 is made of SO-DIM
It has an external dimension that can be mounted on an M substrate, and a plurality of pads 4 are formed in a row near the center of the module substrate 2 in parallel with the longitudinal direction. Two memory bare chips 1 are mounted on both sides of these pads 4, and the direction in which the pads 4 of the module substrate 2 are arranged and the direction in which the pads 3 of each memory bare chip 1 are arranged are almost parallel. In other words, a plurality of pads 4 are placed on the module substrate 2 between two memory bare chips 1 arranged such that their long sides are adjacent to each other so as to be in parallel with each pad 3.
Are formed. The pad 3 corresponds to a chip pad, and the pad 4 corresponds to a substrate pad.

The pads 4 of the module substrate 2 and the pads 3 of the bare memory chip 1 are connected by bonding wires 5. As shown in FIG. 2, the bonding wires 5 are alternately pulled out from the memory bare chips 1 located on both sides of the pad 4, and each bonding wire 5 has substantially the same shape and length. As described above, the pad 4 on the module substrate 2 is located between the two memory bare chips 1 arranged so that their long sides are adjacent to each other.
Is concentrated, each memory bare chip 1
The area occupied by the entire pad 4 can be reduced as compared with the case where the pads 4 are separately formed outside the memory module 10, and the memory module 10 can be reduced in size and mounted with high density.

When the two memory bare chips 1 arranged adjacent to each other with the pad 4 of the module substrate 2 interposed therebetween are aligned, the same type of two adjacent memory bare chips 1 is used. Two pads 4 on the module substrate 2 corresponding to the pads 3 can be formed at adjacent positions. Therefore, when these two pads 4 are connected to each other, it is only necessary to add a wiring pattern on the surface of the module substrate 2, and it is not necessary to perform connection using different wiring layers inside the module substrate 2, 2 can be simplified.

When the bonding wire 5 is connected, if the height of the bonding wire 5 is too low and a part of the bonding wire 5 comes into contact with the end of the memory bare chip 1, short-circuiting or disconnection due to heat may be caused. If the distance between the memory chip 5 and the bare memory chip 1 is too large, the height of the memory module 10 becomes too high. Therefore, it is desirable to perform wire bonding at a height as short as possible without the bonding wire 5 coming into contact with the bare memory chip 1.

In the memory module 10 of the present embodiment, as shown in FIG. 3, the upper surface of the wire-bonded memory bare chip 1 is covered with a resin 6 to prevent disconnection or the like. If the resin 6 is formed thick, the height of the memory module 10 becomes too high. Therefore, a sealing frame 7 having a predetermined height is attached near the outer periphery of the module substrate 2, and the resin 6 is poured into the sealing frame 7. Resin thickness is sealing frame 7
To match the height. Thereby, variation in the height of the memory module 10 can be reliably suppressed.

The above-mentioned memory module 10
It is mounted on the SO-DIMM board 11 by a so-called LCC (Leadless Chip Carrier) method. As shown in FIG. 4, external connection terminals 8 formed in a concave shape are provided on the outer surface of the module substrate 2, and these external connection terminals 8 are connected to wiring patterns 9 formed on the surface of or inside the module substrate 2. Is electrically connected to the pads 4 on the surface of the module substrate 2 via Also, by pouring solder into the recesses of these external connection terminals 8, SO-D
At the same time as the electrical connection with the IMM substrate and the like, the mechanical fixing is performed.

As described above, the memory module 10 has a SO-D by flowing the solder into the external connection terminals 8 on the outer surface.
Since mounting on the IMM board 11 can be performed, the mounting area is substantially equal to the module size, and four unpackaged memory bare chips 1 are mounted on each module board 2. Therefore, from the viewpoint of the SO-DIMM board 11 on which the memory module 10 is mounted, the CSP (Chip S
ize Package) CSM (Chip Siz)
e Module) mounting is possible.

The memory module 10 has a small area (for example, 4 chips) on the module substrate 2 in order to cut out the memory bare chip 1 formed on the semiconductor wafer and mount it on the module substrate 2 without packaging. ) Memory bare chips 1 can be mounted without difficulty.

Further, since the number of external connection terminals 8 is not so different from the number of terminals of the conventional memory IC, the number of wirings is far greater than when a normal memory IC is individually mounted on the SO-DIMM board 11. And the number of manufacturing steps and manufacturing costs can be greatly reduced. For example, assuming that a memory module 10 having a 4M × 16 bit configuration is realized by mounting four 4M × 4 bit 16M bit memory bare chips 1 on a module substrate 2 as shown in FIG. Can be commonly used by the four memory bare chips 1, and most of the control terminals such as the write enable terminal and the chip enable terminal can be commonly used. As an example, since the write enable terminal, output enable terminal, and RAS terminal except for the CAS terminal can be shared by all the memory bare chips 1, the number of external connection terminals 8 of the memory module 10 is It does not differ much from the total number of pads 3 of one.

As shown in FIG. 1A, the SO-DIMM
On one surface of the substrate 11, two memory modules 10 are mounted. Between these memory modules 10, a capacitor (generally called a bypass capacitor, hereinafter referred to as a bypass capacitor) 12 for removing noise is provided. And the controller 13 are mounted. One bypass capacitor 12 is provided for two memory bare chips 1, and the controller 13 checks the operation of each memory bare chip. These decaps 12 and controller 13 are S
It is mounted by MT (Surface Mount Technology) method.

As shown in FIG. 1B, the SO-D
On the other surface of the IMM substrate 11, the memory module 10
Are mounted, and these memory modules 10
Between them, a bypass capacitor 12 is mounted at a ratio of one to two memory bare chips 1.

FIG. 5 is a circuit diagram of the memory system shown in FIG. In this circuit diagram, the bypass capacitor 12 and the controller 13 are omitted for simplification. In the figure, portions surrounded by alternate long and short dash lines respectively correspond to the memory modules 10, and the memory bare chips 1 included in the respective memory modules 10 have address terminals A0 to A10 and data input / output terminals I / O, respectively. O0-3, write enable terminal WE, output enable terminal O
E, a CAS terminal and a RAS terminal are provided.

In this memory system, as external connection terminals 8, address terminals AD0 to AD10, data input / output terminals D0 to 63, a write enable terminal WTE, an output enable terminal OTE, a read enable terminal RE, and a chip enable terminal CE0 to CE7 are provided.

Address terminal A of each memory bare chip 1
0 to 10 are address terminals AD0 to AD1 of the external connection terminal 8.
0. Similarly, the write enable terminal WE, the output enable terminal OE, and the RAS terminal of each memory bare chip 1 are connected to the external connection terminal 8.
, A write enable terminal WTE, an output enable terminal OTE, and a read enable terminal RE. On the other hand, the data input / output terminals D0 to D63 of the external connection terminal 8 are connected to the corresponding data input / output terminals I / O0 to I / O3 of the memory bare chip 1, respectively. Also, the chip enable terminal CE of the external connection terminal 8
0 to 7 are provided at a ratio of one to two memory bare chips 1, and each memory bare chip 1 has a C
Connected to AS terminal.

As described above, the write enable terminal WE, the output enable terminal OE, excluding the CAS terminal among the various control terminals of each memory bare chip 1
The RAS terminal and the address terminals A0 to A10 are commonly connected to all the memory bare chips 1. Therefore, as for these terminals, it is only necessary to connect each bare chip for memory 1 in the memory module 10 and make one external connection terminal 8 correspond, so that the number of external connection terminals of the memory module 10 can be reduced as much as possible. it can. Therefore, the memory bare chips 1 are individually
The number of terminals to be connected can be greatly reduced as compared with the case where the terminal is mounted on the DIMM board 11, and the number of manufacturing steps can be reduced. Also, the number of patterns on the SO-DIMM substrate 11 is reduced, and it is not necessary to use an expensive multilayer substrate, so that the cost of parts can be reduced.

If a part of the memory bare chip 1 mounted on the SO-DIMM board 11 is defective, the repair operation may be performed for each memory module 10 and the entire memory system may be defective as in the prior art. Since it is not necessary to treat the product, the yield of the product is improved. further,
Replacement in units of modules has higher work efficiency and lower failure rate than replacement in units of chips.

The SO-DIMM board 11 shown in FIGS. 1 and 5 is the same as mounting 16 memory ICs on one side and 16 on both sides.
Assuming that each memory bare chip 1 included in 0 has a 4M × 4 bit configuration, the memory capacity of each memory module 10 is 8 Mbytes, and the memory capacity of the entire SO-DIMM is 32 Mbytes.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, in the above-described embodiment, an example has been described in which the memory bare chip 1 formed on the semiconductor wafer is cut out one by one; however, the cutout unit may be two or more. If a plurality of pads 3 are cut out in units of two or more rows and mounted on the module substrate 2 of the memory module 10, the mounting area can be further reduced, and the outer dimensions of the memory module 10 can be further reduced. Also, if a plurality of sets are cut out, positioning when mounting the module substrate 2 becomes easy, and the trouble of cutting out the semiconductor wafer can be saved.

FIGS. 6 (a) and 6 (b) show an example in which two memory bare chips 1 are cut out from a semiconductor wafer as a unit, and FIG. 6 (a) shows a rectangular memory bare chip 1. FIG. 6B shows an example in which two memory bare chips 1 arranged so as to be adjacent to each other via the long side are used as cutout units, and FIG. An example is shown in which two arranged memory bare chips 1 are used as cutout units.
When the cutout as shown in FIG. 6B is performed, the pad 4 may be formed near the center of the module substrate 2 as in FIG. 2, but when the cutout as shown in FIG. The pads 4 need to be formed outside the substrate 2.

FIG. 2 shows an example in which the memory bare chip 1 having a plurality of pads 3 arranged in a row is mounted. However, a memory using a memory bare chip having a plurality of pads 3 arranged in a plurality of rows is used. A module may be configured.

FIG. 7 is a plan view of a memory module 10a formed by using a memory bare chip 1a having a plurality of pads 3 arranged in two rows near the center. As shown in the figure, in this case, unlike the memory module 10 shown in FIG. 2, it is desirable to form the pads 4 also on the outer peripheral side of the module substrate 2a. As for the pads 4 formed near the center of the module substrate 2a, the bonding wires 5 are alternately pulled out from the memory bare chips on both sides as in FIG. Instead of forming a plurality of pads 3 in two rows near the center of each memory bare chip 1a, as shown in FIG. 8, pads 3 are formed in two rows near the outer edge of each memory bare chip. You may.

In FIGS. 7 and 8, a plurality of pads 3 are formed in two rows in parallel with the long side of the memory bare chip having a rectangular shape. However, as shown in FIG. A plurality of pads 3 may be formed in two rows in the vicinity. Further, as shown in FIG. 10, a plurality of pads 3 may be formed in two rows near the center so as to be parallel to the short side of each memory bare chip. In this case, it is desirable that the bonding wire 5 is drawn out toward the vicinity of the pad 3 as shown in FIG. Alternatively, depending on the length of the long side of the memory bare chip, as shown in FIG. 11, the bonding wire 5 may be drawn out in a direction perpendicular to the direction in which the plurality of pads 3 are arranged.

In FIG. 2, the bonding wires 5 are alternately drawn from the memory bare chips 1 mounted on both sides of the pads 4 of the module substrate 2. However, as shown in FIG. The bonding wire 5 may be drawn out alternately in units of.
By performing such wire bonding, the replacement operation of the defective memory bare chip 1 becomes easy.

FIG. 2 shows an example in which the pads 4 are formed in one line on the module substrate 2, but the pads 4 may be formed in two or more lines. FIG. 13 shows two rows of pads 4 formed on the module substrate 2 (hereinafter referred to as pad rows).
The memory bare chips 1 are placed on both sides of these pad rows.
The example which implemented is shown. Each pad 3 of each memory bare chip 1 jumps over a pad 4 in a row at a close distance and is connected to a pad 4 in a row distant from each other by a bonding wire 5. By such wire bonding, the height of the bonding wire 5 can be suppressed lower, and the bonding operation becomes easier. In addition, since the memory bare chips 1 adjacent to each other can be arranged close to each other by the amount of the intersection of the bonding wires 5, high density mounting of the memory bare chips 1 is possible.

FIG. 14 is a diagram showing a configuration of a memory module in which the pads 4 on the module substrate are partially formed in two rows and the other pads 4 are shared by the memory bare chips on both sides. As shown in the figure, a plurality of pads 4 are formed in a row or two rows in a region sandwiched between two memory bare chips 1, and the pads 4 arranged in a row have memory pads on both sides. Bonding wires 5 extending from the bare chip 1 are commonly connected.
For terminals commonly connected to each memory bare chip 1 such as address terminals and various control terminals, two bonding wires 5 are connected to the pads 4 on the module substrate to share the pads 4. And pad 4
Can be made smaller than the total number of pads 3 of all memory bare chips 1. Also, some pads 4 have 2
By connecting the two bonding wires 5, the connection between the two bonding wires 5 can be performed at the same time through the common pad 4, so that the wiring amount in the module substrate can be reduced. For example, compared to the case where a module substrate is configured using a multilayer substrate,
The number of layers of the module substrate can be reduced, and the cost of the memory module can be reduced.

In FIG. 2, the SO-DIMM substrate 11
Although two memory modules 10 are mounted on both sides of the SO-DIMM board 11, the number of memory modules 10 mounted on one side of the SO-DIMM board 11 is not limited to two.

FIG. 2 illustrates an example in which the memory module 10 is configured to include the four memory bare chips 1. However, the number of the memory bare chips 1 mounted on the memory module 10 is limited to four. There is no particular limitation as long as it is two or more. However, if too many memory bare chips 1 are mounted, the failure rate of the memory module 10 may increase. Therefore, taking into consideration the number of bits and the memory capacity of the memory bare chip 1 to be mounted, the memory module
It is desirable to determine the number of memory bare chips 1 to be mounted depending on whether or not the chip is manufactured. Normal computer equipment often manages memory capacity in multiples of four,
It is desirable that the number of memory bare chips 1 mounted on the module substrate be an even number.

FIG. 15 is a diagram showing a configuration of a memory module configured by using two memory bare chips.
For example, if a memory bare chip having a capacity of 64 Mbits is to be mounted on the module substrate 2 shown in FIG. 2, it is impossible to mount four chips, or the capacity of the entire memory module is not so large. In this case, a memory module may be configured using two bare chips 1 for a memory as shown in FIG.
As shown in FIG. 16, a memory module may be configured by arranging four memory bare chips in a line in the same direction.

In the above-described embodiment, the completed memory module 10 is connected to the SO-DIM by the LCC method.
Although the example of mounting on another substrate such as M has been described, the BGA (Ba
ll Grid Array) method. FIG.
FIG. 7 is a diagram for explaining the outline of the BGA method. As shown in the figure, in the case of the BGA system, the memory module 10c
A plurality of pads 21 for external connection are formed on the chip mounting surface, and bumps (projections) 22 are attached to these pads 21. Then, the memory module 10c is turned upside down, and the pad 21 of the memory module 10c is bonded to the pad 24 of the SO-DIMM substrate or the like 23 via the bump 22. As described above, in the case of the BGA method, the height of the memory module 10c is set to LC
Although it has the disadvantage of being higher than the C method, it has the advantage that there is no need to form the external connection terminals 8 on the outer surface of the memory module 10c, and the point that bonding wires 5 are unnecessary and high density mounting is possible. Common to the LCC method.

Further, in the above-described embodiment, the D-substrate having various capacities (16 Mbits or 64 Mbits)
Although the example of mounting the RAM has been described, the synchronous DRA
It is also possible to mount another type of memory bare chip 1 such as M, SRAM or flash ROM.

FIG. 2 shows an example in which the sealing frame 7 is provided in the vicinity of the outer periphery of the module substrate 2 and the resin 6 is poured. However, the method of fixing the chip mounting surface of the module substrate 2 with the resin 6 is described in FIG. For example, as shown in FIG. 18A, a method of forming a transfer mold by injection molding, or as shown in FIG. 18B, simply using a resin 6 without using a sealing frame 7, a mold, or the like. Into the chip mounting location. The method of FIG. 18 (a) requires a mold, but is suitable for mass production because the molding time can be shortened. The method of FIG. 18 (b) is difficult to keep the height of the resin 6 constant, but is cost effective. Is advantageous.

The memory module 10 of the present embodiment
As shown in FIG. 19, an insulating projection 30 may be formed along the side of the end of the memory bare chip 1 on the side from which the bonding wire 5 is drawn. After forming the insulating protrusions 30, the bonding wire 5
By pulling out, the insulating state between the bonding wire 5 and the bare chip for memory 1 can be reliably ensured.

Further, in the above-described embodiment, an example has been described in which the memory bare chip is COB-mounted on the module substrate by wire bonding, but flip-chip mounting may be performed. In this case, higher-density mounting becomes possible, so that the outer dimensions of the memory module 10 can be further reduced. FIG. 20 is a diagram showing a module substrate when the memory bare chip 1 is flip-chip mounted, and shows a module substrate when the memory bare chip 1 shown in FIG. 2 is flip-chip mounted. As shown in FIG. 2, pads 4 'are formed on the module substrate at the same intervals as the pads 3 of the bare memory chip 1 shown in FIG. 2, and these pads 4' and the pads 3 of the bare memory chip 1 face each other. With this arrangement, flip-chip mounting can be performed.

Also, the memory bare chips shown in FIGS. 7, 8 and 9 are suitable for flip chip mounting because pads 3 are formed in two rows at separated positions. On the other hand, in the memory chip shown in FIG. 10, since the pads 3 are concentrated in two rows at the center, the mounting state may be unstable when flip-chip mounted. Therefore, as shown in FIG. 21 (a) or (b), it is desirable to form several pads at the end near the short side of the memory bare chip.

Instead of COB mounting, a so-called COG (Chip On Glass) for mounting a chip on a glass substrate is used.
3.) Mounting or COF (Chip On Film) mounting may be performed, and the material of the module substrate 2 can be changed as appropriate.

In the above-described embodiment, an example in which the memory module 10 is mounted on the SO-DIMM board 11 has been described.
The present invention is not limited to the MM board 11, but may be another memory board such as a SIMM board, or a motherboard or a daughter board.

[0057]

As described above in detail, according to the present invention, a plurality of module boards 2 on which a plurality of memory bare chips 1 are mounted are mounted on the SO-DIMM board 1, and the memory bare chips 1 Directly to SO-DIMM board 1
The number of connection terminals can be greatly reduced as compared with the case of mounting on a semiconductor device, and the mounting operation becomes easier. Further, since a plurality of memory bare chips 1 cut from a semiconductor wafer are mounted on each module substrate 2 in a bare state, high-density mounting is possible, and the memory capacity of the memory system can be greatly increased. Can be. Further, when a part of the memory bare chip 1 becomes defective, the repair work can be performed in units of the module substrate 2, so that the entire memory system does not have to be treated as defective, and the yield of products is improved.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a memory system according to an embodiment; FIG. 1A is a plan view of one surface, and FIG.
Is a plan view of the other surface.

FIG. 2 is an enlarged plan view showing a memory module.

FIG. 3 is a sectional view taken along line AA ′ of FIG. 2;

FIG. 4 is a perspective view showing a part of the memory module shown in FIG. 2;

FIG. 5 is a circuit diagram of the memory system shown in FIG. 1;

FIG. 6 is a diagram showing an example in which a memory bare chip is cut out from a semiconductor wafer in units of two or more, and FIG.
FIG. 3B is a diagram showing an example in which two memory bare chips arranged adjacent to each other on the long side are used as a cutout unit, and FIG. 8B shows two memory bare chips arranged adjacently on the short side. FIG. 6 is a diagram showing an example in which a unit is used.

FIG. 7 is a plan view of a memory module configured using a memory bare chip having pads arranged in two rows parallel to a long side.

FIG. 8 is a plan view of a memory module formed by using another memory bare chip having pads arranged in two rows parallel to a long side.

FIG. 9 is a plan view of a memory module configured using a memory bare chip having pads arranged in two rows parallel to a short side.

FIG. 10 is a plan view of a memory module formed by using another memory bare chip having pads arranged in two rows in parallel with a short side.

FIG. 11 is a plan view of a memory module formed by using another memory bare chip having pads arranged in two rows in parallel with a short side.

FIG. 12 is a diagram showing an example in which a plurality of wires are alternately drawn out.

FIG. 13 is a diagram showing an example in which pads are formed in two rows on a module substrate.

FIG. 14 is a plan view of a memory module configured using a memory bare chip having pads arranged in two rows in part;

FIG. 15 is a plan view of a memory module configured using two memory bare chips.

FIG. 16 is a plan view of a memory module configured by arranging four memory bare chips in a line in the same direction.

FIG. 17 is a diagram schematically illustrating a BGA method.

FIGS. 18A and 18B are diagrams showing a modified example of a resin covering a memory bare chip on a memory module. FIG. 18A is a diagram for explaining resin formation by a transfer molding method, and FIG. It is a figure explaining resin formation at the time of not using.

FIG. 19 is a diagram illustrating an example in which an insulating protrusion is formed at an end of a memory bare chip.

FIG. 20 is a diagram showing a module substrate when a memory bare chip is flip-chip mounted.

FIG. 21 is a view showing a modification in which a pad is formed in parallel with a short side of a memory bare chip, and FIGS.
(B) is a diagram showing a pad formation surface of a memory bare chip suitable for flip-chip mounting.

FIG. 22 is a diagram showing an example in which a plurality of memory ICs are stacked and mounted.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 bare chip for memory 2 module substrate 3, 4 pad 5 bonding wire 6 resin 7 sealing frame 8 external connection terminal 10 memory module

Claims (14)

[Claims] 1. A memory system wherein a plurality of memory modules on which a plurality of memory chips cut out from a semiconductor wafer are mounted are mounted on a printed wiring board. 2. The memory system according to claim 1, wherein two memory modules are mounted on both sides of the printed wiring board. 3. The memory system according to claim 2, wherein the mounting position of the memory module is the same on each surface of the printed wiring board. 4. The memory system according to claim 2, wherein a noise removing capacitor corresponding to the memory module is mounted on each of both surfaces of the printed wiring board. 5. The memory system according to claim 4, wherein one capacitor is provided for every two memory chips. 6. The memory system according to claim 2, wherein a controller for checking an operation of the memory chip is mounted on one surface of the printed wiring board. 7. The memory system according to claim 1, wherein the printed wiring board includes an external connection terminal for exchanging signals with each of the memory chips. 8. The memory system according to claim 1, wherein the printed wiring board is a board for a small outline dual in-line memory system. 9. The memory system according to claim 1, wherein the printed wiring board is a motherboard of a computer device. 10. The memory system according to claim 1, wherein the memory module has a module substrate on which two rectangular memory chips are mounted in the vertical and horizontal directions. 11. The memory according to claim 1, wherein the memory module has a module substrate on which two rectangular memory chips are mounted with their long sides adjacent to each other. system. 12. The memory according to claim 1, wherein the memory module includes a module substrate having a pad row including a plurality of substrate pads formed in at least one row, and the pad row on the module board. Wherein the same number of the memory chips are mounted on both sides of the memory system. 13. The memory chip according to claim 1, wherein each of the memory chips has a pad row including a plurality of chip pads formed in at least one row along a long side of the memory chip. A memory system, wherein the memory chip is mounted on the module substrate such that a pad row on the memory chip and a pad row on the module substrate are substantially parallel to each other. 14. The semiconductor device according to claim 1, wherein the chip pads formed on the memory chip and the substrate pads formed on the module substrate are connected by bonding wires. Characteristic memory system.