JPH1131664A - Method for manufacture and evaluation of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method, in which a semiconductor device having a few defects can be manufactured and to provide an evaluation method for a semiconductor device, in which the manufacturing process, the measuring circuit and the measuring procedure of a device to be evaluated are simple. SOLUTION: First, an oxide film 12 is formed on a silicon substrate 11. Then, N-type impurities (phosphorus, arsenic or the like) and P-type impurities (boron, BF2 or the like) are ion-implanted in such a way that the concentration of the P-type impurities becomes about two to five times the concentration of the N-type impurities. Then, a thermal diffusion operation at 1150 deg.C and for about 10 hours takes place in a nitrogen atmosphere, and a P-type well 13 is formed. After that, the P-type well is heated at 1000 deg.C and for about two to four hours in a wet atmosphere, and a thermal oxide film 14 is formed on the surface. Then, due to the difference in segregation coefficients, the P-type impurities are absorbed into the thermal oxide film 14, and the N-type impurities are segregated on the surface of the silicon substrate 11. Through such a phenomenon, an N-type diffused layer 15 is formed on the surface of the silicon substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a shallow PN junction and a method for evaluating the method.

[0002]

With miniaturization of Related Art LSI, there is a need for the formation of the PN junction by a shallower diffusion layers, RTA (R apid T hermal A nnea as prior art to achieve this
ling) technology. This technique will be described below with reference to FIG.

First, as shown in FIG. 7A, an oxide film 42 of about 500.degree. Is formed on a silicon substrate 41, and for example, boron is ion-implanted as a P-type impurity. Next, as shown in FIG. 7B, the P-type impurity is thermally diffused to form a P well 43, and then a field oxide film 44 is formed by thermal oxidation (FIG. 7C). The field oxide film 44 is partially removed by photolithography and etching as shown in FIG.
To form Then, arsenic, which is an N-type impurity, is ion-implanted into the concave portion formed by the etching as shown in FIG. 7E, and finally, annealing is performed at about 1000 ° C. for several seconds in a lamp annealing furnace. Data Handbook, pp. 251-256). As a result, the ion-implanted arsenic is activated and becomes shallow (about 0.2 μm) as shown in FIG.
3.) An N-type diffusion layer 45 is formed near the surface of the P well 43, and a PN junction having a shallow junction depth is obtained.

FIG. 8 is a graph showing a carrier concentration distribution in a depth direction. The carrier concentration is highest on the surface of the N-type diffusion layer 45 and sharply decreases toward the PN junction interface. Then, on the surface of the P well 43, the height is sharply increased, and gradually decreases toward the deep portion after passing through the maximum value.

The quality evaluation of silicon wafers having such a PN junction is becoming stricter year by year.
With the increase in capacity and miniaturization of DRAMs, especially DRAM-LSIs, higher precision and higher sensitivity are required. For this assessment,
It is necessary to separate the current component generated by crystal defects existing inside the silicon bulk from the current component generated by the silicon-oxide film interface state, and an evaluation method using a gate controlled diode as shown in FIG. Has been implemented since.

In this method, a constant reverse bias voltage of several V is applied between the N ⁺ diffusion layer 51 of the gate controlled diode and the P-type well 52, and the positive bias voltage is swept from 0V to the gate 53. To apply. FIG. 10 shows a change in leakage current with respect to a change in gate voltage at this time. There is only current component 57 generated by the oxide film interface state leak current increases, further increasing the gate voltage - if a value X ₁ or where there is a gate voltage, the silicon substrate 56 surface immediately under the gate 53 is depleted, silicon silicon substrate 56 surface by a voltage value X ₂ is inverted to N type (55). As a result, the leak current is reduced, and only the current 58 generated by the crystal defect existing inside the silicon bulk is obtained.

Further, while the gate voltage is maintained at a higher value than the voltage of the N ⁺ diffusion layer 51 and the inversion layer 55 is formed, the voltage (reverse bias voltage) of the N ⁺ diffusion layer 51 is increased (FIG. 11).
In this case, the depletion layer 54 extends toward the deep portion of the silicon substrate 56 and takes in defects in the substrate bulk, so that the leakage current increases as shown in FIG.

In this evaluation method, a change in leakage current is monitored to separate and evaluate a current component generated by a crystal defect existing inside a silicon bulk and a current component generated by a silicon-oxide interface level. (Basics of semiconductor devices, pp.332-339).

[0009]

When a PN junction is formed by the RTA technique, the crystal defects introduced during ion implantation cannot be sufficiently recovered due to a short annealing time. Further, since rapid heating and rapid cooling are performed, there is a problem that the wafer is warped by thermal stress and current leakage occurs at the PN junction.

In addition, the conventional evaluation method using a gate controlled diode has a disadvantage that the number of steps for manufacturing an evaluation device is large because a gate electrode needs to be formed. There is also a problem that the measurement circuit and the measurement procedure are complicated.

The present invention has been made in view of such circumstances, and a PN junction shallower than the conventional one can be easily formed by introducing impurities of both conductivity types and sucking out one to form a diffusion layer. It is an object of the present invention to provide a method capable of manufacturing a semiconductor device having few defects. It is another object of the present invention to provide a method for evaluating a semiconductor device which does not require a gate electrode and uses a simple measurement circuit and a simple measurement procedure by utilizing a change in leakage current due to diffusion of a depletion layer.

[0012]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a PN junction near a surface of a semiconductor substrate. An N-type impurity is introduced at substantially the same depth, a well layer of one conductivity type is formed by thermal diffusion, and then the surface is thermally oxidized. Is segregated on the surface of the well layer.

It is necessary to set the impurity concentration of the introduced two conductivity types so that the thickness from the surface is substantially the same. By subjecting the introduced impurities to heat treatment, the impurities of the conductivity type of the desired diffusion layer are segregated on the substrate surface by the difference in the segregation coefficient, and the impurities of the opposite conductivity type are sucked out.
A diffusion layer is formed. Since the diffusion layer is formed by segregation of impurities on the substrate surface, a diffusion layer having a small thickness can be easily formed.

Further, instead of forming a diffusion layer by introducing impurities of another conductivity type into a well layer of one conductivity type as in the prior art, one is extracted from a layer in which impurities of both conductivity types are present, so that it is introduced. The impurity concentration may be lower than before, and the impurity concentration of the obtained diffusion layer is also lower than before. Furthermore, since the ion implantation step and the short-time heating step for forming the diffusion layer in the conventional method can be omitted, a semiconductor device with few defects and little leak current can be obtained. Also, the number of steps is reduced.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
2. The method according to claim 1, wherein the semiconductor substrate is a silicon substrate, the well layer is a P-type well layer, and a concentration of the P-type impurity introduced into a surface of the silicon substrate is a concentration of the N-type impurity. 2 to 5 times as large as

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
3. The method according to claim 1, wherein the P-type impurity is boron or boron fluoride, and the N-type impurity is phosphorus or arsenic.

According to a fourth aspect of the present invention, there is provided a semiconductor device evaluation method comprising:
In a method for evaluating a semiconductor device having a PN junction in which a diffusion layer of another conductivity type is formed on the surface of a substrate on which a well layer of one conductivity type is formed, and an oxide film is formed thereon, By applying the reverse bias voltage while increasing it, the depletion layer reaches the interface between the substrate and the oxide film, and the leakage current at this time is measured.

When a depletion layer is diffused by application of a reverse bias voltage and reaches a substrate-oxide film interface, a current generated by a substrate-oxide film interface level is measured by utilizing a sudden rise of a leak current. I do. Therefore, the semiconductor device to be evaluated needs to have a low impurity concentration in the diffusion layer and a small thickness. Therefore, this method is suitable for evaluating a semiconductor device manufactured by the manufacturing method according to the present invention. Further, since a gate electrode is not required unlike the related art, a step of forming the gate electrode is not required. Further, the measuring circuit and the measuring procedure used for measuring the leak current are simplified.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. FIG. 1 is a schematic cross-sectional view for explaining each step of the method for manufacturing a semiconductor device according to the present invention. First, as shown in FIG.
Approximately 200-500 膜厚 on silicon substrate 11 of 10Ωcm
The oxide film 12 is formed of, then, N-type impurity (phosphorus, arsenic, etc.) and P-type impurity (boron, BF ₂ or the like), so that the P-type impurity concentration of about 2 to 5 times the N-type impurity concentration Ion implantation. Then, thermal diffusion is performed at 1150 ° C. for about 10 hours in a nitrogen atmosphere to form a P-type well 13 as shown in FIG. 1B. If the ion implantation concentration ratio is less than 2 times, the well becomes N-type. If the concentration ratio is 5 times or more, the surface cannot be made N-type by thermal oxidation in a later step.
In other words, when the concentration ratio is 2 times or less, the substrate becomes N
When the concentration ratio exceeds 5 times, an N-type diffusion layer is not formed.

After the P-type well 13 is formed, the substrate is heated in a wet atmosphere at 1000 ° C. for about 2 to 4 hours to form a thermal oxide film 14 on the surface. Then, due to the difference in segregation coefficients, the P-type impurities are absorbed in the thermal oxide film 14 and the N-type impurities are segregated on the surface of the silicon substrate 11. Due to such a phenomenon, an N-type diffusion layer 15 is formed on the surface of the silicon substrate 11 as shown in FIG. The carrier concentration distribution in the depth direction is as shown in FIG. 2, and is similar to the distribution in the conventional PN junction (FIG. 8). That is, the carrier concentration is highest on the surface of the N-type diffusion layer 15 and sharply decreases toward the PN junction interface. Then, the temperature rises sharply on the surface of the P well 13 and gradually decreases in the deep portion after passing through the maximum value.

In the conventional method, since an N-type impurity is introduced into a P-type substrate to form an N-type diffusion layer 45, many impurities are required, and the impurity concentration is usually 10 ²⁰ cm ⁻³ . . However, in the above-described method, the N-type diffusion layer 15 is obtained by extracting the P-type impurity from the layer where the P-type and N-type impurities are present. Therefore, the impurity concentration is relatively low,
It is about 10 ¹⁷ to 10 ¹⁸ cm ^-3 . Further, the thickness of the N-type diffusion layer 45 formed by the conventional method is usually about 0.2 μm. If the thickness is made smaller than this, variations in impurity concentration and diffusion layer thickness and PN junction leakage increase, so Was difficult. However, in the present invention, since the impurity is sucked out and segregated at the oxide film-silicon interface during thermal diffusion, the N-type diffusion layer 15 having a half thickness (about 0.1 μm) is easily formed. be able to. By reducing the thickness of the N-type diffusion layer 15, its planar size can be easily reduced, and high integration can be achieved.

Next, a method for evaluating a semiconductor device according to the present invention will be described. As shown in FIG. 3, in a semiconductor device having an N-type diffusion layer 24 formed on its surface, a reverse bias voltage is swept from 0 to several tens of volts between an N ⁺ diffusion layer 21 for an electrode and a P-type well 22. Apply. The voltage-current characteristics at this time are shown in FIG.
It becomes as shown in. That is, as the reverse bias voltage increases, the depletion layer 23 gradually expands to the deep portion of the silicon substrate 25.
The leak current gradually increases by the current 27 generated by the crystal defects taken into the depletion layer 23. When the voltage is further increased, the depletion layer 23 expands upward, and a certain value X
_{When the} voltage reaches ₃ (V), it reaches the surface of the silicon substrate 25 and rapidly increases by the current component 28 generated by the silicon-oxide film interface state. By monitoring such an increase in the leak current, a current component generated by a crystal defect existing inside the silicon bulk and a current component derived from the silicon-oxide film interface state can be separately evaluated.

This evaluation method utilizes the fact that the reverse bias voltage is increased and the leak current increases sharply when the depletion layer 23 reaches the surface of the silicon substrate 25. Therefore, it is necessary that the depletion layer 23 is easily spread and the depletion layer 23 can reach the interface between the silicon substrate 25 and the oxide film. The expansion of the depletion layer 23 is greatly affected by the impurity concentration, and the lower the impurity concentration, the easier the expansion. In the semiconductor device manufactured by the above-described manufacturing method, the impurity concentration of the diffusion layer is low and the diffusion layer is thin, so that this evaluation method can be applied.

[0024]

[Embodiment] Based on the procedure shown in FIGS. 1 (a) to 1 (c),
An oxide film 12 having a thickness of 200 ° is formed on a P-type silicon substrate 11, phosphorus is ion-implanted at 1 × 10 ¹³ cm ⁻² , and boron is
^Implant at ¹³ cm ^-2 . Then 1150 in nitrogen atmosphere
Thermal diffusion was performed at 10 ° C. for 10 hours, and finally, wet oxidation was performed at 1000 ° C. for 3 hours.

As a result, a shallow PN having a depth of 0.1 μm
A junction is obtained, and the junction leakage current is as shown in FIG.
A value one digit lower than the conventional value was obtained. This eliminates the need for the N-type impurity ion implantation step (FIG. 7 (e)) and the thermal diffusion step (FIG. 7 (f)) conventionally performed to form the N-type diffusion layer. Is almost nonexistent, and the wafer is not warped because there is no RTA process for rapid heating and rapid cooling.

Next, the result of evaluating a wafer by the semiconductor device evaluation method according to the present invention will be described. As shown in FIG. 3, an evaluation device having an N ⁺ diffusion layer 21 for an electrode and a shallow PN junction formed by the above-described manufacturing method was manufactured. Then, a reverse bias voltage of 0 is applied to the N ⁺ diffusion layer 21.
The applied voltage was changed to 3030 V, and the leak current was measured.
As a result, as shown in FIG. 6, when the reverse bias voltage reached 20 V, the leak current sharply increased by about one digit. The current before the increase is a current generated by crystal defects in the silicon substrate 11, and the increased amount can be evaluated as a current generated by the silicon-oxide film interface state.

[0027]

As described above, the method of manufacturing a semiconductor device according to the present invention can omit the ion implantation step and the short-time heating step for forming the diffusion layer, so that the defect is small and the leak current is small. A semiconductor device can be obtained. Also, the number of steps is reduced. In the method for evaluating a semiconductor device according to the present invention, since a variable reverse bias voltage is directly applied to the diffusion layer, a gate electrode is not required, and the manufacturing process of the evaluation device and the simplification of the measurement circuit and the measurement procedure are realized. The present invention has excellent effects.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view for explaining each step of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a graph showing a carrier concentration distribution in a depth direction of the semiconductor device shown in FIG.

FIG. 3 is a diagram for explaining an evaluation method according to the present invention.

FIG. 4 is a graph showing a change in leakage current with respect to a change in reverse bias voltage in the evaluation method according to the present invention.

FIG. 5 is a graph showing a junction leak current of a semiconductor device manufactured by using the method of manufacturing a semiconductor device according to the present invention.

FIG. 6 is a graph showing a result of measuring a leak current by the semiconductor device evaluation method according to the present invention.

FIG. 7 is a schematic cross-sectional view for explaining each step of a conventional method for manufacturing a semiconductor device.

8 is a graph showing a carrier concentration distribution in a depth direction of the semiconductor device shown in FIG.

FIG. 9 is a diagram for explaining a conventional evaluation method using a gate controlled diode.

FIG. 10 is a graph showing a change in leakage current with respect to a change in gate voltage in a conventional evaluation method.

FIG. 11 is a graph showing a change in leak current with respect to a change in reverse bias voltage in a conventional evaluation method.

[Explanation of symbols]

 11, 25 Silicon substrate 13, 22 P-type well 14, 26 Thermal oxide film 15, 24 N-type diffusion layer

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device having a PN junction in the vicinity of a surface of a semiconductor substrate, wherein a P-type impurity and an N-type impurity are introduced into the surface of the semiconductor substrate at substantially the same depth, and are thermally diffused. Forming a well layer of one conductivity type,
Thereafter, the surface is thermally oxidized, and impurities of another conductivity type are segregated on the surface of the well layer by a difference in segregation coefficient of the impurities at this time. 2. The semiconductor substrate is a silicon substrate,
2. The method according to claim 1, wherein the well layer is a P-type well layer, and a concentration of the P-type impurity introduced into the surface of the silicon substrate is 2 to 5 times a concentration of the N-type impurity.
The manufacturing method of the semiconductor device described in the above. 3. The method according to claim 1, wherein the P-type impurity is boron or boron fluoride, and the N-type impurity is phosphorus or arsenic. 4. A method for evaluating a semiconductor device having a PN junction in which a diffusion layer of another conductivity type is formed on the surface of a substrate on which a well layer of one conductivity type is formed and an oxide film is formed thereon. Applying a reverse bias voltage to the diffusion layer while increasing the reverse bias voltage, and measuring a leak current.