JP2020184584A - Method for evaluating epitaxial wafer - Google Patents

Abstract

To provide a method for evaluating an epitaxial wafer, enabling an interface between an epitaxial layer and a semiconductor substrate to be evaluated with a high degree of accuracy.SOLUTION: The method for evaluating an epitaxial wafer is provided that comprises the steps of: preparing an epitaxial wafer including an epitaxial layer having the same conductivity type as a semiconductor substrate on the semiconductor substrate; diffusing a dopant having a conductivity type different from those of the semiconductor substrate and epitaxial layer into the epitaxial layer to form a diffusion layer and form pn junction; forming an electrode on the surface of the diffusion layer; and applying voltage to the pn junction so that the depth of a depletion layer to be formed is a depth including an interface between the epitaxial layer and the semiconductor substrate and measuring a junction leakage current flowing when applying the voltage.SELECTED DRAWING: Figure 1

Description

The present invention relates to an evaluation method for an epitaxial wafer.

With the miniaturization and higher performance of semiconductor devices such as memory and solid-state image sensors such as CCDs, in order to improve the yield of these products, silicon wafers as materials are also required to have higher quality. Various silicon wafers have been developed. In a solid-state image sensor, the quality of the silicon substrate has a great influence on the element structure, and in particular, the wafer surface layer portion is a region where PDs (photodiodes), which are presumed to directly affect the product characteristics, are formed. Crystallinity is important. As measures to improve surface quality, 1) high temperature treatment in an atmosphere containing inert gas or hydrogen, 2) reduction of grow-in defects by improving pulling conditions, 3) development of epitaxial wafers, etc. Is being done.

In particular, for a solid-state image sensor, in order to convert light into an electric signal, the light is penetrated into the semiconductor by a PD, and an image is constructed from the generated electric signal. Therefore, not only the outermost surface quality but also the quality at a depth of about several μm from the surface is very important. For this purpose, epitaxial wafers (hereinafter sometimes referred to as "EPW") are often used. EPW has merits in manufacturing a solid-state image sensor, such as having no crystal defects in the epitaxial layer (hereinafter, may be referred to as "EP layer") and having a low concentration of oxygen and carbon. However, even the EPW is not without its influence. As an example, Non-Patent Document 1 points out that the level of the interface between the silicon substrate and the EP layer has an effect. Since it is the growth interface of the EP layer and there is a difference in the dopant concentration between the substrate and the EP layer, the level can be formed here, and the carriers from the so-called neutral region mainly from the outside of the depletion layer of PD are formed. Since it is said that it affects diffusion, a method for evaluating the interface between the substrate and the EP layer is required.

Here, an electrical evaluation method for a silicon wafer, which is a typical semiconductor substrate, particularly near the surface layer will be described. As a method for evaluating the electrical characteristics of the surface quality of a silicon wafer, an oxide film withstand voltage evaluation (hereinafter, may be referred to as "GOI evaluation") is well known. In the GOI evaluation, a gate oxide film is formed on the surface of the silicon wafer by thermal oxidation, and an electrode is formed on the gate oxide film to apply electrical stress to the silicon oxide film which is an insulator. It evaluates the quality of the surface. That is, if defects or metal impurities are present on the surface of the original silicon wafer, they are incorporated into the silicon oxide film by thermal oxidation, resulting in a non-uniform insulator. That is, since the insulating property deteriorates in the presence of defects and impurities, the surface quality of the silicon wafer is evaluated by observing the degree of deterioration of the insulating property.

Since the GOI evaluation is related to the reliability of the gate oxide film of the MOSFET in an actual device, various wafers have been developed for improving the GOI characteristics. Studies of Green-in defects, especially those related to COP, in relation to GOI evaluation have contributed significantly to the improvement of wafers and devices. However, even if there is no problem in the GOI evaluation, it naturally occurs that the device yield is lowered. In particular, in recent years, with the increasing integration of devices, many such events have been increasing. In particular, in a solid-state image sensor, it is necessary to reduce the leakage current caused by the wafer in consideration of the principle, such as the influence of the diffusion current from the neutral region outside the depletion layer.

In advancing the development and improvement of silicon wafers that solve the above problems, there is a problem that the effect cannot be determined unless a device such as a solid-state image sensor is actually manufactured and evaluated. Therefore, conventionally, focusing on the structure of the light receiving portion, which can be said to be the heart of the solid-state image sensor, the wafer quality is evaluated by forming a pn junction in the wafer surface and measuring this leak current (for example,). See Patent Document 1). Patent Document 1 discloses a structure with a guard ring as a cell structure for measuring a leak current of a pn junction formed in a wafer. In this structure, a guard ring is provided in the peripheral portion of the pn junction, and the area component (consisting of the diffusion current and the generated current) of the leak current and the peripheral component (surface generated current) are separated by the guard ring. That is, according to this structure, by adjusting the voltage applied to the guard ring, the width of the depletion layer in the peripheral portion of the pn junction can be controlled and the leakage current from the peripheral portion can be suppressed.

In Patent Document 2, heteroepitaxial growth is performed to grow an epitaxial layer having a conductivity different from (opposite) that of a semiconductor substrate to form a depletion layer, and a depletion layer is also formed in the epitaxial layer. A method of evaluating not only the surface but also a deep region with a double structure is disclosed. With the double structure, it is possible to evaluate not only the epitaxial layer but also the silicon wafer.

Janesick, James R. Written by Scientific charge-coupled devices p. 334 (2000)

Japanese Patent No. 3250158 Japanese Patent No. 5751531

Although the prior art has been described above, it is extremely difficult to make an evaluation specialized for the epitaxial layer / semiconductor substrate interface. In the method of Patent Document 1, the depletion layer is located at one place near the surface, and this part can be selectively evaluated, but evaluation of a deep place such as the epitaxial layer / semiconductor substrate interface is not assumed. The method of Patent Document 2 can evaluate deep regions, but since there are two depletion layers, it is unknown where the leak source is. As described above, the evaluation of the epitaxial layer / semiconductor substrate interface as described in Non-Patent Document 1 is very difficult because the interface is located at a relatively deep position.

The present invention has been made to solve the above problems, and the problem is that the leakage current characteristics of high-quality wafers used in products that require high yield such as CCDs and CMOS sensors, especially in epitaxial wafers. , An object of the present invention is to provide an evaluation method for an epitaxial wafer capable of evaluating the epitaxial layer / semiconductor substrate interface with high accuracy.

The present invention has been made to achieve the above object, and is different from the step of preparing an epitaxial wafer having the same conductive type epitaxial layer as the semiconductor substrate on the semiconductor substrate, and the semiconductor substrate and the epitaxial layer. The step of forming a pn junction by diffusing a conductive type dopant into the epitaxial layer to form a diffusion layer, the step of forming an electrode on the surface of the diffusion layer, and the depth of the formed depleted layer are described above. Provided is an evaluation method of an epitaxial wafer including a step of applying a voltage to the pn junction so as to have a depth including an interface between the epitaxial layer and the semiconductor substrate and measuring a junction leakage current when the voltage is applied.

According to such an evaluation method of an epitaxial wafer, it is possible to evaluate the epitaxial layer / semiconductor substrate interface with high accuracy.

At this time, in the step of measuring the junction leakage current, a voltage may be applied to the pn junction so that the depth of the formed depletion layer is equal to the interface between the epitaxial layer and the semiconductor substrate. it can.

This makes it possible to evaluate the epitaxial layer / semiconductor substrate interface with higher accuracy.

At this time, before the step of forming the pn junction, a well having the same conductive type as the semiconductor substrate and the epitaxial layer is formed so as to include an interface between the epitaxial layer and the semiconductor substrate, and the well is formed. It can be used as an evaluation method for an epitaxial wafer having a step of forming a channel stop layer around it.

As a result, the influence of the resistance of the semiconductor substrate can be eliminated at the time of measuring the junction leakage current, so that the quality evaluation of the epitaxial layer / semiconductor substrate interface can be performed more easily and with higher accuracy.

At this time, before the step of forming the well and the channel stop layer, a step of forming a separation oxide film having a window portion is further provided, and in the step of forming the well and the channel stop layer, ion implantation is performed. By doing so, a well can be formed in the lower part of the window portion, and a channel stop layer can be formed directly under the separation oxide film.

As a result, it is possible to effectively prevent the occurrence of parasitic depletion capacity around the well, and as a result, it is possible to prevent the leakage current (peripheral component) from around the well from being measured when measuring the junction leak current. Therefore, it is possible to evaluate the epitaxial layer / semiconductor substrate interface with higher accuracy.

At this time, in the step of forming the well, ions can be injected into the window portion where the oxide film is not formed at an injection amount of 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁷ atoms / cm ^3. ..

As a result, the formation of dislocations and the formation of defects in the wells due to ion implantation can be suppressed more effectively, and the influence of the resistance of the semiconductor substrate is reduced, so that the leakage current measurement can be performed more stably.

At this time, the dopant concentration of the well is 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁷ atoms / cm ³ , the depth is 2 μm or less, and the dopant concentration of the channel stop layer is 1 × 10 ¹⁶ atoms / cm ^3. ~ 1 × 10 ¹⁷ atoms / cm ³ , depth is 0.5 μm or less, dopant concentration of the diffusion layer is 1 × 10 ¹⁸ atoms / cm ³ ~ 5 × 10 ²⁰ atoms / cm ³ , depth is 1 μm or less. can do.

As a result, it is possible to effectively prevent the occurrence of parasitic depletion capacity around the well, it is possible to set a depletion layer suitable for the junction leak current measurement, and the leak current measurement can be performed more stably.

At this time, in the step of forming the electrode on the surface of the diffusion layer, the area of the electrode to be formed can be set to 4 mm ² or less.

As a result, it is possible to secure a high position resolution when measuring the junction leak current, and it is possible to effectively prevent the current value when measuring the leak current from becoming too large.

As described above, according to the present invention, it is possible to evaluate the epitaxial layer / semiconductor substrate interface with high accuracy.

An example of a junction structure (cross-sectional structure) for measuring leak current according to the present invention is shown. It is a flow chart which showed an example of the manufacturing process of a bonded structure. The leak current measurement result of Example 1 is shown. The leak current measurement result of Example 2 is shown.

Hereinafter, the present invention will be described in detail, but the present invention is not limited thereto.

As described above, there has been a demand for an evaluation method for an epitaxial wafer capable of evaluating the epitaxial layer / semiconductor substrate interface with high accuracy.

As a result of diligent studies on the above problems, the present inventors have prepared a step of preparing an epitaxial wafer having the same conductive type epitaxial layer as the semiconductor substrate on the semiconductor substrate, and the semiconductor substrate and conductivity different from the epitaxial layer. The step of forming a diffusion layer by diffusing a mold dopant into the epitaxial layer to form a pn junction, the step of forming an electrode on the surface of the diffusion layer, and the depth of the formed depleted layer are the epitaxial. According to an epitaxial wafer evaluation method including a step of applying a voltage to the pn junction so as to include the interface between the layer and the semiconductor substrate and measuring the junction leakage current when the voltage is applied, the epitaxial layer / We have found that the characteristics of the semiconductor substrate interface can be evaluated accurately, and completed the present invention.

FIG. 1 shows an example of a bonding structure 100 (cross-sectional structure) for measuring a bonding leak current when the evaluation method for an epitaxial wafer according to the present invention is carried out. The junction structure 100 for measuring the junction leakage current includes a semiconductor substrate 1, an epitaxial layer (hereinafter, may be referred to as “EP layer”) 2 formed on the semiconductor substrate 1, and the EP layer 2 thereof. That is, it has a well 5 formed to a depth including the epitaxial layer / semiconductor substrate interface 9, and a diffusion layer 6 formed in the well 5. As in the example shown in FIG. 1, it is possible to further form the separation oxide film 7 around the junction of the wells 5 and the channel stop layer 8 formed immediately below the separation oxide film 7. One of the features of the bonded structure 100 is that the well 5 is formed to a depth including the epitaxial layer / semiconductor substrate interface 9. As a result, the influence of the resistance of the semiconductor substrate can be eliminated when measuring the junction leakage current, so that the depletion layer 4 can be more easily expanded to the epitaxial layer / semiconductor substrate interface 9, and as a result, the epitaxial layer / semiconductor substrate interface can be expanded. The quality evaluation of 9 can be performed more easily and with higher accuracy. However, as will be described later, the formation of the well 5 can be omitted.

The well 5 can be formed directly under the window-opened portion of the separation oxide film 7, that is, in the window portion 91 in which the oxide film is not formed. The well 5 is of the same conductive type as the EP layer 2. The concentration of the well 5 (well concentration) is preferably in the range of 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁷ atoms / cm ³ . For example, by ion-implanting boron and setting it within the above range, the formation of dislocations and defects in the well 5 due to ion implantation can be more effectively suppressed, and the influence of the resistance of the semiconductor substrate 1 is small. Therefore, the leakage current can be measured more stably.

The separation oxide film 7 is an oxide film for insulatingly separating the bonding element. The thickness of the separated oxide film 7 can be set in consideration of the formation of the channel stop layer 8 described later. The diffusion layer 6 is a layer in which a conductive type dopant different from the well 5 is diffused in the well 5 from the surface of the well 5 to a certain depth inside the well 5. Since the well 5 (however, the portion excluding the diffusion layer 6) and the diffusion layer 6 have different conductive types, the interface between the well 5 and the diffusion layer 6 is a pn junction 3. Therefore, when a voltage is applied, a depletion layer 4 (a region surrounded by a dotted line) formed by the pn junction 3 is formed in the well 5. The dopant concentration of the diffusion layer 6 is preferably in the range of 1 × 10 ¹⁸ atoms / cm ³ to 5 × 10 ²⁰ atoms / cm ³ . The depth of the diffusion layer 6 is preferably 1 μm or less. By setting the dopant concentration and depth of the diffusion layer 6 within the above ranges, the depletion layer 4 suitable for measuring the junction leakage current can be set.

The channel stop layer 8 can be formed around the junction of the wells 5. In one example of the embodiment, the channel stop layer 8 is formed directly below the separation oxide film 7. The dopant concentration of the channel stop layer 8 is preferably in the range of 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁷ atoms / cm ³ . Further, the depth of the channel stop layer 8 is preferably 0.5 μm or less. The channel stop layer 8 can effectively prevent the generation of parasitic depletion capacity around the well 5 due to the influence of the separation oxide film 7 and the surface interface state. As a result, when measuring the junction leakage current, it is possible to prevent the leakage current (peripheral component) from the periphery of the well 5 from being measured, so that the epitaxial layer / semiconductor substrate interface 9 should be evaluated with higher accuracy. Can be done. Further, by setting the dopant concentration and depth of the channel stop layer 8 within the above ranges, it is possible to prevent defects that affect GOI (oxide pressure resistance) from occurring due to ion implantation during the formation of the channel stop layer 8 described later.

Using the bonded structure 100 described above, a voltage (reverse bias) is applied so that the depletion layer 4 includes the epitaxial layer / semiconductor substrate interface. Then, it is monitored as a junction leakage current (current generated and recombined in the depletion layer) flowing at that time. According to the bonded structure 100, it is possible to measure the quality of the epitaxial layer / semiconductor substrate interface 9 with high accuracy, and therefore, the epitaxial wafer can be evaluated with high accuracy.

Further, it is preferable to apply a voltage so that the depth (lower end) of the depletion layer 4 is equal to the depth of the epitaxial layer / semiconductor substrate interface. More accurate evaluation of the epitaxial layer / semiconductor substrate interface becomes possible.

Next, an evaluation method for an epitaxial wafer according to the present invention will be described. First, as the substrate to be evaluated, an epitaxial wafer in which the same conductive type epitaxial layer as the semiconductor substrate is formed on the semiconductor substrate is prepared. Next, a conductive type dopant different from the semiconductor substrate and the epitaxial layer is diffused in the epitaxial layer to form a diffusion layer, and a pn junction is formed. Further, an electrode can be formed on the surface of the diffusion layer to obtain a bonded structure for evaluation. The evaluation is performed by applying a voltage to the pn junction so that the depth of the formed depletion layer includes the interface between the epitaxial layer and the semiconductor substrate, and measuring the junction leakage current when the voltage is applied.

FIG. 2 is a flow chart showing a specific example of the manufacturing process of the bonded structure 100. First, as shown in FIG. 2A, a mask oxide film 90 serving as a mask is formed on the prepared epitaxial wafer. The mask oxide film 90 may be thermally oxidized or CVD. That is, when forming a well after this, ion implantation is performed, but the mask oxide film 90 is formed so that the ions at this time slightly pass through the mask oxide film 90 to form the channel stop layer 8. It is preferable to set the thickness. Since this thickness depends on the elements constituting the ions and the ion implantation conditions (acceleration voltage, etc.), a value suitable for the process and equipment can be set. Next, as shown in FIG. 2B, photolithography is performed on the mask oxide film 90, and the mask oxide film 90 is subjected to window opening processing by dry etching or wet etching to form the window portion 91. At this time, the window portion 91 corresponds to the joint area (electrode area) of the pn junction 3 in FIG. Therefore, the area of the window portion 91 is preferably set so as to satisfy 4 mm ² or less. By doing so, it is possible to secure a high position resolution when measuring the junction leak current, and it is possible to effectively prevent the current value when measuring the leak current from becoming too large. The portion of the mask oxide film 90 excluding the window portion 91 becomes the separation oxide film 7.

Next, as shown in FIG. 2C, the same conductive type ion 13 (dopant) as the EP layer 2 is implanted into the EP layer 2 by ion implantation. At this time, the ion implantation layer 12 is formed directly below the window portion 91 and directly below the separation oxide film 7. Of the ion-implanted layers 12, the layer formed directly under the window portion 91 functions as a well 5, and the layer formed directly under the separation oxide film 7 functions as a channel stop layer 8. The well 5 corresponds to the well before the diffusion layer 6 of FIG. 2D is formed. Further, the channel stop layer 8 is formed by passing the ions 13 through the separation oxide film 7, that is, by utilizing cell alignment. Further, in this step, ion implantation is performed directly without forming an oxide film other than the separation oxide film 7 (for example, a thermal oxide film for a screen oxide film). This makes it possible to simplify the manufacturing process of the bonded structure 100. The dose amount in ion implantation is within a range in which defects that affect GOI (oxide pressure resistance) characteristics do not occur, that is, a preferable range of the dopant concentration of well 5 described above (1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ^17). It is set to satisfy the range of atoms / cm ^3). Further, the accelerating voltage in ion implantation can be set so that the channel stop layer 8 can be formed in consideration of the thickness of the separation oxide film 7 and the like. After ion implantation, recovery annealing should be performed.

Next, as shown in FIG. 2D, in order to form the pn junction 3 in the well 5, a conductive element different from the well 5 is diffused to form the diffusion layer 6. The diffusion at this time may be ion implantation or fixed diffusion. At this time, the recovery heat treatment performed by ion implantation may also serve as the recovery heat treatment by ion implantation of well formation. Finally, on the surface of the diffusion layer 6 exposed to the window portion 91, an electrode portion 10 for measuring the junction leakage current by applying a voltage to the pn junction is formed. Through each of the above steps, the joint structure 100 is completed. The depth of the depletion layer formed by using such a junction structure 100 is preferably such that the depth of the depletion layer 4 is the depth including the interface between the EP layer 2 and the semiconductor substrate 1. However, by applying a voltage to the pn junction so that the depth is equal to the interface between the EP layer 2 and the semiconductor substrate 1 and measuring the junction leakage current when the voltage is applied, the epitaxial wafer, especially the epitaxial layer / Highly accurate evaluation of the semiconductor substrate interface can be performed.

In the above description, the joint structure 100 has a structure having wells 5, but a structure without wells 5 can also be adopted. This can be applied regardless of the thickness of the EP layer 2, but is particularly suitable for evaluation when the EP layer 2 is thick. For example, evaluation is possible even when the ion implantation depth cannot reach the epitaxial layer / semiconductor substrate interface 9. In this case, the method for producing the bonded structure 100 may simply omit the ion implantation step for producing the wells. At this time, the channel stop layer 8 can be formed by the diffusion of the diffusion layer 6. In the case of the bonded structure 100, the depth of the depletion layer 4 can be defined by the resistivity of the EP layer 2 and the applied voltage. When comparing between wafers, if the resistivity of EP layer 2 of each wafer is matched, the depletion layer width will be the same when the applied voltage is the same, and the comparison between wafers can be easily performed. It can be carried out.

Hereinafter, the present invention will be described in detail with reference to examples, but this does not limit the present invention.

(Example 1)
The following experiment was carried out to confirm the effect of the present invention. As a semiconductor substrate to be evaluated, a boron-doped 200 mmφ silicon wafer having a resistivity of 10 Ω · cm was prepared. First, for the semiconductor substrate to be evaluated, a reactor (with contamination and no contamination) whose difference in heavy metal contamination level has been investigated in advance is used to grow a boron-doped EP layer to produce epitaxial wafers with different contamination levels. did. The EP layer at this time had a thickness of 1.5 μm and a resistivity of 10 Ω · cm. The epitaxial wafer was treated with a Pyro atmosphere at 1000 ° C. for 90 minutes to form a 200 nm oxide film. After that, a resist was applied and photolithography was performed. In this example, a negative resist was selected. This resisted wafer was subjected to oxide film etching with a buffered HF solution, the resist was removed with a hydrogen peroxide mixed solution, and then RCA cleaning was performed. Boron was ion-implanted into this epitaxial wafer at an accelerating voltage of 200 KeV and a dose amount of 2 × 10 ¹² atoms / cm ² to form a well and a channel stop layer. The thickness (depth) of the well was 2 μm. The dose amount of 2 × 10 ¹² atoms / cm ^{2 at} this time is the dose amount at which the peak concentration of the well is 1 × 10 ¹⁷ atoms / cm ³ . After performing recovery annealing at 1000 ° C. in a nitrogen atmosphere, phosphorus glass was applied and diffused, and phosphorus was diffused from the surface to form a pn junction in the well.

The result of measuring the leak current using this structure is shown in FIG. In this structure, the well is 2 μm as described above, and in this case, when the applied voltage is 2.5 V, the depletion layer reaches the lower end of the well. As shown in FIG. 3, in the epitaxial wafer using the contaminated reactor, the leakage current increased sharply when the applied voltage was around 2.5 V. In this way, when the epitaxial layer / semiconductor substrate interface is contaminated, the leakage current increases when the depletion layer reaches the well, that is, the epitaxial layer / semiconductor substrate interface (voltage about 2.5 V). Can be seen. As described above, it can be seen that the leakage current evaluation using the junction structure of Example 1 enables the evaluation of the epitaxial layer / semiconductor substrate interface.

(Example 2)
In Example 2, an epitaxial wafer having an EP layer thicker than that of Example 1 was produced, and leakage current was evaluated without forming wells. First, for the semiconductor substrate to be evaluated, a reactor (with contamination and no contamination) whose difference in heavy metal contamination level has been investigated in advance is used to grow a boron-doped EP layer to produce epitaxial wafers with different contamination levels. did. The EP layer at this time had a thickness of 4 μm and a resistivity of 10 Ω · cm. The epitaxial wafer was treated with a Pyro atmosphere at 1000 ° C. for 90 minutes to form a 200 nm oxide film. After that, a resist was applied and photolithography was performed. In this example, a negative resist was selected. This resisted wafer was subjected to oxide film etching with a buffered HF solution, the resist was removed with a hydrogen peroxide mixed solution, and then RCA cleaning was performed. Phosphorus was ion-implanted into this epitaxial wafer at an accelerating voltage of 160 KeV and a dose amount of 2.5 × 10 ¹² atoms / cm ² to form a pn junction.

The leakage current measurement result of Example 2 is shown in FIG. In Example 2, there are no wells and the depletion layer width is determined by the resistance of the EP layer and the applied voltage. When the applied voltage is 9V, the depletion layer reaches the epitaxial layer / semiconductor substrate interface. For wafers using contaminated reactors, the leakage current increases sharply at 9V. As described above, when the epitaxial layer / semiconductor substrate interface is contaminated, the leakage current increases when the depletion layer reaches the epitaxial layer / semiconductor substrate interface (voltage of about 9 V). In this way, by evaluating the bonding structure of Example 2, it can be seen that the bonding leakage current at the epitaxial layer / semiconductor substrate interface can be measured.

As can be seen from the results of Examples 1 and 2, according to the evaluation method of the present invention, an epitaxial layer / semiconductor substrate interface that could not be evaluated conventionally by using a bonded structure having a simple structure is used. Highly accurate measurement of junction leakage current has become possible.

The present invention is not limited to the above embodiment. The above-described embodiment is an example, and any object having substantially the same configuration as the technical idea described in the claims of the present invention and exhibiting the same effect and effect is the present invention. Is included in the technical scope of.

1 ... semiconductor substrate, 2 ... epitaxial (EP) layer, 3 ... pn junction,
4 ... depletion layer, 5 ... well, 6 ... diffusion layer, 7 ... separation oxide film,
8 ... channel stop layer, 9 ... epitaxial layer / semiconductor substrate interface,
10 ... Electrode part, 12 ... Ion implantation layer, 13 ... Ions,
90 ... Mask oxide film, 91 ... Window part, 100 ... Bonded structure.

Claims (7)

This is an evaluation method for epitaxial wafers.
A process of preparing an epitaxial wafer having the same conductive type epitaxial layer as the semiconductor substrate on the semiconductor substrate, and
A step of diffusing the semiconductor substrate and a conductive type dopant different from the epitaxial layer into the epitaxial layer to form a diffusion layer and forming a pn junction.
The step of forming an electrode on the surface of the diffusion layer and
A step of applying a voltage to the pn junction so that the depth of the formed depletion layer includes the interface between the epitaxial layer and the semiconductor substrate, and measuring the junction leakage current when the voltage is applied. A method for evaluating an epitaxial wafer, which comprises. In the step of measuring the junction leakage current, a voltage is applied to the pn junction so that the depth of the formed depletion layer is equal to the interface between the epitaxial layer and the semiconductor substrate. The evaluation method for an epitaxial wafer according to claim 1. Prior to the step of forming the pn junction, a well having the same conductive type as the semiconductor substrate and the epitaxial layer is formed so as to include an interface between the epitaxial layer and the semiconductor substrate, and a channel is formed around the well. The method for evaluating an epitaxial wafer according to claim 1 or 2, further comprising a step of forming a stop layer. Prior to the step of forming the well and the channel stop layer, a step of forming a separation oxide film having a window portion is further included.
3. The third aspect of the present invention is that in the step of forming the well and the channel stop layer, a well is formed in the lower part of the window portion and a channel stop layer is formed directly under the separation oxide film by performing ion implantation. The method for evaluating an epitaxial wafer according to. A claim characterized in that in the step of forming the well, ions are injected into the window portion where the oxide film is not formed at an injection amount of 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁷ atoms / cm ^3. Item 4. The method for evaluating an epitaxial wafer according to Item 4. The dopant concentration of the well was 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁷ atoms / cm ³ , and the depth was 2 μm or less.
The dopant concentration of the channel stop layer was 1 × 10 ¹⁶ atoms / cm ³ to 1 × 10 ¹⁷ atoms / cm ³ , and the depth was 0.5 μm or less.
The epitaxial wafer according to claim 4 or 5, wherein the dopant concentration of the diffusion layer is 1 × 10 ¹⁸ atoms / cm ^{3 to} 5 × 10 ²⁰ atoms / cm ³ , and the depth is 1 μm or less. Evaluation methods. The method for evaluating an epitaxial wafer according to any one of claims 1 to 6, wherein the area of the electrode to be formed is 4 mm ² or less in the step of forming the electrode on the surface of the diffusion layer. ..

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