JPH11313225A - Clamp circuit for video signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a clamp circuit for a video signal that is operated stably even for a video signal received at weak electric field strength. SOLUTION: The clamp circuit is provided with an integration circuit 1 that receives a video signal and whose integration action is set/reset depending on a control signal, a clamping capacitor 2 that receives an output signal from the integration circuit 1 at its one-side terminal, and a comparator 3 whose one terminal connects to the other terminal of the clamping capacitor 3 and whose other terminal connects to a reference voltage source and whose comparison output charges/discharges the clamping capacitor 2. In this clamping circuit, the integration circuit 1 makes integration for a period when the comparator 3 charges/discharges the clamping capacitor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TV receiver and a VT
The present invention relates to a clamp circuit for a video signal such as R, and more particularly to a clamp circuit for a video signal which can operate stably even with a video signal in a weak electric field.

[0002]

2. Description of the Related Art Circuits for processing video signals, such as TV receivers and VTRs, require a video signal clamping circuit.
As one of video signal clamp circuits, there is a method of fixing a pedestal period immediately after a horizontal synchronization signal to a constant DC voltage. In this method, the voltage of the horizontal synchronizing signal during the pedestal period and a constant DC voltage are compared in the pedestal period, and the DC level of the video signal (including the horizontal synchronizing signal) is adjusted so as to eliminate the difference.

[0003] The DC level is adjusted by charging and discharging a clamp capacitor.

[0004]

However, the conventional clamp circuit cannot operate stably for a video signal in a weak electric field. When noise due to a weak electric field is mixed in the pedestal period immediately after the horizontal synchronization signal constituting the video signal, a level comparison between the noise and a constant DC voltage is performed, and the DC level of the video signal is adjusted based on the result. Therefore, the DC level of the video signal fluctuates due to noise.

When such a video signal is displayed on a screen, white / black horizontal stripes occur randomly.

FIG. 2A shows a video signal including both a period in which noise is mixed and a period in which noise is not mixed in a weak electric field. FIG. 2B shows a pedestal pulse which goes to the “H” level during the pedestal period.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has an integration circuit for applying an image signal to turn on and off an integration operation in response to a control signal. A clamp capacitor to which an output signal is applied to one end, a comparator having one end connected to the other end of the clamp capacitor, the other end connected to a reference voltage source, and charging and discharging the clamp capacitor by a comparison output. Wherein the integration operation of the integration circuit is performed during a period in which the comparator charges and discharges the clamping capacitor.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A video signal clamping circuit according to the present invention will be described with reference to FIG. 1 is an integration circuit whose integration operation is turned on / off in response to a control signal, 2 is a clamp capacitor to which an output signal of the integration circuit 1 is applied to one end, 3 is one end connected to the other end of the clamp capacitor 2, The other end is connected to a reference voltage source 4 and is a comparator that charges and discharges the clamping capacitor 2 based on the comparison output.

In FIG. 1, the integrating circuit 1 is composed of a series circuit of a resistor 5, a capacitor 6, and a transistor 7,
A control signal is applied to the base of transistor 7. The comparator 3 is a current output type.

In FIG. 1, a video signal to be clamped (FIG. 3A) is applied to an input terminal 8. Terminal 9
The pedestal pulse shown in FIG.

Note that BGP is used instead of the pedestal pulse.
(Burst gate pulse) and a flyback pulse may be used.

First, the period during which the "H" level pedestal pulse shown in FIG. 3B is applied will be described. During this period, the transistor 7 is turned on and the switch 10 is closed. When the transistor 7 is turned on, the integrating circuit 1 including the resistor 5 and the capacitor 6 functions when viewed from the input terminal 8.

On the other hand, when the switch 10 is closed, the feedback function of the comparator 3 operates.

The video signal to be clamped from the input terminal 8 is subjected to the integration circuit 1 to remove noise during the pedestal pulse period. This is shown at the location of the dotted line connecting FIG. 3 (a) and FIG. 3 (c). Noise is removed from a part of the pedestal period in FIG. The level of the video signal from which the noise has been removed is compared with the level of the reference voltage source 4 of the comparator 3, so that the video signal is not affected by the noise.

The video signal shown in FIG. 3 (c) is applied to the negative input terminal of the comparator 3 via the clamping capacitor 2 and is compared with the level of the reference voltage source 4 of the comparator 3.
The comparator 3 generates a current according to the level difference between the two. Since the switch 10 is closed, the clamp capacitor 2 is charged and discharged by the output current of the comparator 3.

For example, if the output current of the comparator 3 is larger than the current of the constant current source 11, the clamp capacitor 2 is charged by the current, and the DC voltage of the output terminal 12 rises.

Conversely, if the output current of the comparator 3 is smaller than the current of the constant current source 11, a corresponding current flows from the clamping capacitor 2 to the constant current source 11 and the output terminal 12
DC voltage drops.

Therefore, the DC voltage of the output terminal 12 during the clamp period is automatically adjusted to be equal to the reference voltage of the reference voltage source 4.

At this time, the voltage of the video signal during the pedestal period, which is to be compared, does not include a noise component as shown in FIG. 3 (c), so that accurate and stable clamping is possible.

In this way, the remaining video signal arriving via the clamp capacitor 2 charged to a desired DC voltage is led to the output terminal 12.

Therefore, the video signal can be stably clamped even when the video signal is in a weak electric field.

The "L" level period in FIG. 3B will be described. During this period, the transistor 7 is turned off,
Switch 10 opens. When the transistor 7 is turned off, the integration circuit 1 constituted by the resistor 5 and the capacitor 6 when viewed from the input terminal 8 does not exist.

On the other hand, when the switch 10 is opened, the feedback function of the comparator 3 does not operate, and the clamp capacitor 2 enters a hold state.

[0024]

According to the present invention, the integration operation of the integration circuit is performed during the period of charging and discharging the clamp capacitor, so that the video signal can be stably clamped even when the video signal is in a weak electric field. Can be done.

[Brief description of the drawings]

FIG. 1 is a video signal clamping circuit according to the present invention.

FIG. 2 is a waveform chart for explaining a video signal clamping operation of a conventional clamping circuit.

FIG. 3 is a waveform chart for explaining a clamp operation of a video signal of the clamp circuit of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 integration circuit 2 clamping capacitor 3 comparator 4 reference voltage source 7 transistor 10 switch

Claims (3)

[Claims] An integration circuit for integrating an image signal and turning on / off an integration operation in accordance with a control signal; a clamp capacitor to which an output signal of the integration circuit is applied to one end; The other end is connected to a reference voltage source, and a comparator that charges and discharges the clamp capacitor according to a comparison output thereof,
A video signal clamping circuit, wherein the integration operation of the integration circuit is performed during a period in which the comparator charges and discharges the clamping capacitor. 2. The control circuit according to claim 1, wherein said integrating circuit comprises a series circuit of a resistor, a capacitor and a transistor, and said control signal is applied to a base of said transistor.
The described video signal clamp circuit. 3. The video signal clamping circuit according to claim 1, wherein said comparator is of a current output type.