JPH11312792A - Manufacture of capacitor for dram cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of photo-processes by merging a storage- electrode contact-hole forming process and a storage-electrode forming process, and to prevent the faulty array of a storage-electrode contact hole and a storage electrode. SOLUTION: A first insulating layer 108 is etched by using second substance layers and conductive-layer spacers 118 formed on a second insulating layer 112 as masks. Consequently, storage-electrode contact holes, second openings, having size relatively smaller than the size of first openings are formed. The first and second openings are filled with second conductive layers 120 such as polysilicon films, and the second conductive layers 120 and the second substance layers are etched to a flattened shape so that the upper surface of the second insulating layer 112 is exposed. When the second insulating layer 112 is removed by wet type etching, etc., self-alignment storage electrodes 122 are formed to the second openings as storage-electrode contact holes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a DRAM cell capacitor, and more particularly, to a method for self-aligning a storage electrode contact hole and a storage electrode. And a method of manufacturing a DRAM cell capacitor to be manufactured.

[0002]

2. Description of the Related Art In developing a 4GDRAM (0.30 pitch), the size of a storage electrode is gradually reduced, but the size of a storage electrode contact hole is limited. Accordingly, the misalignment margin between the storage electrode contact hole and the storage electrode is reduced, and the margin between the storage electrode contact hole and the bit line is reduced, so that the storage electrode contact hole is reduced in the bit line. (Bit line) is touched.

[0003] Storage electrode poly patterning (pattern)
At the time of ning, many problems such as patterning failure and uniformity failure have occurred due to limitations of existing processes such as fabrication of photomask, optical lithography process, and etching.

[0004]

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and it is possible to self-align a storage electrode contact hole and a storage electrode. An object of the present invention is to provide a method of manufacturing a DRAM cell capacitor that can prevent misalignment of electrodes.

Another object of the present invention is to provide a method of fabricating a DRAM cell capacitor in which the size of the storage electrode contact hole can be reduced, thereby increasing the margin between the storage electrode contact hole and the bit line. It is to provide.

[0006]

According to the present invention, there is provided a method of manufacturing a DRAM cell capacitor, comprising: forming a first insulating layer on a semiconductor substrate having a gate electrode formed thereon; Forming a bit line in the insulating layer; forming a second material layer having an etching selectivity with the insulating layer in sequence with a second insulating layer interposed on the first insulating layer; Forming a second insulating layer to a thickness of the storage electrode, forming a reverse pattern for forming the storage electrode on the second material layer;
A second material layer using the Leaving pattern as a mask,
Sequentially etching the second insulating layer and the first material layer to form at least one first opening;
Removing the leakage pattern; and forming a first opening having an etching selectivity with the first insulating layer on both side walls of the first opening.
Forming a spacer as a conductive layer; etching the first insulating layer using the second material layer and the conductive layer spacer as a mask to form at least one second opening; Filling the opening with the second conductive layer, flattening and etching the second conductive layer and the second material layer so that the upper surface of the second insulating layer is exposed, and using the first material layer as an etch stop layer Removing the second insulating layer to form a self-aligned storage electrode at the second opening.

In a preferred embodiment of the method, D
The method of manufacturing the RAM cell capacitor additionally includes a step of removing the first material layer on both sides of the storage electrode after removing the second insulating layer. In a preferred embodiment of the method, a method of manufacturing a DRAM cell capacitor includes forming a conductive layer on a first material layer including a storage electrode;
Forming a storage electrode spacer by etching the conductive layer and the first material layer under the conductive layer so that the upper surface of the first insulating layer is exposed.

Referring to FIGS. 4 and 11, the method of manufacturing a new DRAM cell capacitor according to the present invention can reduce the number of photo processes by combining a storage electrode contact hole forming process and a storage electrode forming process. . That is, by self-aligning the storage electrode contact hole and the storage electrode, misalignment of the storage electrode contact hole and the storage electrode can be prevented. Also, the size of the storage electrode contact hole can be reduced, and the margin between the storage electrode contact hole and the bit line can be increased.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 8 to 1
In FIG. 4, components having the same functions as the components of the DRAM cell capacitor shown in FIGS. 1 to 7 are denoted by the same reference numerals.

FIGS. 1 to 7 are cross-sectional views showing a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention in the order of steps, taken along a bit line extending direction. FIGS. DRA according to embodiments of the invention
FIG. 4 is a cross-sectional view taken along a word line extending direction as a diagram illustrating a method of manufacturing an M cell capacitor in the order of steps.
Referring to FIGS. 1 and 8, D according to an embodiment of the present invention is shown.
In the method for manufacturing a RAM cell capacitor, first, an element isolation film 102 is formed on a semiconductor substrate 100 by defining an active region and an inactive region.

Gate electrodes 104a-104d are formed on semiconductor substrate 100 with a gate oxide film therebetween.
The gate electrodes 104a to 104d are made of a silicon nitride film Si
It is formed so as to be surrounded by an insulating film such as N105. A storage electrode pad (pad) 106a and a bit line pad 106 are formed between the gate electrodes 104a-104d and on the semiconductor substrate 100 in the bit line formation region.
b is formed.

A first insulating layer 108 is formed on the semiconductor substrate 100 including the gate electrodes 104a-104d. Bit lines 109 a to 109 d are formed in the first insulating layer 108. More specifically, the gate electrode 104a-1
A first oxide film 108a having a flat upper surface is formed on the semiconductor substrate 100 including the substrate 04d. First oxide film 1
After the bit lines 109a-109d are formed on the first oxide film 108a, the second oxide film 1 having a flat upper surface on the first oxide film 108a including the bit lines 109a-109d is formed.
08b is formed.

On the first insulating layer 108, a first material layer 110,
A second insulating layer 112 and a second material layer 114 are sequentially formed. The first and second material layers 110 and 114 are formed of a material having an etching selectivity with respect to the insulating layers 108 and 112. When the insulating layers 108 and 112 are oxide films,
The first and second material layers 110 and 114 are a silicon nitride film or a polysilicon film.

The first material layer 110 has a thickness of about 500. The second insulating layer 112 is formed to have the same thickness or more as the storage electrode. For example, 10,000 -11
000 thickness range. Second material layer 114
Is formed in a thickness range of 1500-2000.

2 and 9, the second material layer 114
A storage electrode forming leakage pattern 116 is formed thereon. The leak pattern 116 is formed of, for example, a photoresist film. Rebus pattern 116
Using as a mask, the second material layer 114, the second insulating layer 112, and the first material layer 110 are sequentially etched to form at least one first opening 117. Since the second material layer 114 has an etching selectivity with respect to the second insulating layer 112, the size of the first opening 117 is prevented from increasing when the first opening 117 is formed.

Referring to FIGS. 3 and 10, after the rib pattern 116 is removed by asking or the like, the second material layer 114 including the first opening 117 is removed.
A first conductive layer such as a polysilicon film is formed thereon. First
The conductive layer is formed to a thickness of about 300.

The first conductive layer is etched by an anisotropic etch such as an etch-back process to form conductive layer spacers 118 on both side walls of the first opening 117. The conductive layer spacer 118 has a function of reducing the size of a storage electrode contact hole formed in a subsequent process. Therefore, it is possible to prevent the storage electrode contact hole from contacting the bit line.

4 and 11, the second material layer 11
The first insulating layer 108 is etched using the fourth and conductive layer spacers 118 as a mask. Then, the first
A storage electrode contact hole having a size relatively smaller than the size of the opening 117, that is, a second opening 119 is formed.

Referring to FIGS. 5 and 12, the second opening 119 and the first opening 117 are filled with a second conductive layer 120 such as a polysilicon film. Second insulating layer 1
The second conductive layer 120 and the second material layer 114 are planarized and etched so that the upper surface of the second conductive layer 12 is exposed. The planarization etching includes an etch-back process and a CMP (Chemical
Mechanical Polishing) is performed in any one of the steps.

Finally, when the second insulating layer 112 is removed by wet etching or the like, as shown in FIGS. 6 and 13, a self-aligned storage electrode 122 is formed in a second opening 119 which is a storage electrode contact hole. It is formed. At this time, when the second insulating layer 112 is removed, the first material layer 110 functions as an etching stop layer.
As a subsequent process, the first material layers 110 on both sides of the storage electrode 122 may be removed. But if the first
If the material layer 110 is a conductive layer, it must be removed.

Here, the first material layer 110 is removed by anisotropic etching such as an etch back process. In order to increase the surface area of the storage electrode 122 and increase the cell capacitance, a storage electrode spacer 124 is further formed as shown in FIGS.

The storage electrode spacer 124 is formed by
First, a polysilicon film for forming a storage electrode spacer is formed on the first material layer 110 including the storage electrode 122. The polysilicon film is formed to a thickness of about 300. The polysilicon film is etched by anisotropic etching such as an etch back process. At this time, the first material layer 1
Etching is performed until the upper surface of the first insulating layer 108 is exposed.

The formation of the storage electrode spacer 124 is as follows.
Step coverage in subsequent deposition processes, eg, deposition of dielectric film and plate electrode film
Will be improved. INDUSTRIAL APPLICABILITY The present invention can be applied to a semiconductor process for manufacturing a landing pad above a contact hole as well as a DRAM cell capacitor.

[0024]

According to the present invention, by combining the storage electrode contact hole forming step and the storage electrode forming step, the number of photo steps can be reduced, and the storage electrode contact hole and the storage electrode can be self-aligned. Therefore, there is an effect that misalignment of the storage electrode contact hole and the storage electrode can be prevented. Also, the size of the storage electrode contact hole can be reduced, and the margin between the storage electrode contact hole and the bit line can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view of a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line, in a process order.

FIG. 2 is a sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention in a process order, taken along a bit line extending direction;

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line.

FIG. 4 is a sectional view of a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line, in a process order;

FIG. 5 is a cross-sectional view taken along a bit line extending direction as a view showing a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention in the order of steps.

FIG. 6 is a cross-sectional view taken along an extending direction of a bit line as a view showing a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention in a process order.

FIG. 7 is a sectional view of a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line, in a process order.

FIG. 8 is a cross-sectional view taken along a word line extension direction, illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view of a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, taken in a word line extending direction, in the order of steps.

FIG. 10 is a sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention in a process order, taken along a word line extending direction.

FIG. 11 is a sectional view of a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut along an extending direction of a word line, in order of steps.

FIG. 12 is a sectional view of a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut along an extending direction of a word line, in order of steps.

FIG. 13 is a sectional view of a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut along an extending direction of a word line, in a process order.

FIG. 14 is a cross-sectional view taken along an extending direction of a word line as a diagram illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention in a process order.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor substrate 102 element isolation film 104 a-104 d gate electrode 106 a storage electrode pad 106 b bit line pad 108 first insulating layer 109 a-109 d bit line 110 first material layer 112 second insulating layer 114 second material layer 116 1 opening 118 conductive layer spacer 119 second opening 120 conductive layer 122 storage electrode 124 storage electrode spacer

Claims (12)

[Claims] A first insulating layer formed on the semiconductor substrate on which the gate electrode is formed, and a second insulating layer having a bit line in the first insulating layer; and a second insulating layer formed on the first insulating layer. Forming an insulating layer and a first material layer having an etch selectivity in sequence with an insulating layer interposed therebetween; forming a storage electrode forming leakage pattern on the second material layer; Etching the second material layer, the second insulating layer, and the first material layer sequentially using the Leaving pattern as a mask to form at least one first opening; and removing the Leaving pattern; Forming a spacer on a first conductive layer having an etching selectivity with the first insulating layer on both side walls of the first opening; and using the second material layer and the conductive layer spacer as a mask. Forming the at least one second opening by etching the first insulating layer, forming the second opening and the first opening, and exposing an upper surface of the second insulating layer. So the second
Planarizing and etching the conductive layer and the second material layer; and removing the second insulating layer using the first material layer as an etch stop layer to form a self-aligned storage electrode at the second opening. A method for manufacturing a DRAM cell capacitor, comprising: 2. The method as claimed in claim 1, wherein the first material layer and the second material layer are one of a silicon nitride film and a polysilicon film, respectively. . 3. The method according to claim 1, wherein the second insulating layer is formed to have at least the same thickness as the storage electrode. 4. The method according to claim 1, wherein the second insulating layer is 10,000 −1
2. The method as claimed in claim 1, wherein the thickness of the DRAM cell is formed within a thickness range of 1,000. 5. The method as claimed in claim 1, wherein the first conductive layer is formed to a thickness of about 300. 6. The DRAM cell capacitor as claimed in claim 1, wherein the conductive layer spacer has a size of the second opening relatively smaller than a size of the first opening. Manufacturing method. 7. The method of claim 1, wherein the planarization etching process is one of an etch-back process and a CMP process. 8. The method of manufacturing a DRAM cell capacitor according to claim 1, further comprising: after removing the second insulating layer, removing a first material layer on both sides of the storage electrode. 3. The method for manufacturing a DRAM cell capacitor according to 1. 9. The method according to claim 8, wherein the removal of the first material layer is performed by an anisotropic etching process.
A method for manufacturing a RAM cell capacitor. 10. The method of manufacturing a DRAM cell capacitor, comprising: forming a conductive layer on a first material layer including the storage electrode; and forming a conductive layer such that an upper surface of the first insulating layer is exposed. And etching the first material layer thereunder by an anisotropic etching process to form storage electrode spacers.
A method for manufacturing a RAM cell capacitor. 11. The method as claimed in claim 10, wherein the conductive layer is formed to a thickness of about 300. 12. The method according to claim 10, wherein the storage electrode spacer increases a surface area of the storage electrode.