JPH1131121A - Bus width conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a bus sizing when a CPU executes access with the addition of less hardware and by simple circuit constitution by collectively taking in 16 bits transfer data into an information processing unit (CPU). SOLUTION: At the time of transferring data from a CPU 101 to a memory 102 (at the time of writing data into the memory) by a control circuit 106, a first bus buffer 103 and a second bus buffer 104 are sequentially operated in every bus cycle and an address for the memory 102 is increased, and 16 bits data are transferred in bus cycles for two times in total. At the time of transferring data from the memory 102 to the CPU 101 (at the time of reading memory data), the first bus buffer 103 and the second bus buffer 104 are sequentially operated in every bus cycle and transfer data are outputted from the bus buffers. Transfer data of two bytes (16 bits) are taken into the CPU 101 in the last (second) bus cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus width conversion circuit, and more particularly, to a bus width conversion circuit in which a CPU is provided with a memory or I / O having a shorter bit width.
The present invention relates to a bus width conversion circuit that realizes a bus sizing function when accessing a peripheral device such as an O with a smaller amount of hardware and a simple circuit configuration.

[0002]

2. Description of the Related Art As a bus width conversion circuit, there has conventionally been one disclosed in Japanese Patent Application Laid-Open No. 2-28745 filed by the present applicant, but this bus width conversion circuit has a 16-bit CPU of 16 bits. This is for accessing a peripheral device such as a bit memory or an I / O. The present invention enables the reverse bus width conversion circuit, that is, the bus width conversion when the CPU accesses a peripheral device such as a memory or an I / O having a shorter bit width. Conventionally, when a CPU that processes 16-bit data as a bus width conversion circuit of this type accesses a peripheral device such as an 8-bit memory or an I / O having a shorter bit width, the data is conventionally processed by software processing. Access was performed in bit units, that is, in byte units. For example, in a configuration in which the lower 8 bits of the 16-bit data bus of the CPU are connected to the data input / output terminal of the 8-bit memory, when the CPU writes 16-bit data to the memory, The processing of writing the lower 8-bit data via the data bus, and then shifting the upper 8-bit data to the lower 8 bits and writing via the data bus is performed by software. Some C
In some PUs, such software processing is incorporated in a control program and automatically processed as a function called bus sizing, but many CPUs do not have the bus sizing function.

[0003]

As described above, when a CPU having no bus sizing function accesses a peripheral device such as a memory having a shorter bit width or an I / O, the processing for changing the access unit one by one is performed. There is a problem that it needs to be incorporated into the program, which hinders software productivity. In the case where the bus sizing function is realized by external hardware, for example, a buffer memory in a plurality of bytes may be configured on a data bus, and the buffer memory may be realized by writing / reading control of the buffer memory. However, there is a problem that the amount of hardware to be added is large, the control is complicated, and the circuit configuration is complicated. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems.
An object of the present invention is to provide a bus width conversion circuit that can realize a bus sizing function when accessing a peripheral device such as / O by adding less hardware and with a simple circuit configuration.

[0004]

In order to solve the above-mentioned problems, a bus width conversion circuit according to a first aspect of the present invention is a first information processing apparatus that handles M-bit (M is an arbitrary positive integer) data. Device and N bits (N is any positive integer, N <M, M =
The second one handles data of p · N + q; q <N)
A bus width conversion circuit for connecting an information processing device or a peripheral device, wherein each of the input / output terminal groups obtained by dividing the M-bit data input / output terminals of the first information processing device into N units; P + 1 bus buffers connected to an N-bit data input / output terminal of an information processing device or a peripheral device for bidirectional data transfer, and between the p bus buffers and the input / output terminals of the first information processing device Holding means for holding the potential of the data signal line for at least a certain period of time, and at the time of data transfer from the first information processing device to the second information processing device or a peripheral device, the (p + 1) bus buffers Are sequentially operated and the address is incremented, and the data transfer is performed in a total of (p + 1) bus cycles. When data is transferred from the bus buffer to the first information processing device, one of the (p + 1) bus buffers is sequentially operated in each bus cycle to output transfer data from the bus buffer. Control means for causing the first information processing apparatus to capture transfer data. Further, in the bus width conversion circuit according to claim 2, in the bus width conversion circuit according to claim 1, the holding means is a latch for holding a state of a data bus signal line in the first information processing device. Things. In addition, the bus width conversion circuit according to claim 3 provides the bus width conversion circuit according to claim 1.
In the bus width conversion circuit described above, the holding means is a capacitor connected between the data signal line and a ground potential. A bus width conversion circuit according to a fourth aspect is the bus width conversion circuit according to the first aspect, wherein the holding unit is a terminator. In the bus width conversion circuit of the present invention, at the time of data transfer from the first information processing device to the second information processing device or the peripheral device, one of the (p + 1) bus buffers is transferred every bus cycle by the control means. By sequentially operating and incrementing the address, the second information processing device or peripheral device sequentially takes in the bus buffer output, and performs the data transfer in a total of p + 1 bus cycles. At the time of data transfer from the device or the peripheral device to the first information processing device, one of the (p + 1) bus buffers is sequentially operated in each bus cycle to output transfer data from the bus buffer. The transfer data is held by the holding means, and the first information processing device collectively loads the transfer data in the last (p + 1) th bus cycle. That. Therefore, the first information processing device (CPU or the like)
A second information processing device having a shorter bit width (another CPU
) Or a peripheral device (memory, I / O, etc.) can be realized with a simpler circuit configuration by adding less hardware.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a bus width conversion circuit according to the present invention will be described below in detail with reference to the drawings in the order of [first embodiment] and [second embodiment].

[First Embodiment of the Invention] FIG. 1 is a circuit configuration diagram of a bus width conversion circuit according to a first embodiment of the present invention. The bus width conversion circuit according to the present embodiment includes a CPU (first information processing device) 101 that handles 16-bit (M = 16) data, an 8-bit (N = 8, M = 2 × N; p) =
2, q = 0) is connected to a memory (peripheral device) 102 composed of a RAM holding data. FIG.
In FIG. 1, portions not directly related to the bus width conversion circuit of the present application are omitted. Further, among the signal lines used in the embodiment, a negative logic signal is distinguished by adding a symbol “#” at the beginning of the reference numeral. In FIG. 1, the bus width conversion circuit of the present embodiment includes a first bus buffer 103,
The configuration includes a second bus buffer 104, a decoder 105, and a control circuit (control means) 106. The first bus buffer 103 and the second bus buffer 104 are respectively input / output terminal groups D0 to D7 and D8 when the 16-bit data input / output terminals of the CPU 101 are divided into eight.
To D15 and the 8-bit data input / output terminals D0 to D7 of the memory 102, and bidirectionally based on the read signal #RD from the CPU 101 and the bus buffer enable signals # E1 and # E2 from the control circuit 106. It performs data transfer. That is, the operations of first bus buffer 103 and second bus buffer 104 are activated based on bus buffer enable signals # E1 and # E2, and the direction of data transfer is controlled based on read signal #RD. Here, the first bus buffer 103 and the CPU 1
01 are connected to the input / output terminals D0 to D7 via the lower 8-bit data bus 111, and the second bus buffer 104 and the CP
The input / output terminals D8 to D15 of U101 are connected by an upper 8-bit data bus 112, and furthermore, the first bus buffer 103 and the second bus buffer 104 and the memory 102
Input / output terminals D0 to D7 are connected to an 8-bit data bus 113.
Connected by As will be described later, in the present embodiment, when reading memory data, the first bus buffer 103 is operated in the first bus cycle to output transfer data to the lower 8-bit data bus 111, and the last ( In the second) bus cycle, the second bus buffer 104
Is operated to output the transfer data on the upper 8-bit data bus 112, and the CPU 101 collectively captures the 16-bit transfer data. Therefore, the transfer data on the lower 8-bit data bus 111 is processed until the last bus cycle. It is necessary to keep the signal line potential. For this reason, in the present embodiment, as a holding unit for holding the signal line potential of the lower 8-bit data bus 111 for a certain period, a CPU is used.
A latch for holding the state of the signal line of the data bus 111 is provided inside 101. The holding means includes, in addition to the latch, a lower 8-bit data bus 111.
It is also possible to connect a capacitor between each signal line and the ground potential. Also, the terminator, ie, 3
State bidirectional bus transceiver (external pull-up when bidirectional 3-state output is high impedance,
(It is possible to actively pull up and pull down in an internal circuit without using a pull-down resistor.) Further, the decoder 105 generates a chip select signal #CE indicating access to the memory 102 based on the upper two bits A8 and A9 on the address bus 115 supplied from the CPU 101, and It is supplied to the select signal terminal #CS and the control circuit 106. In this embodiment, the memory 102 has a 256-byte configuration and is accessed by the address signals A0 to A7.
Although the chip select signal is generated in A9, the present invention is not limited to this.
In addition, if the configuration of the address signal is made to correspond to the number of memories that can be accessed by the CPU 101, the present embodiment can be applied to any memory configuration. Further, the control circuit 106 reads the read signal #RD and the write signal #WR from the CPU 101,
5, a first bus buffer enable signal # E1, a second bus buffer enable signal # E2, a memory write signal #MWR, a memory read signal #MRD, and an address signal for the memory 102. Generate A0. That is, the control circuit 10
6, when the data is transferred from the CPU 101 to the memory 102 (at the time of writing to the memory), the first bus buffer 103 and the second bus buffer 104 are sequentially operated in each bus cycle. The address for the memory 102 is incremented and 16-bit data is transferred in a total of two bus cycles. When data is transferred from the memory 102 to the CPU 101 (when reading memory data), the first bus is transferred every bus cycle. The buffer 103 and the second bus buffer 104 are sequentially operated to output transfer data from the bus buffer, and the CPU 101 loads two bytes (16 bits) of transfer data in the last (second) bus cycle. Next, the operation of the bus width conversion circuit of the present embodiment will be described in detail with reference to the timing charts shown in FIGS. First, FIG.
6 is a timing chart showing voltage waveforms of respective signals at the time of 6-bit data transfer (at the time of writing to a memory). Here, FIG. 2A shows a clock CLK for driving the information processing system, and FIG. 2B shows a chip select signal #CE.
FIG. 2C shows the write signal #WR, and FIG. 2D shows the first bus buffer enable signal # E1 and the address signal A.
0, FIG. 2E shows the second bus buffer enable signal #E
2. FIG. 2 (f) shows the memory write signal #MWR. First, when the CPU 101 issues the write signal #WR (to the “L” level) while the chip select signal #CE is at the “L” level and the memory 102 is selected, a write cycle to the memory 102 starts. Is done. In the first bus cycle WS1, the first bus buffer enable signal # E1 is set to "L" level and the first bus buffer 10
3 is operated, the lower 8-bit data on the data bus 111 is supplied to the memory 102 via the 8-bit data bus 113, and writing is performed while the memory write signal #MWR is at the "L" level. At this time, the address signal A
0 is set to the “L” level, and lower 8 bits of data are written to even addresses of the memory 102. This is achieved simply by making the generation logic of the address signal A0 the same as that of the first bus buffer enable signal # E1. This is for simplifying the logic of 106, and it is of course possible to write from an odd address of the memory. Next, in the last (second) bus cycle WS2, the second bus buffer 104 is operated by setting the second bus buffer enable signal # E2 to the “L” level, and the upper 8-bit data on the data bus 112 is converted to 8-bit data. The data is supplied to the memory 102 via the bus 113, and writing is performed while the memory write signal #MWR is at "L" level. At this time, the address signal A0 goes to the “H” level, and upper 8-bit data is written to the incremented (+1) address of the memory 102. Next, FIG.
5 is a timing chart showing voltage waveforms of respective signals when 16-bit data is transferred from the memory 102 to the CPU 101 (when reading memory data). Here, FIG.
3A is a clock CLK, FIG. 3B is a chip select signal #CE, FIG. 3C is a read signal #RD, FIG.
3D shows the first bus buffer enable signal # E1 and the address signal A0, FIG. 3E shows the second bus buffer enable signal # E2, and FIG. 3F shows the memory read signal #M.
RD is shown. First, the chip select signal #CE is "L"
When the memory 102 is selected as the level,
When the CPU 101 issues the read signal #RD (to the “L” level), a read cycle from the memory 102 is started. In the first bus cycle RS1, the first bus buffer enable signal # E1 is set to the "L" level,
Activate the bus buffer 103 and set the 8-bit data bus 1
13 is output to the lower 8-bit data bus 111. Next, in the last (second) bus cycle RS2, the second bus buffer enable signal #E
2 is set to the “L” level to operate the second bus buffer 104 and output the data read out on the 8-bit data bus 113 to the upper 8-bit data bus 112. At this time, the address signal A0 goes to the “H” level, and the upper eight bits from the incremented (+1) address in the memory 102.
Bit data is read. Then, the CPU 101 collectively takes in the 16-bit data on the lower 8-bit data bus 111 and the upper 8-bit data bus 112, and ends the read cycle. In FIGS. 2 and 3, the first bus buffer enable signal # E1 and the address signal A0 are set to "
The L level is used to prevent the data signal line of the 8-bit data bus 113 connected to the memory 102 from becoming undefined. In order to perform the above-described write and read operations, control is performed. Circuit 106
Is realized by a circuit configuration as shown in FIG. 4, for example. That is, in FIG. 4, the control circuit 106 has a two-input NA
It comprises an ND gate G1, a two-input OR gate G2, a NOT gate G3, a three-input OR gate G4, G5, and D-type flip-flops FF1, FF2. As described above, in the bus width conversion circuit of the present embodiment, when data is transferred from the CPU 101 to the memory 102 (when writing to the memory) by the control circuit 106, the first bus buffer 103 and the The second bus buffer 104 is sequentially operated, the address for the memory 102 is incremented, 16-bit data is transferred in a total of two bus cycles, and data is transferred from the memory 102 to the CPU 101 (when reading memory data). ) Includes a first bus buffer 10 for each bus cycle.
The third and second bus buffers 104 are sequentially operated to output transfer data from the bus buffer, and the last (second time)
In the bus cycle, the CPU 101 takes in the transfer data of 2 bytes (16 bits).
However, the bus sizing function when accessing the memory 102 having a shorter bit width can be realized with the addition of less hardware and a simple circuit configuration without using the software processing of the CPU 101.
In the present embodiment, as described above, writing and reading to and from the even address and the even + 1 address of the memory 102 are performed. Then, the restriction on the memory access can be released, and the writing and reading of the odd address and the odd + 1 address of the memory 102 become possible. In the write and read operations, when the bus cycle is insufficient, control by the wait signal WAIT may be added.

[Second Embodiment] FIG. 5 is a configuration diagram of a bus width conversion circuit according to a second embodiment of the present invention. Note that the bus width conversion circuit of the present embodiment is 32 bits (M = 16)
CPU (first information processing device) 501 that handles data
And 8 bits (N = 8, M = 4 × N; p = 4, q =
0) is connected to a memory (peripheral device) 502 including a RAM for holding the data of 0). In FIG. 5, the bus width conversion circuit of the present embodiment includes a first bus buffer 50.
3, the second bus buffer 504, the third bus buffer 50
5, a fourth bus buffer 506, a decoder 507, and a control circuit (control means) 508. The first bus buffer 503, the second bus buffer 504, the third bus buffer 505, and the fourth bus buffer 506 are respectively input / output terminal groups D0 to D7 when the 32-bit data input / output terminals of the CPU 501 are divided into eight. , D8-
D15, D16 to D23 and D24 to D31 are connected to the 8-bit data input / output terminals D0 to D7 of the memory 502, and the read signal #RD from the CPU 501 and the bus buffer enable signal # E1 from the control circuit 508 are connected.
Data transfer is performed bidirectionally based on # E2, # E3, and # E4. That is, each of the bus buffers 50 based on the bus buffer enable signals # E1 to # E4.
The operations of 3 to 506 are activated, and the direction of data transfer is controlled based on the read signal #RD. Here, the first bus buffer 503 and the input / output terminals D0 to D7 of the CPU 101 are used.
Are the data bus 511 and the second bus buffer 504 and C
The input / output terminals D8 to D15 of the PU 501 are connected to the data bus 5
12, the third bus buffer 505 and the input / output terminals D16 to D23 of the CPU 501 are the data bus 513, and the fourth bus buffer 506 and the input / output terminals D24 to
D31 is connected by a data bus 514, and the bus buffers 503 to 506 are connected to the input / output terminals D0 to D7 of the memory 502 by an 8-bit data bus 515. In this embodiment, when reading memory data, the first bus buffer 503 and the second bus buffer 5 are sequentially read in the first to third bus cycles.
04, the third bus buffer 505 is operated to output the transfer data on the data buses 511, 512, and 513, and the fourth bus buffer 506 is operated in the last (fourth) bus cycle to operate the data bus 514. Since the transfer data is output to the CPU 501 and the CPU 501 collectively captures the 32-bit transfer data, the data buses 511 and 5
It is necessary to hold the signal line potential for the transfer data on the lines 12 and 513 until the last bus cycle. Therefore, also in the present embodiment, the data buses 511, 512, 51
As a holding means for holding the signal line potential of No. 3 for a certain period, C
Either a latch is provided inside the PU 501 for holding the state of the signal line of each data bus, a capacitor is connected between each signal line of each data bus and the ground potential, or a terminator is provided. I do. The decoder 507 is connected to the address bus 5 supplied from the CPU 501.
16 based on the upper two bits A8 and A9 on the memory 5
Chip select signal # indicating that the access is to the access to H.02
CE is generated and supplied to the chip select signal terminal #CS of the memory 502 and the control circuit 508. Further, the control circuit 508 reads the read signal #RD from the CPU 501.
The first bus buffer enable signal # E1, the second bus buffer enable signal # E2, and the third bus buffer enable signal #E based on the write and write signals #WR and the chip select signal #CE from the decoder 507.
3, the fourth bus buffer enable signal # E4, and
A memory write signal #MWR, a memory read signal #MRD, and address signals A0 and A1 to the memory 102 are generated. That is, based on each control signal from the control circuit 508, when transferring 32-bit data from the CPU 501 to the memory 502 (when writing to the memory), the first bus buffer 503 and the second bus buffer
04, the third bus buffer 505 and the fourth bus buffer 506 are sequentially operated, the address for the memory 502 is incremented, and 32-bit data is transferred in a total of four bus cycles.
When transferring 32-bit data to the PU 501 (when reading memory data), the first bus buffer 503, the second bus buffer 504, the third bus buffer 505, and the fourth bus buffer 506 are sequentially operated in each bus cycle. Then, the transfer data is output from each bus buffer, and the CPU 501 fetches 4 bytes (32 bits) of transfer data in the last (fourth) bus cycle. The operation of the bus width conversion circuit of the present embodiment and the specific circuit configuration of the control circuit 508 for realizing the operation are the same as those of the first embodiment, and a description thereof will be omitted. As described above, the bus width conversion circuit of the present embodiment allows the CPU 501
However, the bus sizing function when accessing the memory 502 with a shorter bit width can be realized with the addition of less hardware and a simple circuit configuration without using software processing of the CPU 501.
In the first and second embodiments, the case where the CPU accesses the memory has been described as an example. However, the present invention is not limited to this, and I / Os with shorter bit widths and other MPs may be used.
It is also applicable when accessing U.

[0008]

As described above, according to the bus width conversion circuit of the present invention, the first information processing device that handles M-bit (M is an arbitrary positive integer) data and the N-bit (N is an arbitrary Is a positive integer and has a relationship of N <M and M = p · N + q; q <
In the bus width conversion circuit for connecting the second information processing device or the peripheral device handling the data of N), the control means controls the bus width conversion circuit when transferring data from the first information processing device to the second information processing device or the peripheral device. , P + every bus cycle
One of the bus buffers is sequentially operated, the address is incremented, and the output of the bus buffer is sequentially taken in by a second information processing device or a peripheral device. Make a transfer,
Also, at the time of data transfer from the second information processing device or the peripheral device to the first information processing device, p
One of the +1 bus buffers is sequentially operated to output transfer data from the bus buffer, and the output transfer data is held by the holding means, and the first transfer is performed in the last (p + 1) th bus cycle. Of the first information processing device (CP
U) can access a second information processing device (other CPU, etc.) or a peripheral device (memory, I / O, etc.) having a shorter bit width by a bus sizing function by adding less hardware. Further, it is possible to provide a bus width conversion circuit which can be realized with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a bus width conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation when a CPU writes 16-bit data to an 8-bit memory.

FIG. 3 is a timing chart illustrating an operation when a CPU reads 16-bit data from an 8-bit memory.

FIG. 4 is a specific circuit diagram of a control circuit in the bus width conversion circuit according to the first embodiment.

FIG. 5 is a circuit configuration diagram of a bus width conversion circuit according to a second embodiment of the present invention.

[Explanation of symbols]

101, 501 CPU (first information processing device) 102, 502 Memory (RAM, peripheral device) 103, 503 First bus buffer 104, 504 Second bus buffer 505 Third bus buffer 506 Fourth bus buffer 105, 507 Decoder 106, 508 Control circuit (control means) 111 Lower 8-bit data bus 112 Upper 8-bit data bus 113 8-bit data bus 115, 516 Address bus CLK Clock #CE Chip select signal #WR Write signal #RD Read signal # E1 First bus buffer enable signal # E2 Second bus buffer enable signal # E3 Third bus buffer enable signal # E4 Fourth bus buffer enable signal #MWR Memory write signal #MRD Memory read signal D0 to D7 Lower 8 bits Over data D8~D15 upper 8-bit data A0 address of the LSB A1~A7, A8, A9 address 511,512,513,514,515 8-bit data bus

Claims (4)

[Claims] 1. A first information processing apparatus that handles M-bit (M is an arbitrary positive integer) data and an N-bit (N is an arbitrary positive integer, N <M, M = p · N + q) Have; q <
N) a bus width conversion circuit for connecting to a second information processing device or a peripheral device that handles data, wherein each of the I / O terminals when the M-bit data input / output terminal of the first information processing device is divided into N units A terminal group, p + 1 bus buffers connected to an N-bit data input / output terminal of the second information processing device or the peripheral device for bidirectional data transfer, the p bus buffers and the first Holding means for holding the potential of the data signal line between the input / output terminals of the information processing device for at least a certain period of time; and a bus cycle for transferring data from the first information processing device to the second information processing device or a peripheral device. Each time, one of the (p + 1) bus buffers is sequentially operated and the address is incremented, and the data transfer is performed in a total of (p + 1) bus cycles. When data is transferred from a processing device or a peripheral device to the first information processing device, one of the p + 1 bus buffers is sequentially operated in each bus cycle to output transfer data from the bus buffer, and Control means for causing the first information processing device to take in transfer data in a first bus cycle. 2. The bus width conversion circuit according to claim 1, wherein said holding means is a latch for holding a state of a data bus signal line in said first information processing device. Conversion circuit. 3. The bus width conversion circuit according to claim 1, wherein said holding means is a capacitor connected between said data signal line and a ground potential. 4. The bus width conversion circuit according to claim 1, wherein in the bus width conversion circuit, the holding unit is a terminator.