JPH11307319A - Composite element - Google Patents
Composite elementInfo
- Publication number
- JPH11307319A JPH11307319A JP10787298A JP10787298A JPH11307319A JP H11307319 A JPH11307319 A JP H11307319A JP 10787298 A JP10787298 A JP 10787298A JP 10787298 A JP10787298 A JP 10787298A JP H11307319 A JPH11307319 A JP H11307319A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistor
- thermistor
- conductor
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Thermistors And Varistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、抵抗とサーミスタ
とを直列に接続すると共に、この抵抗及びサーミスタに
対して抵抗を並列に接続した複合素子に係り、詳しく
は、液晶等の温度補償回路用として回路基板等に表面実
装される温度補償用に好適な複合素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite device in which a resistor and a thermistor are connected in series and a resistor and a thermistor are connected in parallel with each other. The present invention relates to a composite device suitable for temperature compensation which is surface-mounted on a circuit board or the like.
【０００２】[0002]
【従来の技術】液晶の温度補償回路等において、所望の
抵抗−温度特性（リニア特性）を得るためには、サーミ
スタと抵抗を組み合わせて直列回路ないし並列回路を構
成する必要がある。従来、このような場合においては、
サーミスタ及びチップ抵抗等の複数の電子部品を個々に
同一基板上にフローあるいはリフローはんだ付けにより
実装することが行われている。2. Description of the Related Art In order to obtain a desired resistance-temperature characteristic (linear characteristic) in a liquid crystal temperature compensating circuit or the like, it is necessary to form a series circuit or a parallel circuit by combining a thermistor and a resistor. Conventionally, in such a case,
2. Description of the Related Art A plurality of electronic components such as a thermistor and a chip resistor are individually mounted on the same substrate by flow or reflow soldering.
【０００３】[0003]
【発明が解決しようとする課題】しかし、このようにサ
ーミスタ、チップ抵抗等の個々の電子部品を複数個用い
て回路を構成する場合には、複数の部品を同一基板上に
実装するため、必然的に実装面積が増大し、回路の小型
化を進める上で大きな制約となっていた。However, when a circuit is formed by using a plurality of individual electronic components such as a thermistor and a chip resistor as described above, since a plurality of components are mounted on the same substrate, it is inevitable. Therefore, the mounting area has been increased, which has been a great limitation in miniaturizing the circuit.
【０００４】本発明は、サーミスタ素体の表面に抵抗材
料を厚膜形成する手法を採用することにより、サーミス
タと抵抗を直列に接続し、更に、このサーミスタと抵抗
に対して抵抗を並列に接続した回路と等価な特性を１チ
ップで実現した複合素子を提供することを目的とする。The present invention employs a technique of forming a thick resistive material on the surface of a thermistor body, thereby connecting the thermistor and the resistor in series, and further connecting the resistor in parallel with the thermistor and the resistor. It is an object of the present invention to provide a composite device that realizes characteristics equivalent to a circuit obtained by one chip.
【０００５】[0005]
【課題を解決するための手段】本発明の複合素子は、チ
ップ状のサーミスタ素体と、該サーミスタ素体の両端面
に形成された端子電極と、該サーミスタ素体の側面に形
成された第１の抵抗体層と、該第１の抵抗体層が形成さ
れた該サーミスタ素体の側面とは異なる側面に形成され
た第２の抵抗体層とを備えてなり、一方の端子電極、該
第１の抵抗体層、該サーミスタ素体及び他方の端子電極
がこの順に直列接続されると共に、一方の端子電極、該
第２の抵抗体層及び他方の端子電極がこの順に直列接続
されてなることを特徴とするものである。A composite device according to the present invention comprises a chip-shaped thermistor element, terminal electrodes formed on both end faces of the thermistor element, and a first electrode formed on a side face of the thermistor element. A first resistor layer, and a second resistor layer formed on a side surface different from a side surface of the thermistor element body on which the first resistor layer is formed. The first resistor layer, the thermistor element, and the other terminal electrode are connected in series in this order, and one terminal electrode, the second resistor layer, and the other terminal electrode are connected in series in this order. It is characterized by the following.
【０００６】かかる本発明によれば、サーミスタと抵抗
を直列に接続し、更に、このサーミスタと抵抗に対して
抵抗を並列に接続した回路と等価な、所望の抵抗一温度
特性を有する複合素子を単体の素子として実現すること
が可能となる。本発明による複合素子を利用すれば、サ
ーミスタ及び抵抗より構成している温度補償回路等、電
子回路の小型化が可能となる。特に、小型化ニーズの強
い液晶等の温度補償用回路として、本素子は有用であ
る。According to the present invention, there is provided a composite element having a desired resistance-temperature characteristic equivalent to a circuit in which a thermistor and a resistor are connected in series and a resistor is connected in parallel with the thermistor and the resistor. It can be realized as a single element. The use of the composite device according to the present invention enables the miniaturization of an electronic circuit such as a temperature compensation circuit including a thermistor and a resistor. In particular, this element is useful as a temperature compensating circuit for a liquid crystal or the like for which there is strong need for miniaturization.
【０００７】[0007]
【発明の実施の形態】以下に図面を参照して本発明の実
施の形態を詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【０００８】図１は実施の形態に係る複合素子の断面図
であり、サーミスタ素体１の両面に導電体層２、３が形
成されている。図の上面側の導電体層２の上には、所定
の間隔をあけて絶縁体層４、５が形成され、この絶縁体
層４、５同士の間にまたがるようにして絶縁体層４，５
間の導電体層２上に導電体層６が形成されている。FIG. 1 is a cross-sectional view of a composite device according to an embodiment. Conductive layers 2 and 3 are formed on both surfaces of a thermistor body 1. Insulator layers 4 and 5 are formed at predetermined intervals on conductor layer 2 on the upper surface side in the drawing, and insulator layers 4 and 5 are formed so as to extend between insulator layers 4 and 5. 5
The conductor layer 6 is formed on the conductor layer 2 between them.
【０００９】この導電体層６から離隔して絶縁体層４の
上に導電体層７が形成されている。導電体層６、７同士
の間にまたがって、抵抗体層（第１の抵抗体層）８が形
成されている。A conductor layer 7 is formed on insulator layer 4 so as to be spaced from conductor layer 6. A resistor layer (first resistor layer) 8 is formed between the conductor layers 6 and 7.
【００１０】この導電体層７の一部のみを露出させるよ
うに、且つ抵抗体層８、導電体層６及び絶縁体層５を覆
うように絶縁体層９が形成されている。この絶縁体層９
はサーミスタ素体１の図の右端に達しているが、サーミ
スタ素体１の左端からは離隔しており、この絶縁体層９
の左方において導電体層７の一部が絶縁体層９で覆われ
ておらず、後述の端子電極１７が導電体層７に直に接す
るように設けられている。An insulator layer 9 is formed so as to expose only a part of the conductor layer 7 and to cover the resistor layer 8, the conductor layer 6 and the insulator layer 5. This insulator layer 9
Reaches the right end of the thermistor body 1 in the figure, but is separated from the left end of the thermistor body 1.
A part of the conductor layer 7 is not covered with the insulator layer 9 on the left side of the figure, and a terminal electrode 17 described later is provided so as to be in direct contact with the conductor layer 7.
【００１１】サーミスタ素体１の図の下面側では、導電
体層３上に絶縁体層１０，導電体層１１，１２、抵抗体
層（第２の抵抗体層）１３及び絶縁体層１４が積層形成
されている。絶縁体層１０は、図の左端縁に達している
が、右端縁からは離隔しており、導電体層３はこの右端
側において絶縁体層１０によって覆われていない。導電
体層１１，１２はそれぞれ、図の左端縁及び右端縁か
ら、互いに所定の間隔をあけて形成され、導電体層１
１，１２同士の間にまたがるようにして、導電体層１
１，１２上に抵抗体層１３が形成されている。この抵抗
体層１３の両端は、図の左端縁及び右端縁からは離隔し
ている。絶縁体層１４は、図の左端縁及び右端縁の両端
縁から離隔して、抵抗体層１３上に設けられており、導
電体層１１の左端側及び導電体層１２の右端側は絶縁体
層１４で覆われていない。On the lower surface side of the thermistor body 1 in the figure, an insulator layer 10, conductor layers 11, 12, a resistor layer (second resistor layer) 13 and an insulator layer 14 are provided on the conductor layer 3. It is formed by lamination. The insulator layer 10 reaches the left edge of the figure but is separated from the right edge, and the conductor layer 3 is not covered by the insulator layer 10 on the right end side. The conductor layers 11 and 12 are formed at predetermined intervals from the left edge and the right edge of the figure, respectively.
1 and 12 so that the conductive layer 1
A resistor layer 13 is formed on the layers 1 and 12. Both ends of the resistor layer 13 are separated from the left edge and the right edge in the figure. The insulator layer 14 is provided on the resistor layer 13 so as to be separated from both left and right edges of the drawing, and the left end of the conductor layer 11 and the right end of the conductor layer 12 are insulators. Not covered by layer 14.
【００１２】サーミスタ素体１の両端面には絶縁体層１
５、１６が形成され、その上に端子電極１７、１８が形
成されている。左側の絶縁体層１５は導電体層２、３と
端子電極１７とを絶縁し、右側の絶縁体層１６は、導電
体層２、３と端子電極１８とを絶縁している。このた
め、図においてサーミスタ素体１の上面側では、端子電
極１７は導電体層７にのみ導通している。また、サーミ
スタ素体１の下面側では、端子電極１７は導電体層１１
にのみ導通し、端子電極１８は導電体層１２（及び導電
体層３）にのみ導通している。An insulating layer 1 is provided on both end faces of the thermistor body 1.
5 and 16 are formed, and terminal electrodes 17 and 18 are formed thereon. The insulator layer 15 on the left insulates the conductor layers 2 and 3 from the terminal electrode 17, and the insulator layer 16 on the right insulates the conductor layers 2 and 3 from the terminal electrode 18. For this reason, in the figure, on the upper surface side of the thermistor element 1, the terminal electrode 17 is electrically connected only to the conductor layer 7. On the lower surface side of the thermistor body 1, the terminal electrode 17 is
And the terminal electrode 18 is electrically connected only to the conductor layer 12 (and the conductor layer 3).
【００１３】従って、図２（ａ）の等価回路の通り、端
子電極１７−導電体層７−抵抗体層８−導電体層６−導
電体層２−サーミスタ素体１−導電体層３−導電体層１
２−端子電極１８のように接続された抵抗・サーミスタ
直列接続と、この直列接続に対して、端子電極１７−導
電体層１１−抵抗体層１３−導電体層１２−端子電極１
８のように接続された抵抗が並列に接続された複合素子
が得られる。Accordingly, as shown in the equivalent circuit of FIG. 2A, the terminal electrode 17-conductor layer 7-resistance layer 8-conductor layer 6-conductor layer 2-thermistor element 1-conductor layer 3- Conductor layer 1
2-series connection of a resistor and thermistor connected like the terminal electrode 18 and, for this series connection, the terminal electrode 17-the conductor layer 11-the resistor layer 13-the conductor layer 12-the terminal electrode 1
As a result, a composite device in which the resistors connected as shown in FIG. 8 are connected in parallel is obtained.
【００１４】なお、図示はしないが、素体１の図１の紙
面と平行方向の側面にも絶縁体層が設けられている。Although not shown, an insulator layer is also provided on the side surface of the element body 1 in the direction parallel to the plane of FIG.
【００１５】次に、この複合素子の製造方法について図
２（ｂ）を参照して説明する。Next, a method of manufacturing the composite device will be described with reference to FIG.
【００１６】まず、サーミスタ薄板２１の両面の全面に
導電体層２２、２３を形成する。この導電体層２２の上
に膜状の絶縁体層２４を形成し、導電体層２３の上に絶
縁体層２５を形成する。なお、絶縁体層２４、２５は同
一方向に延びている。絶縁体層２４同士の間及び絶縁体
層２５同士の間には、それぞれ所定の間隔があいてい
る。First, conductor layers 22 and 23 are formed on the entire surface of both surfaces of the thermistor thin plate 21. A film-like insulator layer 24 is formed on the conductor layer 22, and an insulator layer 25 is formed on the conductor layer 23. Note that the insulator layers 24 and 25 extend in the same direction. A predetermined interval is provided between the insulator layers 24 and between the insulator layers 25.
【００１７】絶縁体層２４，２４同士の間の導電体層２
２上に帯状の導電体層２６を形成すると共に、絶縁体層
２４の上にのみ帯状の導電体層２７を形成する。また、
導電体層２３の露出面から絶縁体層２５，２５の上面に
かけて、帯状の導電体層２８を形成する。導電体層２
６、２７の間には所定の間隔があいている。また、導電
体層２８同士の間にも所定の間隔があいている。The conductor layer 2 between the insulator layers 24, 24
2, a strip-shaped conductor layer 26 is formed, and a strip-shaped conductor layer 27 is formed only on the insulator layer 24. Also,
A strip-shaped conductor layer 28 is formed from the exposed surface of the conductor layer 23 to the upper surfaces of the insulator layers 25, 25. Conductor layer 2
There is a predetermined interval between 6 and 27. Also, there is a predetermined space between the conductor layers 28.
【００１８】導電体層２６、２７にまたがるように帯状
の抵抗体層２９を形成すると共に、導電体層２８，２８
にまたがるように帯状の抵抗体層３０を形成する。抵抗
体層２９、導電体層２６及び絶縁体層２４を覆い、導電
体層２７については大部分が露出するように絶縁体層３
１（図示略）を帯状に形成する。また、抵抗体層３０を
覆い、導電体層２８の大部分は露出するように絶縁体層
３２（図示略）を形成する。A strip-shaped resistor layer 29 is formed so as to straddle the conductor layers 26 and 27, and the conductor layers 28 and 28 are formed.
A strip-shaped resistor layer 30 is formed so as to straddle. The insulator layer 3 covers the resistor layer 29, the conductor layer 26, and the insulator layer 24 so that the conductor layer 27 is largely exposed.
1 (not shown) is formed in a band shape. An insulator layer 32 (not shown) is formed so as to cover the resistor layer 30 and expose most of the conductor layer 28.
【００１９】次いで、これらの帯状の層の長手方向と直
交方向にサーミスタ薄板２１を切断し、短冊状の素体を
形成する。Next, the thermistor thin plate 21 is cut in a direction orthogonal to the longitudinal direction of these strip-shaped layers to form a strip-shaped element.
【００２０】次に、この短冊状の素体の切り出した側面
に絶縁体層を形成した後、短冊状素体をその長手方向と
直交方向に２点鎖線Ｘで示すように導電体層２７の抵抗
体層２９と反対側の端縁（図の左端縁。この端縁は、絶
縁体層２５の端縁と同位置にある。）に沿って切断して
チップとする。なお、図２（ｂ）の２点鎖線Ｘはこのと
きの切断予定線を示す。このチップの両端面に絶縁性樹
脂層を塗着して絶縁体層１５，１６を形成した後、端子
電極１７，１８を形成することにより、複合素子が得ら
れる。Next, after an insulating layer is formed on the cut side surface of the strip-shaped element, the strip-shaped element is placed on the conductor layer 27 in a direction orthogonal to the longitudinal direction as indicated by a two-dot chain line X. The chip is cut along the edge opposite to the resistor layer 29 (the left edge in the figure; this edge is located at the same position as the edge of the insulator layer 25). Note that the two-dot chain line X in FIG. 2B indicates the planned cutting line at this time. After forming insulating layers 15 and 16 by coating insulating resin layers on both end surfaces of the chip, and forming terminal electrodes 17 and 18, a composite element is obtained.
【００２１】なお、特に本発明を限定するものではない
が、サーミスタ材料としてはＭｎ−Ｃｏ−Ｃｕ系、Ｍｎ
−Ｃｏ−Ｆｅ系のものなどを用いることができる。Although the present invention is not particularly limited, examples of the thermistor material include Mn-Co-Cu,
-Co-Fe-based materials and the like can be used.
【００２２】絶縁体層２４、２５、３１及び３２（図示
略）は、例えばガラスペーストをスクリーン印刷等によ
り印刷し、乾燥後焼き付けることにより形成される。な
お、絶縁体層３１及び３２は後にそれぞれ絶縁体層９及
び１４を構成する。The insulator layers 24, 25, 31 and 32 (not shown) are formed, for example, by printing a glass paste by screen printing or the like, drying and baking. Note that the insulator layers 31 and 32 will later constitute the insulator layers 9 and 14, respectively.
【００２３】導電体層２２、２３、２６、２７、２８
は、例えば導電性電極ペーストをスクリーン印刷等によ
り印刷し、乾燥後焼き付けることにより形成される。な
お、導電体層、抵抗体層及び誘電体層の焼き付けを一緒
に行うようにしても良い。Conductor layers 22, 23, 26, 27, 28
Is formed, for example, by printing a conductive electrode paste by screen printing or the like, drying and baking. Note that the conductor layer, the resistor layer, and the dielectric layer may be baked together.
【００２４】抵抗体層２９、３０は、ＲｕＯ2 系等の抵
抗体ペーストをスクリーン印刷等により印刷し、乾燥後
焼き付けることにより形成される。The resistor layers 29 and 30 are formed by printing a resistor paste of RuO 2 or the like by screen printing or the like, drying and baking.
【００２５】端子電極１７，１８はＡｇ等の導電性下地
電極とめっき層（Ｎｉめっきとはんだめっき）とで形成
される。The terminal electrodes 17 and 18 are formed of a conductive base electrode such as Ag and a plating layer (Ni plating and solder plating).
【００２６】なお、絶縁体層は、一液性エポキシ配合樹
脂等の絶縁性樹脂材料を塗付することによっても形成で
きる。この絶縁性樹脂材料を用いて絶縁体層を形成した
場合、端子電極１７、１８は導電性樹脂材料を用いて形
成される。この場合、端子電極は、樹脂系下地電極とめ
っき層（Ｎｉめっきとはんだめっき）とで形成するのが
好ましい。The insulator layer can also be formed by applying an insulating resin material such as a one-component epoxy resin. When the insulating layer is formed using this insulating resin material, the terminal electrodes 17 and 18 are formed using a conductive resin material. In this case, the terminal electrode is preferably formed of a resin base electrode and a plating layer (Ni plating and solder plating).
【００２７】このような本発明の複合素子では、サーミ
スタ素体のサーミスタ材料組成、素体形状及び電極面
積、抵抗体層の抵抗体材料組成及び電極間距離等を適宜
調整することにより、所望の抵抗−温度特性を実現でき
る。In such a composite device of the present invention, the desired thermistor material composition, element shape and electrode area of the thermistor element body, the resistor material composition of the resistor layer, the distance between the electrodes, etc. are appropriately adjusted to obtain the desired values. Resistance-temperature characteristics can be realized.
【００２８】[0028]
【実施例】以下、実施例について説明する。Embodiments will be described below.
【００２９】（１）３０×５０×０．６ｍｍの寸法の薄
板状サーミスタ（Ｍｎ−Ｃｏ−Ｆｅ系焼結体）２１を用
意し、その薄板状素体の両面に市販の導電性電極ペース
ト（Ａｇ）を素体全面にスクリーン印刷法により印刷
し、乾燥後（１５０℃、１５分）、８５０℃×１５分で
焼き付け、導電体層２２、２３を形成した。(1) A sheet thermistor (Mn-Co-Fe sintered body) 21 having a size of 30 × 50 × 0.6 mm is prepared, and a commercially available conductive electrode paste ( Ag) was printed on the entire surface of the element body by a screen printing method, dried (150 ° C., 15 minutes), and baked at 850 ° C. × 15 minutes to form conductor layers 22 and 23.
【００３０】（２）この導電体層を形成した薄板状素体
の両面に所定の帯状パターンとなるように、市販のガラ
スペースト（絶縁性）をスクリーン印刷法により印刷
し、乾燥後（１５０℃、１５分）、８５０℃×１５分で
焼き付け、絶縁体層２４、２５を形成した。なお、絶縁
体層２４の帯状ガラスの幅：１．５２ｍｍ、帯状ガラス
の間隔：０．１０ｍｍとした。また、絶縁体層２５の帯
状ガラスの幅：１．５２ｍｍ、帯状ガラスの間隔：０．
１０ｍｍとした。(2) A commercially available glass paste (insulating) is printed by a screen printing method so as to form a predetermined band pattern on both sides of the thin plate body on which the conductor layer is formed, and dried (150 ° C.). , 15 minutes) and baking at 850 ° C. × 15 minutes to form insulator layers 24 and 25. The width of the strip glass of the insulator layer 24 was 1.52 mm, and the interval between the strip glasses was 0.10 mm. In addition, the width of the strip glass of the insulator layer 25: 1.52 mm, and the interval of the strip glass: 0.1 mm.
It was 10 mm.
【００３１】（３）この絶縁体層２４、２５を形成した
薄板状素体の両面に導電性電極ペースト（Ａｇ）をスク
リーン印刷法により所定のパターンとなるように印刷
し、乾燥させ（１５０℃、１５分）、帯状の導電体層２
６、２７及び導電体層２８を形成した。導電体層２６の
幅は０．３０ｍｍ、導電体層２７の幅は０．５０ｍｍ、
導電体層２６と２７との間隔は、抵抗体層形成部分で
０．５０ｍｍとした。また、導電体層２８の幅は０．５
６ｍｍ、導電体層２８同士の間隔は０．５０ｍｍとし
た。(3) A conductive electrode paste (Ag) is printed on both sides of the thin plate-shaped body on which the insulator layers 24 and 25 are formed by a screen printing method so as to form a predetermined pattern, and dried (150 ° C.). , 15 minutes), strip-shaped conductor layer 2
6, 27 and the conductor layer 28 were formed. The width of the conductor layer 26 is 0.30 mm, the width of the conductor layer 27 is 0.50 mm,
The distance between the conductor layers 26 and 27 was 0.50 mm at the portion where the resistor layer was formed. The width of the conductor layer 28 is 0.5
6 mm, and the interval between the conductor layers 28 was 0.50 mm.
【００３２】（４）次に、薄板状素体の一方の面に、抵
抗体ペーストをスクリーン印刷法により所定のパターン
となるように印刷し、乾燥後（１５０℃、１５分）、８
５０℃×１５分で焼き付け、幅０．８０ｍｍの帯状の抵
抗体層２９及び幅０．８０ｍｍの帯状の抵抗体層３０を
形成した。なお、抵抗材料は酸化ルテニウム（Ｒｕ
Ｏ2）系の材料を用いた。(4) Next, a resistor paste is printed on one surface of the thin plate element by a screen printing method so as to form a predetermined pattern, and dried (150 ° C., 15 minutes).
Baking was performed at 50 ° C. for 15 minutes to form a strip-shaped resistor layer 29 having a width of 0.80 mm and a strip-shaped resistor layer 30 having a width of 0.80 mm. The resistance material is ruthenium oxide (Ru)
An O 2 ) -based material was used.
【００３３】（５）さらに、この薄板状素体の両面にガ
ラスペーストをスクリーン印刷法により所定のパターン
となるように印刷し、乾燥後（１５０℃、１５分）、８
５０℃×１５分で焼き付け、絶縁体層３１，３２（図示
略）を形成した。(5) Further, a glass paste is printed on both sides of the thin plate-like body by a screen printing method so as to form a predetermined pattern, and after drying (150 ° C., 15 minutes), 8
Baking was performed at 50 ° C. for 15 minutes to form insulator layers 31 and 32 (not shown).
【００３４】（６）この薄板状素体を、ダイシングマシ
ーンを用いて、幅０．７２ｍｍの短冊状素体に切断し
た。(6) The thin plate was cut into strips having a width of 0.72 mm using a dicing machine.
【００３５】（７）この短冊状素体の２面（切断面）に
市販のガラスペーストをスクリーン印刷法により印刷
し、乾燥後（１５０℃、１５分）、８５０℃×１５分で
焼き付け、絶縁体層を形成した。(7) A commercially available glass paste is printed on two surfaces (cut surfaces) of the strip-shaped body by a screen printing method, dried (150 ° C., 15 minutes), baked at 850 ° C. for 15 minutes, and insulated. A body layer was formed.
【００３６】（８）この短冊状素体をダイシングマシー
ンを用いて図２（ｂ）のＸに示す位置で幅１．５２ｍｍ
のチップ状素体に切断した。(8) Using a dicing machine, this strip-shaped body is 1.52 mm wide at the position indicated by X in FIG. 2B.
Was cut into chips.
【００３７】（９）このチップ状素体の両端に、絶縁性
樹脂をディプ法により付着させ、乾燥後（１２０℃、１
５分）、１５０℃×３０分で熱硬化させ、絶縁体層１
５、１６を形成した。絶縁性樹脂は一液性エポキシ配合
樹脂を用いた。(9) An insulating resin is adhered to both ends of the chip-shaped element by a dip method, and dried (at 120 ° C., 1 ° C.).
5 minutes), and heat cured at 150 ° C. × 30 minutes to form an insulator layer 1
5 and 16 were formed. As the insulating resin, a one-component epoxy compound resin was used.
【００３８】（１０）このチップ状素体の両端に、市販
の樹脂系フィラーのＡｇ電極をディップ法で付着させ、
乾燥後（１５０℃、１５分）、１５０℃×１時間で熱硬
化させ、その上に電解バレルメッキ法により、Ｎｉめっ
き、はんだめっきし、端子電極１７、１８を形成した。
Ｎｉめっき厚さは約４μｍ、はんだめっき厚さは約５μ
ｍである。これにより、図２（ａ）の等価回路の複合素
子が得られた。(10) Ag electrodes of a commercially available resin filler are attached to both ends of the chip-like element by a dipping method,
After drying (150 ° C., 15 minutes), it was thermally cured at 150 ° C. × 1 hour, and Ni plating and solder plating were performed thereon by electrolytic barrel plating to form terminal electrodes 17 and 18.
Ni plating thickness is about 4μm, solder plating thickness is about 5μ
m. As a result, a composite device having the equivalent circuit of FIG. 2A was obtained.
【００３９】この複合素子は、 サーミスタＴｈ：６８ｋΩ（３６５０Ｋ） 抵抗Ｒ1：２２ｋΩ 抵抗Ｒ2：１８ｋΩ であり、図３に示す抵抗−温度（Ｒ−Ｔ）特性（リニア
な抵抗−温度特性）を示した。This composite device has a thermistor Th: 68 kΩ (3650 K), a resistance R 1 : 22 kΩ, and a resistance R 2 : 18 kΩ. Indicated.
【００４０】[0040]
【発明の効果】以上詳述した通り、本発明によれば、サ
ーミスタ素体の一方の側面に、絶縁体層、導電体層、抵
抗体層を所定のパターンに形成し、他方の側面に絶縁体
層、導電体層、抵抗体層を所定のパターンに形成するこ
とにより、サーミスタと抵抗を直列に接続し、更に、こ
のサーミスタと抵抗に対して抵抗を並列に接続した回路
と等価な複合素子であって、所望の抵抗−温度特性（リ
ニアな抵抗−温度特性）を有する複合素子を提供するこ
とができる。As described above in detail, according to the present invention, an insulator layer, a conductor layer, and a resistor layer are formed in a predetermined pattern on one side of the thermistor body, and an insulating layer is formed on the other side. A composite element equivalent to a circuit in which a body layer, a conductor layer, and a resistor layer are formed in a predetermined pattern to connect a thermistor and a resistor in series, and further connect a resistor in parallel with the thermistor and the resistor. Thus, it is possible to provide a composite device having desired resistance-temperature characteristics (linear resistance-temperature characteristics).
【００４１】この複合素子によれば、サーミスタと抵抗
を直列に接続し、更に、このサーミスタと抵抗に対して
抵抗を並列に接続した回路と等価な特性を有する複合素
子を単体の素子として実現できるため、例えば、サーミ
スタ、抵抗から構成される温度補償回路等、各種回路の
小型化が可能となる。特に、小型化ニーズの強い液晶等
の温度補償用回路として、本素子は有用である。According to this composite device, a composite device having characteristics equivalent to a circuit in which a thermistor and a resistor are connected in series and a resistor is connected in parallel with the thermistor and the resistor can be realized as a single device. Therefore, for example, various circuits such as a temperature compensation circuit including a thermistor and a resistor can be miniaturized. In particular, this element is useful as a temperature compensating circuit for a liquid crystal or the like for which there is a strong need for miniaturization.
【図１】実施の形態に係る複合素子の断面図である。FIG. 1 is a cross-sectional view of a composite device according to an embodiment.
【図２】図２（ａ）は、図１に示す複合素子の等価回路
図、図２（ｂ）は製造途中図である。FIG. 2A is an equivalent circuit diagram of the composite device shown in FIG. 1, and FIG.
【図３】実施例１で製造された複合素子の抵抗−温度特
性を示すグラフである。FIG. 3 is a graph showing resistance-temperature characteristics of the composite device manufactured in Example 1.
１ サーミスタ素体 ２，３，６，７，１１，１２ 導電体層 ４，５，９，１０，１４，１５，１６ 絶縁体層 ８，１３ 抵抗体層 １２ 誘電体層 １７，１８ 端子電極 ２１ サーミスタ薄板 ２２，２３，２６，２７，２８ 導電体層 ２４，２５，３１，３２ 絶縁体層 ２９，３０ 抵抗体層 DESCRIPTION OF SYMBOLS 1 Thermistor body 2,3,6,7,11,12 Conductor layer 4,5,9,10,14,15,16 Insulator layer 8,13 Resistor layer 12 Dielectric layer 17,18 Terminal electrode 21 Thermistor thin plate 22, 23, 26, 27, 28 Conductor layer 24, 25, 31, 32 Insulator layer 29, 30 Resistor layer
Claims (1)
スタ素体の両端面に形成された端子電極と、該サーミス
タ素体の側面に形成された第１の抵抗体層と、該第１の
抵抗体層が形成された該サーミスタ素体の側面とは異な
る側面に形成された第２の抵抗体層とを備えてなり、 一方の端子電極、該第１の抵抗体層、該サーミスタ素体
及び他方の端子電極がこの順に直列接続されると共に、
一方の端子電極、該第２の抵抗体層及び他方の端子電極
がこの順に直列接続されてなることを特徴とする複合素
子。1. A chip-shaped thermistor element, terminal electrodes formed on both end faces of the thermistor element, a first resistor layer formed on side surfaces of the thermistor element, A second resistor layer formed on a side surface different from the side surface of the thermistor body on which the resistor layer is formed; one terminal electrode, the first resistor layer, and the thermistor body And the other terminal electrode are connected in series in this order,
A composite device comprising one terminal electrode, the second resistor layer, and the other terminal electrode connected in series in this order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10787298A JP3419305B2 (en) | 1998-04-17 | 1998-04-17 | Composite element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10787298A JP3419305B2 (en) | 1998-04-17 | 1998-04-17 | Composite element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11307319A true JPH11307319A (en) | 1999-11-05 |
| JP3419305B2 JP3419305B2 (en) | 2003-06-23 |
Family
ID=14470237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10787298A Expired - Fee Related JP3419305B2 (en) | 1998-04-17 | 1998-04-17 | Composite element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3419305B2 (en) |
-
1998
- 1998-04-17 JP JP10787298A patent/JP3419305B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3419305B2 (en) | 2003-06-23 |
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