JPH11306764A - Swl ferroelectric memory and drive circuit therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a nonvolatile memory using no plate line and a drive circuit therefor. SOLUTION: A large number of cells each comprising a transistor and a dielectric capacitor are arranged in blocks and when a data is written in that cell or read out therefrom, the blocks are arranged on the left and right sides of an SWL(slip word line) for driving a transistor and a core containing a bit line control section for controlling read/write of data in the bit line direction is arranged between respective blocks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory, and more particularly, to a method using a word line instead of a plate line and using one word line for two word lines.
Split word line ((Split
Word Line (SWL) relates to a ferroelectric memory device and its driving circuit.

[0002]

2. Description of the Related Art In general, a ferroelectric memory (Ferroelect) having a data processing speed comparable to that of a DRAM used as a semiconductor memory device and storing data even when power is turned off.
ric Random Access Memory (RAM) has attracted attention as a next-generation storage device. An FRAM uses a capacitor as a storage device like a DRAM, but removes an electric field by using a ferroelectric as a dielectric material of the capacitor (that is, by using a high remanent polarization that is a ferroelectric characteristic). Is a storage device that does not lose data.

FIG. 1A is a characteristic diagram showing a hysteresis loop of a general ferroelectric, and FIG. 1B is a configuration diagram of a unit capacitor of a general ferroelectric memory. As shown in the hysteresis loop of FIG. 1A, the polarization induced by the electric field is maintained at a certain amount (d, a state) without disappearing due to the existence of spontaneous polarization even when the electric field is removed. This d, a
The state was applied to 1 and 0, respectively, and applied as a storage device.

In FIG. 1B, a state in which a positive (+) voltage is applied to the node 1 is a state c in FIG. 1A, and a state in which no voltage is applied thereafter is a state d. Conversely, node 1 (-)
When the voltage is applied, the state shifts from the d state to the f state. If a voltage is not applied to the node 1, the state becomes the a state.
State. As a result, data is stored in a stable state of a and d even when no voltage is applied to both ends of the capacitor. On the hysteresis loop, states c and d are states of logical value “1”, and states a and f are states of logical value “0”.

[0005] As a method of reading data stored in the capacitor, a method of destroying the d state is used. The prior art uses a sense amplifier that compares a voltage read from a main cell array with a voltage generated by a reference voltage generator. When a ferroelectric reference cell is used, one polarity, 0
A reference voltage is generated on the reference bit line using the two mode states of the polarity. The information of the main cell can be read by the sense amplifier comparing the bit line voltage of the main cell with the reference bit line voltage of the reference cell. The read data must be rewritten in the same cycle to recover the corrupted data. Although the number of the plurality of ferroelectric reference cells is an even number, half is in a unipolar state and half is in a zero polar state.

A conventional ferroelectric memory will be described below with reference to the accompanying drawings. Such an FRAM includes a 1T / 1C FRAM in which a unit cell includes one transistor and one capacitor, and a 2T / 2C FRAM in which a unit cell includes two transistors and two capacitors.
There is a RAM. FIG. 2 is a diagram showing a cell array configuration of a conventional 1T / 1C ferroelectric memory. Conventional 1T / 1C F
The unit cell structure of the RAM is similar to that of a DRAM, and is composed of one transistor and one capacitor.
/ 1C. That is, a plurality of word lines W / L are formed in one direction at regular intervals, and each word line W / L is formed.
A plurality of plate lines (PL) are formed along the line. A plurality of bit lines B1,... At a certain interval in a direction perpendicular to each word line W / L and plate line P / L.
.. B_n is formed. The gate electrodes of the transistors constituting the unit memory cell are commonly connected to the word line W / L. A source electrode of the transistor is connected to an adjacent bit line B / L, a drain electrode of the transistor is connected to a first electrode of a capacitor, and a second electrode of the capacitor is connected to a plate line P / L corresponding to a word line. You.

Next, the driving circuit and operation of such a conventional 1T / 1C ferroelectric memory device will be described.
3 and 4 are configuration diagrams of a driving circuit of a conventional 1T / 1C ferroelectric memory device. FIG. 5 is a timing chart for explaining a writing operation of a conventional 1T / 1C ferroelectric memory cell. FIG. 6 is a timing chart for explaining a read operation of a conventional 1T / 1C ferroelectric memory cell. A drive circuit of a conventional 1T / 1C ferroelectric memory device includes a reference voltage generator 1 for generating a reference voltage, a plurality of transistors Q1 to Q4, a capacitor C1, and the like. Cannot be directly supplied to the sense amplifier.
A reference voltage stabilizing unit 2 for stabilizing the reference voltages of the bit lines B1 and B2, and a plurality of transistors Q6
To Q7, capacitors C2 to C3, and the like. The first reference voltage storage unit 3 stores reference voltages of logic values “1” and “0” in adjacent bit lines, respectively.
, A transistor Q5, a first equalizer 4 for equalizing two adjacent bit lines, and a plurality of transistors Q8, Q9,...
, C6, etc., connected to a word line W / L and a plate line P / L to store data, and a plurality of transistors Q10
To Q15, a P-sense amplifier PSA and the like, a first sense amplifier unit 6 for sensing data of a cell selected by a word line among cells of the main cell array unit 5, a plurality of transistors Q26, Q27,. A second main cell array unit 7 connected to different word lines and plate lines to store data, a plurality of transistors Q28 to Q29, capacitors C9 to C10, and the like.
A second reference voltage storage unit 8 storing reference voltages of logic values “1” and “0” in adjacent bit lines, respectively, and a plurality of transistors Q16 to Q25, N−
A second sense amplifier unit 9 comprising a sense amplifier NSA or the like and sensing and outputting data of the second main cell array unit 7;

The operation of the conventional ferroelectric memory cell having the 1T / 1C structure configured as described above is as follows. First, the write mode and the read mode will be described separately.
In the write mode, as shown in FIG. 5, an external chip enable signal (CSBpad) is enabled from “high” to “low”, and the write mode enable signal (WE
When Bpad) transitions from “high” to “low”, the write mode is started. When the decoding of the address starts, "high" is applied to the word line of the selected cell, and the cell is selected. Then, during the period in which the word line is maintained at “high”, the corresponding plate line P
/ L is sequentially applied with a “high” signal for a certain period and a “low” signal for a certain period. In order to write a logic value “1” or “0” to a selected cell, a “high” or “low” signal is applied to a corresponding bit line in synchronization with a write enable signal. That is, when a "high" signal is applied to a bit line to write a logic value "1", when the signal on the plate line becomes "low" while the word line is "high", the signal is applied to the ferroelectric capacitor. A logic value "1" is written. On the other hand, when a "low" signal is applied to the bit line to write the logic value "0", the logic value "0" is written to the ferroelectric capacitor when the signal on the plate line is "high". Thus, a logic value “1” or “0” is written.

The operation for reading data stored in a cell will be described below. First, as shown in FIG. 6, an external chip enable signal (CSBpad)
Is input and enabled from “high” to “low”,
Before a word line is selected, all bit lines are equipotentially driven low by the equalization signal. That is, in FIG. 3, when a "high" signal is applied to the equalizer 4 and a "high" signal is applied to the transistors Q19 and Q20, the bit line is grounded through the transistors Q19 and Q20, so that the potential of the bit line becomes low. Becomes Then, after turning off the transistors Q5, Q19 and Q20 to inactivate each bit line, the address is decoded. A signal is applied from “low” to “high” to the word line selected by the decoded address, and the word line is selected. Further, the bit line is also selected, and the corresponding cell is selected. Then, when a "high" signal is applied to the plate line of the selected cell, the electric charge corresponding to the logic value "1" stored in the ferroelectric memory is discharged through the bit line, thereby destroying the data. If the logic value "0" is stored in the ferroelectric memory, the corresponding data is not destroyed.

As described above, the destroyed data and the non-destructed data output different values according to the above-described hysteresis loop principle. When data output through the bit line is sensed by the sense amplifier, a logic value “1” or “0” can be sensed.
When the data is destroyed, the data is changed from d to f in the hysteresis loop of FIG. 1, and when the data is not destroyed, the data is changed from a to f. After a certain period of time, when the sense amplifier is enabled, if the data is destroyed, it is amplified and outputs a logic value "1". If the data is not destroyed, it is amplified and outputs the logic value "0". I do. Thus, after the sense amplifier amplifies and outputs the data, it is necessary to restore the original data. At this time, when the plate line is changed from "high" to "low" while "high" is applied to the corresponding word line, the data amplified on the bit line is stored in the capacitor again. That is, data destroyed immediately after reading is recovered.

However, in the conventional ferroelectric memory cell of 1T / 1C, the reference cell is accessed every time reading is performed, and the same operation is performed. Therefore, the reference cell must operate more than the main memory cell. Therefore, the characteristics of the reference cell rapidly deteriorate, and the reference voltage becomes unstable. Also, in a method of generating a reference voltage by a voltage adjusting circuit without using a reference cell, since the reference voltage is affected by the external power supply characteristic, it is uneasy and is affected by external noise characteristics.

Instead of the 1T / 1C FRAM having the above-mentioned problems, various elements (such as the degree of development of an alternative electrode material, the degree of integration, the stability of the ferroelectric thin film, and the operation reliability) are used. One proposed with consideration is a 2T / 2C ferroelectric memory cell. FIG. 7 is a diagram showing a cell array configuration of a conventional 2T / 2C ferroelectric memory, and FIG. 8 is a conventional 2T / 2C ferroelectric memory.
FIG. 9 is a timing chart for explaining a write operation of a C ferroelectric memory cell, and FIG. 9 is a timing chart for explaining a read operation of a conventional 2T / 2C ferroelectric memory cell. In the configuration of the conventional 2T / 2C ferroelectric memory cell, the unit cell configuration includes two transistors and two capacitors. That is, the word line W /
L and a plate line P / L are formed as a pair, and two transistors and two capacitors are formed in those lines formed as a pair of a bit line B_n and a bit bar line BB_n. They are arranged to form a unit memory cell. The gates of the two transistors are both connected to a word line, and the other electrodes of the capacitors connected to those transistors are commonly connected to a plate line P / L. A large number of the unit memory cells are arranged in a matrix as shown.

Next, the driving circuit and operation of such a conventional 2T / 2C ferroelectric memory cell will be described. Conventional 2T / 2C ferroelectric memory cells write and read logic values "1" or "0" differently than 1T / 1C ferroelectric memory cells. Data "1" or "0" is determined according to the storage state of the two capacitors is "1", "0" or "0", and "1". As shown in FIG. 8, in the write mode, the external chip enable signal (CSBpad) transitions from “high” to “low” and is enabled, and the write enable signal (WEBpa) is enabled.
d) is changed from "high" to "low", and "high" and "low" or "low" and "high" signals are applied to the bit line and the bit bar line, respectively, based on the logic value to be written. Is done. When the address is decoded, "high" is applied to the word line of the selected cell, and each transistor is turned on. Then, while the word line is maintained at “high”, the corresponding plate line P / L is sequentially set to “high” for a certain period.
A signal and a "low" signal for a period of time are applied. That is, to write the logic value “1”, a “high” signal is applied to the bit line (B_n) to the bit bar line (BB_n).
In order to write a logic value “0” by applying a “low” signal to n), a “low” signal may be applied to the bit line (B_n) and a “high” signal may be applied to the bit bar line (BB_n). The logic value “1” or “0” is written by such a method.

An operation for reading data stored in a cell will be described below. As shown in FIG. 9, the external CSBpad is enabled from “high” to “low” to enable the read mode. That is,
Write mode enable signal (WEBpad) is low
Is changed to “high”, the write mode ends and the read mode starts. Then, before the word line is selected, all the bit lines are equalized to low (Vss) by the equalization signal. This is 1T /
The operation is the same as that of the 1C ferroelectric memory. After completion of equipotential to low voltage, the address is decoded. Thereafter, the signal applied to the corresponding word line is changed from "low" to "high" according to the decoded address, and the corresponding cell is selected. A "high" signal is applied to the plate line of the selected cell to destroy data on the bit line or bit bar line. That is, when the logic value "1" is recorded, the data of the capacitor connected to the bit line is destroyed, and when the logic value "0" is recorded, the data of the capacitor connected to the bit bar line is destroyed. Is destroyed.

As described above, depending on which data of the bit line and the bit bar line is destroyed, different values are output according to the above-described hysteresis loop principle. Therefore, the sense amplifier senses data output through the bit line and the bit bar line to detect a logic value “1” or “0”. After this, after the sense amplifier amplifies and outputs,
It is the same as in the previous example that the corrupted data must be restored, and the operation is the same. When the voltage on the plate line goes low, the charge Is charged.

[0016]

However, such a conventional ferroelectric memory device and drive circuit have the following problems. Although there is an advantage that data is stored even when the power is turned off, in the conventional FRAM, the cell plate line must be separately configured, so that the layout is complicated and the manufacturing process is complicated. This is disadvantageous in terms of mass production. Since a separate plate line must be used, a control signal must be supplied to the plate line when data is read or written. Therefore, the efficiency of the storage device decreases. With the conventional ferroelectric memory cell, the integration degree cannot be solved unless a new electrode material and barrier material are presented. Capacitors cannot be formed directly on silicon substrates or polysilicon because techniques for forming ferroelectrics directly on silicon surfaces are not yet sufficient. Therefore, the area is larger than that of a DRAM having the same capacity. In particular, in the conventional 1T / 1C, one reference cell is configured to be used for a read operation about several hundred times or more more than the cells of the memory array, so that the reference cells are more than the main memory cells. In operation, the characteristics of the reference cell suddenly deteriorate and the reference voltage becomes unstable.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art FRAM. A memory device and a driving circuit thereof are provided.

[0018]

According to the present invention, there is provided a ferroelectric memory device comprising: a SWL driver for driving a split word line (SWL); a cell array unit for storing data; And a core unit including a bit line control block for controlling a bit line, and a cell array unit includes a suitable number of blocks as one block and a left and right side centered on one SWL driver. The blocks are arranged, and the core unit is arranged between the cell array units in the vertical direction of each cell array unit.

According to another aspect of the present invention, there is provided a driving circuit for a ferroelectric memory device, comprising: an X post decoder for decoding input X and Z addresses and controlling the corresponding cell array block to operate; A global control pulse generator for outputting a control pulse required for writing and reading data based on a CSBpad signal input from the outside, and a control pulse for the global control pulse generator for inputting and writing data. A local control pulse generator for outputting a control signal required for reading, a SWL cell array block for storing data, and an SWL based on the control signals of the X post decoder and the local control pulse generator.
A SWL driver for driving the cell array block; a Y address decoder for decoding and outputting a Y address signal input from the outside; and a column based on a control signal of a local control pulse generator and a decode signal of the Y address decoder. A column control unit for controlling, and a sensing and data input / output control unit for sensing data of the cell array based on a control signal of the local control pulse generation unit and control of the column control unit and writing data to the cell array. Features.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A ferroelectric memory device and a driving circuit according to an embodiment of the present invention will be described below with reference to the accompanying drawings. The ferroelectric memory device according to the present embodiment is as follows. FIG.
0 is a configuration block diagram simply showing the overall configuration of the ferroelectric memory device of the present embodiment. The chip of the present ferroelectric memory device has an S driving large split word line.
A core in which a WL driver, a cell array unit having a number of memory cells for storing data as one block, a sense amplifier for sensing data, and a bit line control unit for controlling bit lines are combined as a block. And a part. Here, the cell array section is SW
The cores are arranged between the cell array units in the vertical direction of each cell array unit.

The cell array section of the embodiment of the present invention thus configured will be described in more detail. FIG. 11 is a configuration diagram of a sub-block array of the SWL ferroelectric memory cell according to the first embodiment of the present invention. The configuration of the SWL ferroelectric memory cell array according to the first embodiment of the present invention includes two word lines accessed by one address, that is, first split word lines (SWL1_n, SWL1_n + 1,
..) And the second split word line (SWL2_
, SWL2_n + 1,...) are arranged at regular intervals, and bit lines (Bit_n, Bit_n + 1,...) are arranged in a direction orthogonal to the pairs.
In this configuration, a memory cell including a transistor and a capacitor is arranged at the intersection of the two. This is arranged in the same configuration as the main memory area for storing data and the reference cell area for obtaining a reference voltage when reading data, and is arranged for one block of the main cell area having many columns. Reference cells arranged in two columns are adjacent as a block. The present ferroelectric memory device has a structure in which a large number of clusters of the main cell region and the reference cell region are arranged.

Split word line SWL paired
One unit cell is composed of two transistors and two capacitors arranged at the intersection of two adjacent bit lines Bit. However, in the example of this figure, data can be stored in this unit cell independently of each transistor and capacitor. That is, the unit cell has a so-called 1T / 1C configuration, and the unit cell merely means that the unit cell is manufactured as one unit for manufacturing. That is, although a detailed description is omitted, a large number of the unit cells are arranged in a matrix during manufacture. The SWL cell array according to the first embodiment of the present invention includes:
In the main cell area, four columns of main cell sub-blocks are arranged, and in the reference cell area, two rows of reference cell sub-blocks are arranged. Of course, it is not limited to that number.

This unit cell corresponds to the first S in the pair of SWLs.
A gate electrode is connected to WL, a source electrode is connected to a first transistor connected to a first bit line of the pair of bit lines, and a gate electrode is connected to a second SWL of the pair of SWLs, and the source electrode is connected to a pair of bit lines. A second transistor connected to a second bit line in the line, a first electrode connected to a drain electrode of the first transistor, a second electrode connected to a first capacitor connected to a second SWL, and a drain of the second transistor. The first electrode is connected to the electrode,
The electrode includes a second capacitor connected to the first SWL.

FIG. 12 is a configuration diagram of a cell sub-block array of the SWL ferroelectric memory according to the second embodiment of the present invention. The configuration of the SWL ferroelectric memory cell array according to the second embodiment of the present invention is the same as that of the SWL cell array according to the first embodiment of the present invention. Consists of columns.
If necessary, the main cell sub-block may be in 2n column units (n
= Natural number of 2 or more), and the reference cell block is 2
It may be configured in column units.

FIG. 13 is a configuration diagram of a SWL ferroelectric memory cell array unit according to a third embodiment of the present invention. In the configuration of the SWL ferroelectric memory cell array according to the third embodiment of the present invention, the bit lines are
1,...) And bit bar lines (BB_n, BB_n)
+1,...), And there is no reference cell area. Bit line 1
The structure of the unit cell is not particularly different from that of the previous example only by the fact that the book becomes a bit bar line. Therefore, the third embodiment is also a unit stored in the unit cell.

The driving circuit of the ferroelectric memory device according to the present invention thus configured is as follows. FIG. 14 is a block diagram of the drive circuit of the ferroelectric memory device according to the present invention. The driving circuit of the ferroelectric memory device according to the present invention has the first configuration.
The configuration is such that all can be used in the cell array configurations of the second and third embodiments.

An X address buffer 11 for buffering an X address signal of X, Y, and Z addresses input from the outside; an X predecoder 12 for previously decoding a signal output from the X address buffer 11; A Z address buffer unit 13 for buffering a Z address among X, Y, and Z addresses input from the outside, a Z predecoder unit 14 for decoding a signal output from the Z address buffer unit 13 in advance, and an X address X output from the buffer unit 11 and the Z address buffer unit 13
An X, Z_ATD generating section 15 for detecting and outputting an address transition point of an address and a Z address signal;
The output signal of the generator 15 and the CSB p input from the outside
input signal, generates a power-up sensing signal at power-up, and outputs X, Z_ATD signal, CSBpa
a global control pulse generator 16 that outputs a basic pulse related to memory control based on the d signal and the power-up sensing signal. A Y address buffer unit 17 for buffering a Y address of X, Y, and Z addresses input from the outside;
And a Y_ATD generation unit 19 for detecting and outputting an address transition point of the Y address signal output from the Y address buffer unit 17. Further, the output signal output from global control pulse generator 16 and Z
A local control pulse generator 20 for synthesizing the Z predecode signal output from the predecoder 14 and the output signal of the Y_ATD 19 to generate a pulse required for each memory block is also provided. This local control pulse generator 2
From 0, a signal for driving it is applied to the SWL driver. The SWL driver receives the X from the X predecoder 12
The predecode signal and the Z predecode signal output from the Z predecoder 14 are combined to give an address from the X post decoder 21 for selecting the corresponding memory cell block. It is designed to work based on it. The local control pulse generator 20 further combines the output signals of the Y predecoder 18 and the local control pulse generator 20 to select a bit line (or a bit bar line).
4 and a signal is also sent to the bit line (or bit bar line) selected by the column control unit 24 to operate. Further, in the present embodiment, the sense amplifier and the input / output control unit for controlling the operation and input / output (I / O) of the sense amplifier by combining the output signal of the local control pulse generation unit 20 and the output signal of the column control unit 24 are described. 25, and an input / output bus control unit 26 for interfacing the external data bus with the sense amplifier and input / output control unit 25.

Here, the global control pulse generator 16
Will be described more specifically. FIG. 15 is a block diagram of a first embodiment of the global control pulse generator 16 of the present invention. The global control pulse generator 16 according to the first embodiment of the present invention includes a CSBpad signal input from the outside,
An input buffer unit 31 that receives a signal including at least a CSBpad signal among the X and Z_ATD signals of the X and Z_ATD generation unit 15 and the power-up detection signal to generate first and second synchronization signals; The first synchronization signal, the feedback signal (the fourth signal of the second controller)
Internal signal), a low voltage detection signal for preventing operation at low voltage, a noise removal signal for filtering noise of the first synchronization signal, and a low output for outputting a preactive pulse for precharging a bit line or the like. A voltage operation and noise prevention unit 32; Further, first to fourth controllers 33 to 36 that output various control signals are prepared. The first controller 33 receives a noise-free signal when a normal power supply voltage is supplied from the low-voltage operation and noise prevention unit 32, and is used to generate a signal for adjusting the enable time of the sense amplifier. A first internal signal and a second internal signal used to generate a signal for adjusting a column selection enable time point and adjusting a pull-up of a bit line of a reference cell;
It outputs an input signal of the SWL driver and a third internal signal used to generate a signal for generating another control signal. The second controller receives the third internal signal of the first controller 33 and generates a SWL1 driving signal SWL1 for generating a SWL1 driving signal.
1 and a signal S2 for generating a drive signal for SWL2, and a local control pulse as a pulse signal P2 as an interlock signal for improving the drive capability by compensating the normal operation of the signals (S1, S2) so as not to be disturbed. In addition to outputting to the generator 20, a fourth internal signal, which is a basic pulse signal for adjusting the activation period of the signals (S 1, S 2), is output to the third controller 35, and the low-voltage operation and noise prevention unit 32 Output as a feedback signal.
The third controller 35 is configured to control the first,
When the second synchronizing signal and the fourth internal signal of the second controller 34 are input and the CSBpad signal is disabled, the fifth internal signal for disabling all signals except the signal S1 and the signal S2 for the SWL2 is disabled. Signal and signal S1
And when the signal S2 is enabled and CSBpa
When the signal d is disabled, the disable is interrupted and a sixth internal signal is output to extend the enable state until the basic waveform generation signal S1 of SWL1 and the basic waveform generation signal S2 of SWL2 complete the normal operation. . The fourth controller 36 is the fifth controller and the sixth controller 36 of the third controller 35.
The internal signal, the first, second, and third internal signals of the first controller 33, the low-voltage operation, and the preactive pulse of the noise prevention unit 32 are input, and the enable signal SAN of the nMOS element of the sense amplifier and the enable of the pMOS element are input. A signal SAP, a first control signal C1 for connecting the bit line of the main cell block to the first input / output node of the sense amplifier, a connection between the bit line of the reference cell block and the second input / output node of the sense amplifier. Second
A control signal C2, a third control signal C3 for adjusting the low voltage precharge of the bit line of the main cell, the bit line of the reference cell, and the node of the sense amplifier, and the pull-up of the column selection enable time and the bit line of the reference cell And outputs a fourth control signal C4 for adjusting.

The first embodiment of the global control pulse generator 16 is provided with a low voltage operation and noise prevention unit 32. However, an external input signal (CSBpad signal, X,
This is not necessary if the Z_ATD signal and the power-up detection signal) are input stably. FIG. 16 shows a second embodiment of the global control pulse generator 16 omitting it.
This will be described based on FIG.

That is, the global control pulse generator 1
In the second embodiment, the low-voltage operation and the noise prevention unit 32 are basically removed from the first embodiment. Accordingly, a feedback signal becomes unnecessary, and there is no preactive pulse. In addition, a first synchronization signal is supplied from the input buffer 31 to the fourth controller. Others are not particularly similar to the first embodiment.

Although not shown, the low-voltage operation and noise generation section of the global control pulse generation section 16 in the first embodiment is a low-voltage operation prevention section or a noise elimination section that does not operate at a low voltage. The noise removal unit having only the function may be configured.

Hereinafter, each unit of the global control pulse generator 16 of the present invention configured as described above will be described in more detail. FIG. 17 is a circuit configuration diagram of the input buffer unit 31 of the global control pulse generation unit 16 according to the first embodiment.
8 is a circuit configuration diagram of the input buffer unit 31 of the second embodiment, FIG. 19 is a circuit configuration diagram of the input buffer unit 31 of the third embodiment, and FIG. 20 is a circuit diagram of the input buffer unit 31 of the fourth embodiment. It is a circuit block diagram. As shown in FIG. 17, the configuration of the input buffer unit according to the first embodiment uses only the CSBpad signal input from the outside, and three inverters 41, 42, and 43 are connected in series.
The CSBpad signal is inverted, the output of the inverter 43 is output as a first synchronization signal, and the output of the inverter 42 is output as a second synchronization signal.

The configuration of the second embodiment of the input buffer unit is as follows.
As shown in FIG. 18, CSBpad input from outside
And a power-up detection signal. That is, a "high" signal is output until the power supply is stabilized in order to operate the circuit operation in a stable state, and when the power supply is stabilized, the power-up detection unit 4 transitions to a "low" signal.
A NOR gate 45 that performs a logical OR operation on the CSBpad signal input from the outside and a signal output from the power-up detection unit 44 to invert and output the result;
5 includes an inverter 46 that inverts the output of the inverter 5 and outputs a second synchronization signal, and an inverter 47 that inverts the output of the inverter 46 and outputs the same as a first synchronization signal. The second synchronization signal extracts the input signal of the inverter 47.

The configuration of the third embodiment of the input buffer unit is as follows.
As shown in FIG. 19, CSBpad input from outside
Signals and X, Z_ATD signals output from the X, Z_ATD generation unit 15 in FIG. 14 are used. The configuration is the same as that of FIG. 18 except that the X, Z_ATD signal is input to one input terminal of the NOR gate 45.

The configuration of the fourth embodiment of the input buffer unit is as follows.
As shown in FIG. 20, CSBpad input from outside
Signals, X and Z_ATD signals output from the X and Z_ATD generation unit 15 in FIG. 14, and a power-up detection signal are used. Its configuration is the same as that of FIG.
X, Z using a 3-input NOR gate as the R gate 45
_ATD signal, CSBpad signal, and power-up detection signal are calculated and output.

Here, an example of a detailed circuit of the power-up detecting section will be described with reference to FIG. The power-up detector is
As shown in FIG. 21, the PMOS transistors 211 to 211
14, a power supply voltage rise sensor 233 for detecting and outputting a rise in the power supply voltage, comprising NMOS transistors 215 to 218, and PMOS transistors 219 to 220;
An amplifying unit 234 comprising NMOS transistors 221 to 224 and the like, comparing and amplifying an output signal of the power supply voltage rise detecting unit with the power supply voltage, and outputting the amplified signal;
25, 229, an NMOS transistor 230, inverters 226 to 228, and the like.
A power-up output unit 236 configured with inverters 231 and 232 and the like, and having an improved drive capability and outputting the output of the feedback unit 235 so that the output of the feedback unit 235 can be used by the global control pulse generation unit 16 is provided.

The low voltage operation and noise prevention unit 32 of the present invention
Will be described with reference to the drawings. FIG. 22 is a circuit configuration diagram of the first embodiment of the low voltage operation and noise prevention unit 32,
FIG. 23 is a circuit configuration diagram of the second embodiment. The low-voltage operation and noise prevention unit according to the present invention is roughly divided into three functions.
When the low voltage is detected, the control pulse is inactive at a low voltage, that is, the control pulse is disabled to protect the memory cell data. A third control signal (C) for performing a delay operation to adjust the low voltage precharge of the sense amplifier.
Adjust the pulse width of 3). The noise of the signal (CSBpad signal) input from outside is removed. As shown in FIG. 22, the first embodiment of the low voltage operation and noise prevention unit includes a low voltage detection and delay unit 68 for delaying the pulse width of the low voltage detection and third control signal (C3), and a noise. And a noise removing unit 69 for removing the noise.

The low voltage sensing and delaying unit 68 includes inverters 79 and 80, and the first of the input buffer unit 31.
A first delay unit 61 for delaying the synchronization signal by a predetermined time;
It is composed of inverters 76 and 78 for reducing the current driving capability of the MOS and inverters 75 and 77 for increasing the driving capability of the PMOS and the NMOS, and the “high” pulse width of the first synchronization signal of the input buffer unit 31 A second delay unit 62 for delaying the rising edge of the first synchronization signal so as to reduce the delay, inverters 63 and 64 for respectively inverting the outputs of the first and second delay units 61 and 62, and a gate electrode and a source electrode An NMOS transistor 65 commonly connected to the power supply terminal (Vcc), a drain electrode connected to the output terminal of the inverter 63, a gate electrode connected to the output terminal of the inverter 63, a source electrode connected to the inverter 64, and a drain electrode N that outputs a signal to
The MOS transistor 67 has a gate electrode grounded, a source electrode and a drain electrode connected to a power supply terminal and an NMO
PMO connected to the drain electrode of S transistor 67
And an S transistor 66.

The noise removing section 69 includes an inverter 70 for inverting the fourth internal signal fed back from the second controller 34 and a low voltage detecting and delaying section 6.
A NAND gate 71 for performing a logical product operation on the output of the inverter 8 and the output of the inverter 70 and inverting the output, and a NAND gate 7
Inverter 72 for inverting the output of No. 1 and a NAND gate for performing an AND operation on the first synchronizing signal of the input buffer unit 31 and the output of the inverter 72 to invert and output a preactive pulse for adjusting the precharge of the sense amplifier 74, and an inverter 73 that inverts the output of the inverter 72 and outputs a low voltage detection and noise removal signal.

On the other hand, the low voltage operation and the second
As shown in FIG. 23, the embodiment is the same as the first embodiment shown in FIG.
Inverter 6 of the low voltage sensing and delay unit 68 in FIG.
Between the NMOS transistor 67 and the NMOS transistor 67
9 is provided. That is, the noise removing unit 69
Is an NMOS transistor 85 connected between the inverter 64 and the NMOS transistor 67, an inverter 86 that inverts a feedback signal (fourth internal signal) of the second controller 34 and outputs the inverted signal to the NMOS transistor 85, NMOS based
And an NMOS transistor 87 for grounding the output of the transistor 67. And an inverter 81 for inverting the output of the NMOS transistor 67, an inverter 82 for inverting the output of the inverter 81,
NAND gate 84 for performing an AND operation on the output of the inverter 82 and the first synchronizing signal of the input buffer unit 31 and inverting the result to output as a preactive pulse; May be additionally configured to constitute a low-voltage operation and a noise removing unit. Further, in the low voltage operation and noise prevention unit 32 shown in FIGS. 22 and 23, the low voltage sensing and delay unit 68 may be omitted, and conversely, the noise removal unit 69 may be omitted. You may. That is, FIG. 24 shows a case where only the noise removing unit 69 is provided except for the low voltage sensing and delay unit in FIG. FIG. 25 shows a case where only the low voltage sensing and delay unit 68 is provided except for the noise removing unit in FIG.

The global control pulse generator 16 of the present invention
The configuration of the first controller 33 is as shown in FIG. The first controller 33 includes inverters 91 to 1
A third delay unit 104 configured to delay the low-voltage detection and noise removal signal of the low-voltage operation and noise prevention unit 32 or the first synchronization signal of the input buffer 31 for a predetermined time and output a first internal signal; An inverter 101 for inverting a signal output from the third delay unit 104, a low voltage detection and noise removal signal of the low voltage operation and noise prevention unit 32, or a first synchronization signal of the input buffer unit 31 and an output signal of the inverter 101. Is ANDed and inverted to produce the second
A NAND gate 102 for outputting an internal signal;
An inverter 103 that inverts the output of the gate 102 and outputs a third internal signal. The first to third internal signals are respectively extracted from the illustrated positions.

The configuration of the second controller of the present invention is as follows. FIG. 27 is a circuit configuration diagram of an embodiment of the second controller of the present invention. The second controller reduces the current driving capability of the PMOS of the sense
And a plurality of inverters 111, 113, 115, 117, 119 for increasing the current driving capability of the
And inverters 112, 114, 116, 118 and 120 for increasing the current driving capability of the NMOS, and a fourth delay for delaying a falling edge of the third internal signal output from the first controller 33 for a predetermined time. A NOR gate 121 that performs a logical sum operation on the output of the fourth delay unit 148 and the third internal signal and outputs the inverted result;
Reduce the current drive capability of the PMOS of the sense
A plurality of inverters 123, 125, 127, 129, 131 and P for increasing the current driving capability of the MOS
Inverters 122, 124, 126, 128, 130 for increasing the current driving capability of MOS and NMOS
A fifth delay unit 149 for delaying the rising edge of the output signal of the NOR gate 121 by a predetermined time;
An inverter 132 for inverting an internal signal; a NAND gate 133 for ANDing an output of the inverter 132, an output of the NOR gate 121, and an output of the fifth delay unit 149 to invert and output a fourth internal signal;
And the output of the fourth delay unit 148 and the NAND gate 13
3 and a NAND gate 134 for ANDing and inverting the output of the third and third outputs, and inverters 135 to 138.
A sixth delay unit 150 for delaying the rising edge of the output of the NAND gate 133 by a predetermined time; an output of the inverter 113; an output of the NAND gate 134;
A NAND gate 141 for performing a logical product operation on the output of the NAND gate 141 and inverting the output, and inverters 142 and 143; a seventh delay unit 151 for delaying the rising edge of the output of the NAND gate 141 for a predetermined time;
9 and an inverter 140, and a fifth delay unit 1
The output of the NAND gate 133 includes an S1 signal output unit 237 for performing an AND operation on the output of the NAND gate 133 and the output of the NAND gate 133 to output the signal (S1) for the SWL1, and a NAND gate 144 and an inverter 145. And an output of the seventh delay unit 151, and an S2 signal output unit 238 that outputs a signal (S2) for SWL2 by performing a logical operation, and inverters 146 and 147. The driving capability of the signal of the NAND gate 133 is increased. And a pulse signal output section 152 for outputting an interlock signal (P2). The output signal of the NAND gate 133 becomes the fourth internal signal as it is.

An embodiment of the third controller of the present invention will be described with reference to FIGS. FIG. 28 is a circuit configuration diagram of the first embodiment of the third controller, FIG. 29 is a circuit configuration diagram of the second embodiment, and FIG. 30 is a circuit configuration diagram of the third embodiment. The first embodiment of the third controller includes an inverter 161, NAND gates 162, 163, 16 as shown in FIG.
4 and the like. The first synchronization signal of the input buffer unit 31 and the fourth internal signal of the second controller 34 are input, and the high pulse of the interlock signal (P2) output from the second controller 34 is converted to the CSBpad signal. Is "low"
Signal extension unit 17 that extends until it is enabled
An eighth delay unit 173 which is composed of inverters 165 to 168 and delays the rising edge of the output signal of the signal expansion unit 172 by a predetermined time; an inverted signal of the fourth internal signal and a second synchronization signal of the input buffer 31 A NAND gate 171 that performs a logical product operation on the logical product and inverts the result to output a sixth internal signal;
It comprises a NAND gate 169 and an inverter 170, and comprises an internal signal output section 174 that performs a logical product operation of the output of the eighth delay section 173 and the output of the NAND gate 171 to output a fifth internal signal.

FIG. 2 shows a second embodiment of the third controller.
As shown in FIG. 9, the signal expansion unit 172 is omitted from FIG. That is, the fourth internal signal is directly input to the eighth delay unit 173. The third embodiment of the third controller is as shown in FIG. In FIG. 28, the rising edge of the output signal of the signal extension unit 171 is delayed by the eighth delay unit 173. However, in FIG. Delay).

FIG. 31 is a configuration circuit diagram of an embodiment of the fourth controller using the global control pulse generator of FIG. 15, and FIG. 32 is a configuration circuit diagram of an embodiment of the fourth controller using the global control pulse generator of FIG. It is.
First, the fourth controller shown in FIG. 31 includes inverters 181, 183, 184, and 18 as shown in FIG.
5, a logical operation of the first internal signal of the first controller 33 and the fifth internal signal of the third controller 35. The enable signal (SAN) of the NMOS element of the sense amplifier and the NAND of the sense amplifier. PM
A sense amplifier control signal output unit 199 for outputting an enable signal (SAP) for the OS element;
6. It is composed of inverters 187 to 191 and the like.
Third internal signal of controller 33 and third controller 3
5, a first control signal (C1) for performing a logical operation on the fifth internal signal to connect the bit line of the main cell block to the first input / output node of the sense amplifier, the bit line of the reference cell block and the sense amplifier The first controller 33 includes a bit line switching signal output unit 200 for outputting a second control signal (C2) for connecting to a second input / output node, a NAND gate 192, inverters 193, 194, and 195. A column control signal output unit 201 that performs a logical operation on the second internal signal of the third controller 35 and the fifth internal signal of the third controller 35 to output a fourth control signal (C4) serving as a column control signal, a NAND gate 196, and an inverter 197. 198 and the like, and the pre-active pulse of the low-voltage operation and noise prevention unit 32 and the sixth Composed of precharge control signal output unit 202 for outputting a third control signal for precharging a signal with logic operation (C3).

The structure of the fourth controller shown in FIG. 32 is similar to that shown in FIG.
84, 185, a NAND gate 182, etc.
A logical operation of the first internal signal of the first controller 33 and the fifth internal signal of the third controller 35 are performed to output an enable signal (SAN) of the NMOS element of the sense amplifier and an enable signal (SAP) of the PMOS element of the sense amplifier. And a NAND gate 186, inverters 187 to 191 and the like, and performs a logical operation on the third internal signal of the first controller 33 and the fifth internal signal of the third controller 35 to perform the main cell operation. A first control signal (C1) for connecting the bit line of the block to the first input / output node of the sense amplifier; a second control signal (C1) for connecting the bit line of the reference cell block to the second input / output node of the sense amplifier; A bit line switching signal output unit 200 for outputting a control signal (C2);
AND gate 192, inverters 193, 194, 1
And a fourth control signal (C4) for performing a logical operation on the second internal signal of the first controller 33 and the fifth internal signal of the third controller 35 to output a column control signal. Output unit 201 and inverter 19
7, 198, 203, etc., and the input buffer unit 3
Logical operation of the first first synchronization signal or the sixth internal signal of the third controller 35 to perform a precharge third control signal (C3)
And a precharge control signal output unit 202 for outputting the same.

Next, the SW of the present invention configured as described above will be described.
A driving method of the L ferroelectric memory device will be described. FIG. 33 is an output waveform diagram of each section of the power-up detection section of the present invention. The circuit is shown in FIG. First, it is assumed that the chip enable signal (CSBpad) is fixed to the ground voltage, and that the chip enable signal is in the chip enable state during the entire period at power-up. First, before t1, the power is not yet applied, and the signals of the nodes (N1 to N6) are in the ground state. [Period of t1 to t2] During the period of t1 to t2, the power supply is Vcc.
Powered up to state. The signal at node N1 is PMO
Although the voltage rises due to the pull-up of the S transistor 219, the gradient is gentle. The signal at node N2 is delayed and rises gradually. The voltage of the node N1 rises and the transistor 22
3 turns on, the transistor N5 turns on via the transistor 229 operating as a capacitor, and thus the node N4 is connected to the transistors 222, 223, and 22.
4, via the ground. The signal at node N5 is NMOS
Since the transistor 230 is off, the transistor 230 is in a floating state, and the signal at the node N6 rises due to the effect of the signal at the node N4.

[Period from t2 to t3] When the signal voltage at the node N2 rises to the threshold voltage Vtn or more and the NMOS transistor 221 is turned on, the amplifying section operates and the signal at the node N1 gradually falls, and the node N4 Does not rise to a voltage at which the output of the inverter 226 is inverted, and the signals at the nodes (N5, N6) maintain Vcc. [Period of t3 or more] When the signal at the node N4 continues to rise and rises above the threshold value Vt of the inverter 226, the signal at the nodes (N5, N6) is inverted from high to low, and NM
The OS transistor 224 is turned off, and the amplifier 234 is disabled. The node N4 rises to Vcc by the current of the PMOS transistor 225, and the power-up signal goes low. As a result, the CSBpad signal is fixed at low, but the power-up signal, which is one of the input signals, changes from high in the disabled state to low in the enabled state in the input buffer unit 31.

The operation output waveform of the global control pulse generator of the present invention using the above power-up detector will be described. FIGS. 34 and 35 show the cell arrays shown in FIGS.
FIG. 36 and FIG. 37 are operation timing diagrams of the global control pulse generator when the cell array has the configuration of FIG. 13. 34 and 36 are timing charts when the Y address changes, and FIGS. 35 and 37 are timing charts when the X and Z addresses change. The operation of the global control pulse generator of the present invention is based on the configuration of the cell array, X,
The operation is slightly different depending on the change in the Z address and the change in the Y address as shown in the figure. That is, the cell array configuration is
1 or FIG. 12, and the operation of the first embodiment of the global control pulse generator when the Y address changes is as shown in FIG. The chip enable signal (CSBpad) is applied from outside via a chip enable pin. Since the chip enable signal enables the low state, the chip enable signal is enabled when the CSBpad signal transitions from high to low. In order to perform a new read or write operation, an inactive period to a high state is required.

First, FIG. 34 is divided into periods t1 to t15, and the change state of the signal for each period will be described. CSBpad
Assume that the signal is activated low from the start of the period t1 to the end of the period t14 and is deactivated to the high state from the start of the period t15. While the CSB signal is activated, the X and Z addresses do not change, but the Y and Y addresses do not change.
It is assumed that the address changes at the start of the period t7 and at the start of t11. The Y_ATD signal senses a change in the Y address, and during a period between t7 and t8, and between t11 and t1.
A high pulse is generated between two periods. Here, S1, S
2 is a SWL cell word line (SWL1, SWL
This pulse is used to generate a drive signal for driving 2). Since there is no direct relationship with the present invention, the operation up to driving the word line using these signals S1 and S2 is omitted.

First, in the period t1, the CSBpad signal is enabled from high to low. At this time, X, Y, Z
The address maintains the previous state at t1. When the Y address transitions at the start of t7, the Y_ATD signal goes high from t7 to t8. When the Y address transitions at the start of t11, the Y_ATD signal becomes
From 11 to t12, it is in a high state.

The S1 signal is maintained in a low state until a period t1, maintained in a high state in a period from t2 to t3, in a low state in a period t4, in a high state in a period t5, and in a period from t6 to t15.
It will be in a low state until. At this time, the S2 signal is maintained in the high state during the period from t3 to t4, and otherwise becomes low. Then, the first control signal C1, which is a signal for adjusting the signal flow between the main cell bit line and one of the input / output terminals of the sense amplifier, is in a low state only in the period t3, and is in a high state in other periods. Therefore, the signal flow between the main cell bit line and one of the input / output terminals of the sense amplifier is interrupted only in the period t3. Then, the second control C2, which is a signal for adjusting the signal flow between the reference cell bit line and the other input / output terminal of the sense amplifier, generates a pulse that goes low during the period from t3 to t14. Therefore, the signal flow between the main cell bit line and the other input / output terminal of the sense amplifier is interrupted during the period from t3 to t14.

The fourth control signal C4 is a signal for adjusting the signal transmission between the bit line of the main cell and the external data bus and adjusting the pull-up of the reference cell bit line.
Goes high from t4 to t14, and CSBpad
The point at which the signal is disabled (end point of period t14)
Is changed to the low state again. Therefore, the period from t4 to t1
The signal transmission between the main cell bit line and the external data bus can be adjusted only in four periods, and the pull-up of the reference cell bit line can be adjusted.

The interlock signal P2, which is a signal for preventing interference by other pulses while S1 and S2 generate a normal pulse, is in a high state from the period t2 when the S1 and S2 signals are in a high state to the period t5. At the start of t6, the state becomes low again. The third control signal C3, which precharges the main cell and the reference cell bit line to a low voltage before the activation of S1 and S2, is maintained at the previous high state until the period t1, and the t2 period starts. At this point, the state is changed to the low state, the low state is maintained until the time t14, the precharge becomes inactive, and the region other than this period (the time when the CSBpad signal is disabled)
Is changed to the high state again.

Then, the SAN signal (in order to operate the sense amplifier of the sense amplifier / input / output control unit 25, NM
A spare signal for generating a SANC signal which is a signal for controlling a transistor constituted by the OS) is maintained at the low state of the previous state until the period t2, transitions to the high state at the start of t3, and the CSBpad signal Is transitioned to the low state at the time when is disabled. The SAP signal (a spare signal of the SAPC signal, which is a signal for controlling a transistor formed of a PMOS for operating the sense amplifier of the sense amplifier / input / output control unit 25) changes in reverse to the SAN signal. That is, the high state of the previous state is maintained until the period t2, the state changes to the low state at the start of t3, and the state changes to the high state when the CSBpad signal is disabled.

As described above, when the Y address is changed and Y_ATD is generated while the CSBpad signal is activated, in the write mode, both split word lines are set to “high” by the S1 and S2 signals. , "0" is written in a cell in which "low" is added to the bit line in the period during which the bit line is driven during the period from t2 to t3. Then, "high" is generated by the S1 and S2 signals.
"High" is added to the split word line to which the gate of the transistor whose one electrode is connected to the bit line on which it is mounted, and "Low" to the split word line to which the other capacitor is connected. "1" is written when

On the other hand, the cell array configuration is the same as that shown in FIG.
The operation of the global control pulse generator when the X and Z addresses change is as shown in FIG. The entire timing period will be described separately for the period from t1 to t21. It is assumed that the X and Z addresses change at the start points of the t7 and t14 periods, respectively. That is, X,
The operation of the global control pulse generator when the Z address changes is similar to the operation when the Y address changes. Therefore, only the parts that perform different operations will be described below. FIG.
Then, the Y_ATD signal goes high at the time when the Y address changes, while the X and Z addresses stay in the t7 period,
Assuming that it changes at the beginning of the t14 period, X, Z
The _ATD signal is in the high state in the periods t7 and t14, and is in the low state in other periods. In the global control pulse generator, when the X and Z addresses change, X and Z_
The ATD signal and the CSBpad signal are combined and used.
Therefore, the high state period of the X, Z_ATD signal (t7,
When t14) exists, the global control pulse generator recognizes that the CSBpad signal has been enabled during that period. Accordingly, all the output signals are generated again from the global control pulse generator, and the corresponding X and Z addresses are normally accessed.

The S1 and S2 signals transition to high after a certain period t1 after the CSBpad signal is enabled to "low" state, and the X, Z_ATD signals are "low".
To a high level after a certain period (t8, t15). That is, S1 is a period from t2 to t3,
t5 period, t9 to t10 period, t12 period, t16 to t
The high state is maintained in the 17 period and the t19 period, and the “low” state is maintained in other periods. Then, the S2 signal is generated during a period from t2 to t4, a period from t9 to t11, and a period from t16 to t4.
The “high” state is maintained in the period t18, and the “low” state is maintained in other periods.

The first control signal C1 is generated during a period (t2 to t3, t9 to t10, t9) when both the S1 and S2 signals are in the high state.
16 to t17) (t3, t10, t1)
Transition to low during 7). Then, the second control signal C
2 changes from a high state to a low state when the C1 signal changes to a low level, and changes from a low state to a high state when the X and Z_ATD signals change to a high level. The fourth control signal C4 changes from high to low when the signal C2 changes to high, and changes from the high state to the low state when the X and Z_ATD signals change to high. The P2 signal transitions from low to high when the S1 and S2 signals simultaneously transition to high, and transitions from high to low when both the S1 and S2 signals transition to low. The third control signal C3 changes from high to low when the S1 and S2 signals simultaneously change to high, and changes from low to high when the X and Z_ATD signals change to high. SA
The N signal and the SAP signal transition to the opposite states when the C2 signal changes.

Therefore, the period in which both the S1 and S2 signals are in the "high" state, that is, t2 to t3, t9 to t10, t1
Logic “0” is written to the cell in a period such as 6 to t17. Then, a period in which only one of the S1 and S2 signals is in the “high” state, that is, t4 to t5, t11
Logic "1" is written to the cells during the period from t12 to t18 to t19.

On the other hand, the configuration of the cell array of the present invention is shown in FIG.
FIG. 36 shows the operation of the global control pulse generator when the Y address changes. That is, FIG.
Is divided into periods t1 to t21, and the change state of the signal for each period will be described. FIG. 13 includes a bit line and a bit bar line, and does not include a reference cell. Therefore, the first and second control signals C1 and C2 are not required. C
The SBpad signal is activated low from the start of the period t1 to the end of the period t14, and is deactivated to the high state at the start of the period t15. It is assumed that while the CSB signal is activated, the X and Z addresses do not change, but the Y address transitions at the start of the period t7 and at the start of t11, respectively. Then, the Y_ATD signal senses a change in the Y address, and during a period between t7 and t8, and between t11 and t1.
The high state is set for each of the two periods. The S1 and S2 signals are applied to the split word line (SW) of the SWL memory cell.
L1 and SWL2) are signals used to form the basic waveform, so the S1 signal is generated as a high-state pulse during the periods t2 to t3 and t5, and the S2 signal is generated as a high-state pulse during the periods t2 and t4. Is done.

The C4 signal adjusts the signal transmission between the main cell bit line and the external data bus, and adjusts the pull-up of the main cell bit line and bit bar line. To the high state, and again to the low state when the CSBpad signal is disabled (end point of the period t14). Therefore, a signal can be transmitted between the bit line of the main cell and the external data bus only in the period from t4 to t14.

The P2 signal is a signal that maintains a high state during a period from t2 to t5, which is a period when S1 and S2 generate a normal pulse (high state).
1. The interlock function is performed so as not to disturb the normal pulse of the S2 signal. That is, the S1 and S2 signals are signals that maintain a high state during a period (t2 to t5) during which normal signals are generated, and during this period, other signals do not interfere with the normal signals of S1 and S2. Signal.

The third control C3 is for making the precharge inactive during the period from t2 to t4 and activating the precharge during the other periods. It is maintained, and transitions to a low state at the start of the period t2, and transitions to a high state again when the CSBpad signal is disabled.

The SAN signal is output to the NMO for operating the sense amplifier and the sense amplifier of the input / output control unit.
S which is a signal for controlling a transistor composed of S
A preliminary signal for generating the AN_C signal, which is maintained in a low state until time t2, transitions to a high state at the start of t3, and transitions to a low state when the CSBpad signal is disabled. The SAP signal is a spare signal of the SAP_C signal, which is a signal for controlling a transistor formed of a PMOS for operating the sense amplifier and the sense amplifier of the input / output control unit, and changes in reverse to the SAN signal. That is, the high state is maintained until the period t2, and the state is changed to the low state at the start of the time t3.
When the pad signal is disabled, it transitions to the high state.

Therefore, logic "0" is written to the cell during a period when both the S1 and S2 signals are in the "high" state, that is, during the period from t2 to t3. Then, a period in which only one of the S1 and S2 signals is in the “high” state, that is, t4
Logic “1” is written to the cell in a period from t5.

On the other hand, the structure of the cell array is shown in FIG.
FIG. 37 shows the operation of the global control pulse generator when the Z address is changed. That is, the operation of the global control pulse generator when the X and Z addresses are toggled is similar to the operation when the Y address is toggled. Therefore, only the parts that perform different operations will be described below. In FIG. 36, the Y_ATD signal goes high when the Y address changes, whereas in FIG. 37, the X, Z_ATD signal goes high when the X and Z addresses change. When the X and Z addresses change, the global control generator combines and uses the X and Z_ATD signals and the CSB signal. Therefore, if there is a high-state period (t7, t14) of the X, Z_ATD signal, the global control pulse generator recognizes that the CSBpad signal has become high during that period. Therefore, all output signals are generated again from the global control pulse generator, and the corresponding X and Z addresses are normally accessed.

That is, the S1 and S2 signals are CSBpa
The signal d transitions to high after a certain period (t1) from being enabled to the "low" state, and a certain period (t8, t) when the X, Z_ATD signal transitions to "low".
15) Later transitions high. The C4 signal transitions from high to low when the S1 signal transitions to low and the S2 signal is high, and transitions from high to low when the X, Z_ATD signals transition to high. The P2 signal transitions from low to high when the S1 and S2 signals simultaneously transition to high, and transitions from high to low when both the S1 and S2 signals transition to low. The C3 signal is
When the S1 and S2 signals simultaneously transition to high, the signal transitions from high to low, and when the X and Z_ATD signals transition to high, the signal transitions from low to high. SAN signal, S
The AP signal is changed after being delayed by a predetermined time when the S1 and S2 signals are all “high”, and changes to the opposite state when the X and Z_ATD signals are changed to “high”.

Therefore, the period in which both the S1 and S2 signals are in the "high" state, that is, t2 to t3, t9 to t10, t1
Logic “0” is written to the corresponding cell in a period such as 6 to t17. Then, a period in which only one of the S1 and S2 signals is in the “high” state, that is, t4 to t5, t4
Logic “1” is written to the corresponding cell during the period from 11 to t12, t18 to t19, and the like.

[0070]

As described above, the SWL ferroelectric memory device of the present invention and its driving circuit have the following effects. Since the plate line does not need to be formed separately from the word line formed as the gate of the transistor, the ferroelectric memory device is configured to perform the cell plate function by using the split word line. it can. Further, since another signal for controlling another plate line is not required in data reading and writing operations, the efficiency as a storage device is improved. Conventionally, one reference cell is configured to be used for reading operations of many main memories of about several hundred times or more. However, in the present invention, the reference cells are distributed to a certain number of main memories. Thus, the deterioration of the characteristics of the reference cells in which the reference cells are arranged can be suppressed. Further, although only the CSBpad signal is usually used as a signal for enabling the ferroelectric memory, the present invention uses the X, Y, and Z_ATD signals together with the CSB signal.
Thereby, the memory operation can be efficiently operated, for example, by operating in the column leading access mode to improve the chip access speed and performance. That is, the operation of the address is classified into a case in which only the X and Z addresses change greatly and a case in which only the Y address changes. Also try not to disturb the operation. Further, when the X and Z addresses change, since there is no valid data latched in the sense amplifier, the same operation as when the CSB signal is enabled can be implemented using the X and Z_ATD signals. When only the Y address changes, the split word line corresponding to the row address does not change.
Data already latched in the sense amplifier can be read, and in the write mode, a normal write operation can be performed using the Y_ATD signal.

[Brief description of the drawings]

FIG. 1A is a characteristic diagram showing a hysteresis loop of a general ferroelectric, and FIG. 1B is a configuration diagram of a unit capacitor of a general ferroelectric memory.

FIG. 2 is a diagram showing a cell array configuration of a conventional 1T / 1C ferroelectric memory.

FIG. 3 is a drive circuit configuration diagram of a conventional 1T / 1C ferroelectric memory cell.

FIG. 4 is a drive circuit configuration diagram of a conventional 1T / 1C ferroelectric memory cell.

FIG. 5 is a timing chart for explaining a write operation of a conventional 1T / 1C ferroelectric memory cell;

FIG. 6 is a timing chart for explaining a reading operation of a conventional 1T / 1C ferroelectric memory cell.

FIG. 7 is a configuration diagram of a cell array of a conventional 2T / 2C ferroelectric memory.

FIG. 8 is a timing chart for explaining a write operation of a conventional 2T / 2C ferroelectric memory cell;

FIG. 9 is a timing chart for explaining a read operation of a conventional 2T / 2C ferroelectric memory cell.

FIG. 10 is a block diagram showing a cell array configuration of the SWL ferroelectric memory according to the embodiment of the present invention.

FIG. 11 is a configuration diagram of a cell array circuit of the SWL ferroelectric memory according to the first embodiment of the present invention.

FIG. 12 is a configuration diagram of a cell array circuit of an SWL ferroelectric memory according to a second embodiment of the present invention.

FIG. 13 is a diagram showing a cell array circuit configuration of a SWL ferroelectric memory according to a third embodiment of the present invention.

FIG. 14 is a block diagram showing an embodiment of a drive circuit of the SWL ferroelectric memory device according to the present invention.

FIG. 15 is a block diagram of a first embodiment of a global control pulse generator according to the present invention.

FIG. 16 is a block diagram of a global control pulse generator according to a second embodiment of the present invention.

FIG. 17 is a circuit configuration diagram of a first embodiment of the input buffer unit of the present invention.

FIG. 18 is a circuit configuration diagram of a second embodiment of the input buffer unit of the present invention.

FIG. 19 is a circuit configuration diagram of an input buffer unit according to a third embodiment of the present invention.

FIG. 20 is a circuit configuration diagram of a fourth embodiment of the input buffer unit of the present invention.

FIG. 21 is a circuit configuration diagram of a first embodiment of a power-up detection unit of the present invention.

FIG. 22 is a circuit configuration diagram of a first embodiment of a low-voltage operation and noise prevention unit of the present invention.

FIG. 23 is a circuit configuration diagram of a second embodiment of a low-voltage operation and noise prevention unit according to the present invention.

FIG. 24 is a circuit configuration diagram of a low-voltage operation and noise prevention unit according to a third embodiment of the present invention.

FIG. 25 is a circuit diagram of a low-voltage operation and noise prevention unit according to a fourth embodiment of the present invention.

FIG. 26 is a circuit configuration diagram of a first embodiment of the first controller of the present invention.

FIG. 27 is a circuit configuration diagram of a second embodiment of the second controller of the present invention.

FIG. 28 is a circuit configuration diagram of a first embodiment of the third controller of the present invention.

FIG. 29 is a circuit configuration diagram of a second embodiment of the third controller of the present invention.

FIG. 30 is a circuit diagram of a third controller according to a third embodiment of the present invention.

FIG. 31 is a circuit configuration diagram of a first embodiment of a fourth controller of the present invention.

FIG. 32 is a circuit configuration diagram of a second embodiment of the fourth controller according to the present invention.

FIG. 33 is an operation timing chart of the power-up detection unit of the present invention.

FIG. 34 is an operation timing chart of the global control pulse generator of the present invention.

FIG. 35 is an operation timing chart of the global control pulse generator of the present invention.

FIG. 36 is an operation timing chart of the global control pulse generator of the present invention.

FIG. 37 is an operation timing chart of the global control pulse generator of the present invention.

[Explanation of symbols]

11 X address buffer section 12 X predecoder section 13 Z address buffer section 14 Z predecoder section 15 X, Z_ATD generation section 16 global control pulse generation section 17 Y address buffer section 18 Y predecoder section 19 Y_ATD generation section 20 local control pulse Generation unit 21 Final X decoder unit 22 SWL driver 23 SWL cell array unit 24 Column control unit 25 Sense amplifier and input / output control unit 26 Input / output bus control unit 31 Input buffer unit 32 Low voltage operation and noise prevention unit 33 First controller 34 2 controller 35 3rd controller 36 4th controller 44 Power-up detection unit 68 Low voltage sensing and delay unit 61, 62, 104, 148, 149, 150, 15
1, 173, 179 delay unit 69 noise removal unit 152 P2 pulse signal output unit 172 signal extension unit 174 fifth internal signal output unit 199 sense amplifier control signal output unit 200 bit line control signal output unit 201 column control signal output unit 202 pre Charge control signal output section 233 Power supply voltage rise detection section 234 Amplification section 235 Feedback section 236 Power-up signal output section 237 S1 signal output section 238 S2 signal output section

Claims (26)

[Claims] 1. Two parallelly arranged first split word lines (SWL) accessed by one address.
1) and a second split word line (SWL2), and a bit line in a direction orthogonal to these word lines. The gate of one transistor is connected to the first split word line, and The gate of the other transistor is connected to the split word line, one electrode of each transistor is connected to each bit line, the other electrode is connected to one electrode of the dielectric capacitor, and the other electrode of the dielectric capacitor is connected to In a SWL ferroelectric memory device connected to a split word line to which the capacitor is not connected, an SWL driver for driving each split word line (SWL) and a cell for storing data comprising a transistor and a dielectric capacitor are provided. Cell array section composed of multiple blocks A sense amplifier block including a sense amplifier for sensing data in the cell array unit and writing the data, and a core unit including a bit line control block including a bit line control unit for controlling a bit line. The SWL ferroelectric memory device according to claim 1, wherein the blocks are arranged on the left and right sides with one SWL driver as a center, and the core unit is arranged between the blocks in each cell array unit in the vertical direction. 2. The method according to claim 1, wherein the cell array unit includes a block composed of a main cell for substantially writing data, and a block composed of a reference cell storing a reference value for reading data. S according to claim 1
WL ferroelectric memory device. 3. The main cell block is configured in even column units, the reference cell block is configured in two column units, and a plurality of main cell blocks and reference cell blocks are configured to form one cell array unit. 2. The SWL ferroelectric memory device according to claim 1, wherein: 4. The cell array unit includes a plurality of split word lines (SWLs) arranged in one direction at regular intervals, and a plurality of split word lines (SWLs) arranged at regular intervals in a direction perpendicular to the respective SWLs. 2. A plurality of bit lines, and a ferroelectric unit memory cell formed in each pair of said two adjacent SWLs and two adjacent bit lines. SWL
Ferroelectric memory device. 5. The ferroelectric unit memory cell, wherein a gate electrode is connected to a first SWL of the pair of SWLs, and a source electrode is connected to a first transistor connected to a first bit line of the pair of bit lines. A second transistor connected to a second SWL of the pair of SWLs, a source electrode connected to a second bit line of the pair of bit lines, and a first electrode connected to a drain electrode of the first transistor. A first capacitor connected to the second SWL, a second electrode connected to the second SWL; and a second capacitor connected to the drain electrode of the second transistor, the second electrode connected to the first SWL. The SWL ferroelectric memory device according to claim 4, wherein the memory device is configured. 6. A plurality of bit lines for a main cell for storing data, wherein the plurality of bit lines include:
5. The SWL ferroelectric memory device according to claim 4, further comprising two columns of bit lines for a reference cell for generating a reference voltage required for data sensing. 7. The configuration of the cell array includes: a plurality of split word lines arranged in one direction at a constant interval; and a plurality of split word lines alternately arranged at a constant interval in a direction perpendicular to each of the split word lines. A bit line, a bit bar line, and two adjacent paired split word lines, and a unit cell formed at an intersection of the pair of bit lines and the bit bar line. Item 2. The SWL ferroelectric memory device according to item 1. 8. The unit cell includes: a first transistor having a gate electrode connected to a first split word line of the pair of split word lines and a source electrode connected to a bit line; and the pair of split word lines. A gate electrode is connected to a second split word line inside, a source electrode is connected to a bit bar line, a second transistor is connected to a drain electrode of the first transistor, and a second electrode is connected to the second electrode. A first capacitor connected to two split word lines, a first electrode connected to a drain electrode of the second transistor, and a second electrode connected to the first SWL. The SWL ferroelectric memory device according to claim 7, wherein 9. An X which decodes input X and Z addresses and controls the corresponding cell array block to operate.
A post-decoder unit, a global control pulse generator that outputs control pulses necessary for writing and reading data based on a CSBpad signal input from the outside, and a control pulse of the global control pulse generator, A local control pulse generator for outputting a control signal required for writing and reading data, a SWL cell array block for storing data, and a SWL cell array block based on control signals of the X post decoder unit and the local control pulse generator. A SWL driver for driving a Y address signal, a Y address decoder for decoding and outputting a Y address signal input from the outside, and a column based on a control signal of the local control pulse generator and a decode signal of the Y address decoder. A column controller for controlling, and the local control pulse generator The sensing device according to claim 1, further comprising: a sensing and data input / output control unit for sensing data of the cell array based on a control signal of the control unit and control of a column control unit and writing data to the cell array. A driving circuit for driving any of the SWL ferroelectric memory devices. 10. A global control pulse generator, comprising: an input buffer for receiving a signal including an input CSBpad signal to generate first and second synchronization signals; and a first synchronization signal for the input buffer. A first internal signal for adjusting the enable time of the sense amplifier, a second internal signal for adjusting the column select enable time and adjusting the pull-up of the bit line of the reference cell, SW
A first controller for respectively outputting a third internal signal for generating an input signal of the L driver and other internal signals; and a pair of split words of the SWL driver for receiving a third internal signal of the first controller. A signal (S1) for generating a signal for driving one of the lines, a signal (S2) for generating a signal for driving the other, and a signal for adjusting an activation period of the signals (S1, S2). A second controller for outputting to the local control pulse generator a certain fourth internal signal, an interlock signal (P2) for compensating the normal operation of the signals (S1, S2) so as not to be hindered and improving the driving capability; The first and second synchronization signals of the input buffer unit and the fourth internal signal of the second controller are input and the CSBpa
a fifth internal signal for disabling all signals except signals (S1, S2) for generating a signal for driving the word line in synchronization with the signal d, the signals (S1, S2)
Is enabled, if the CSBpad signal is disabled, the third internal signal is output to interrupt the disable and extend the enable state until the signals (S1, S2) are normally operated. A controller; fifth and sixth internal signals of the third controller;
The first, second, and third internal signals of the controller and the first synchronization signal of the input buffer unit are input, and the N
MOS device enable signal (SAN) and PMOS device enable signal (SAP), first control signal (C1) for connecting the bit line of the main cell block to the first input / output node of the sense amplifier, reference cell A second control signal (C2) for connecting the bit line of the block and the second input / output node of the sense amplifier to each other; A third control signal (C3), a column selection enable time, and a fourth control signal for adjusting a pull-up of a bit line of a reference cell.
The driving circuit according to claim 9, further comprising a fourth controller that outputs a control signal (C4). 11. The input buffer unit includes: a power-up detection unit that detects and outputs a power supply state; and an externally input X, Z_ATD signal, and CSBpad.
A first NOR gate for performing a logical operation on a signal and an output signal of the power-up detection unit and outputting the same; a first inverter for inverting an output of the first NOR gate to output the second synchronization signal; and a first inverter. 11. The driving circuit according to claim 10, further comprising: a second inverter that inverts the output of the second inverter and outputs a first synchronization signal. 12. The power-up detecting unit detects a power supply voltage rise and outputs the detected power-up voltage. The power-up detecting unit compares an output signal of the power supply voltage rise detecting unit with a power supply voltage, amplifies and outputs the amplified signal. An amplifying unit; a feedback unit that feeds back an output of the amplifying unit to output a signal that can indicate a stable state and an unstable state of a power supply voltage; and improves a driving capability of an output of the feedback unit and outputs the output to an input buffer unit. The drive circuit according to claim 11, further comprising a power-up output unit. 13. The first controller outputs first and second delay signals obtained by dividing and delaying a first synchronization signal of the input buffer unit at different times, and outputs the first delay signal to a first synchronization signal. A first delay unit that outputs as an internal signal, a third inverter that inverts a second delay signal of the first delay unit, and a logical operation of a first synchronization signal of the input buffer unit and an output signal of the third inverter 11. The driving circuit according to claim 10, further comprising: a first NAND gate that outputs a second internal signal and a fourth inverter that inverts an output of the first NAND gate and outputs a third internal signal. 14. The second controller outputs a third and a fourth delay signal obtained by dividing and delaying a falling edge of a third internal signal output from the first controller at different times. A second NOR gate that performs a logical operation on a fourth delay signal of the second delay unit and the third internal signal of the first controller; and a second unit that delays a rising edge of an output signal of the second NOR gate by a predetermined time. A third delay unit, a fifth inverter for inverting the third internal signal, a logical operation of an output of the fifth inverter, an output signal of the second NOR gate, and an output of the third delay unit to generate a fourth internal signal. A second NAND gate for outputting, a third NAND gate for performing a logical operation on an output of the fifth inverter, a fourth delay signal of the second delay unit, and an output of the second NAND gate; A fourth delay unit for delaying a rising edge of an output of the third NAND gate by a predetermined time; a third delay unit for performing a logical operation on a third delay signal of the second delay unit, an output of the third NAND gate, and an output of the second NAND gate; A fourth NAND gate; a fifth delay unit for delaying a rising edge of an output of the fourth NAND gate for a predetermined time; and a logical operation of an output of the fourth delay unit and an output of the second NAND gate to form the first split word line. An S1 signal output unit for outputting a signal (S1) for generating a driving signal; and a signal for driving the first split word line by performing a logical operation on an output of the second NAND gate and an output of the fifth delay unit. An S2 signal output unit for outputting a signal (S2) to be generated; and a pulse signal (P2) output by increasing the driving capability of the signal of the second NAND gate. Driving circuit according to claim 10, characterized in that it comprises a pulse signal output section for. 15. The third controller receives a first synchronization signal of the input buffer unit and a fourth internal signal of the second controller, and outputs a high pulse of a pulse signal (P2) output from the second controller. And C
A signal extension unit that extends until the SBpad signal is enabled low; a sixth delay unit that delays a rising edge of an output signal of the signal extension unit for a predetermined time; and an inversion of a fourth internal signal of the second controller. A fifth NAND gate that performs a logical operation on a signal and a second synchronization signal of the input buffer unit to output a sixth internal signal; and performs an AND operation on an output of the sixth delay unit and an output of the fifth NAND gate The drive circuit according to claim 10, further comprising: an internal signal output unit that outputs a fifth internal signal. 16. The third controller, a seventh delay unit for delaying a rising edge of a fourth internal signal of the second controller for a predetermined time, an inverted signal of the fourth internal signal of the second controller, and the input buffer. A sixth NAND gate that performs a logical operation on the second synchronization signal of the second unit and outputs a sixth internal signal; and performs a logical operation on the output of the seventh delay unit and the output of the sixth NAND gate to output a fifth internal signal 11. The drive circuit according to claim 10, further comprising: an internal signal output unit that performs the operation. 17. The high pulse of a pulse signal (P2) output from the second controller, the third controller receiving a first synchronization signal of the input buffer unit and a fourth internal signal of the second controller. And C
A signal extension unit that extends until the SBpad signal is enabled low; an eighth delay unit that delays a rising edge and a falling edge of an output signal of the signal extension unit for a predetermined time; and a fourth internal part of the second controller A seventh NAND gate that performs a logical operation on an inverted signal of the signal and a second synchronization signal of the input buffer unit and outputs a sixth internal signal; and an AND of an output of the eighth delay unit and an output of the fifth NAND gate 11. The drive circuit according to claim 10, further comprising: an internal signal output unit that outputs a fifth internal signal by performing an operation. 18. The NM of a sense amplifier, wherein the fourth controller performs a logical operation on a first internal signal of the first controller and a fifth internal signal of a third controller.
A sense amplifier control signal output unit for outputting an enable signal (SAN) for the OS element and an enable signal (SAP) for the PMOS element of the sense amplifier; a third internal signal of the first controller and a fifth internal signal of the third controller; A first control signal (C1) for connecting the bit line of the main cell to the first input / output node of the sense amplifier by performing a logical operation on the bit line of the main cell and the second input / output node of the sense amplifier. A bit line switching signal output unit for outputting a second control signal (C2) for performing a logical operation on a second internal signal of the first controller and a fifth internal signal of the third controller, and a fourth control signal for the column. (C
4) a column control signal output unit that outputs a precharge control signal that performs a logical operation on the first synchronization signal of the input buffer unit or the sixth internal signal of the third controller to output a precharge third control signal (C3) The driving circuit according to claim 10, further comprising a signal output unit. 19. The bit line switching signal output unit performs a logical operation on a third internal signal of the first controller and a fifth internal signal of the third controller, and performs a logical operation on the bit line and a first input / output node of a sense amplifier. And a second control signal (C2) for connecting a bit bar line to a second input / output node of the sense amplifier. The driving circuit as described. 20. An input buffer unit for receiving a signal including a CSBpad signal input from the outside to generate first and second synchronization signals, and a first synchronization signal of the input buffer unit. And a feedback signal, and a low-voltage operation and a noise prevention unit that outputs a low-voltage detection signal that disables operation at a low voltage and a noise removal signal that filters noise of the first synchronization signal; A first internal signal for adjusting the enable time of the sense amplifier when the normal power supply voltage is supplied from the noise prevention unit and adjusting the enable time of the sense amplifier; A second internal signal for adjusting the line pull-up, S
A first controller that outputs a third internal signal for generating an input signal of the WL driver and another internal signal, and a pair of split words of the SWL driver that receives a third internal signal of the first controller. Line 1
A signal (S1) for generating a signal for driving the split word line, a signal (S2) for generating a signal for driving the second split word line, and the signals (S1, S)
A second internal signal, which is a signal for adjusting the activation period of 2), and a pulse signal (P2) having improved driving capability of the fourth internal signal are generated, and the fourth internal signal is low. A second controller that outputs the feedback signal of the voltage operation and noise prevention unit and outputs the pulse signal (P2) to the local control pulse generation unit; a first and a second synchronization signal of the input buffer unit; and the second controller Of the CSBpa
A signal (S) for generating a signal for driving the first split word line of the split word line in synchronization with the signal d.
1) and a fifth internal signal for disabling all signals other than a signal (S2) for generating a signal for driving the second split word line, and a CSBpad signal when the signals (S1, S2) are enabled. When disabled, disable is interrupted and the signal (S
(1), a third controller that outputs a sixth internal signal for extending the enable state until the operation is normally completed, and a fifth and sixth internal signals of the third controller and the first controller.
Input the first, second and third internal signals of the controller,
Enable signal (SA) for the NMOS element of the sense amplifier
N) and the enable signal (SAP) of the PMOS device, the bit line of the main cell block and the first of the sense amplifier.
A first control signal (C1) for connecting the input / output nodes to each other, and a second control signal (C1) for connecting the bit lines of the reference cell block and the second input / output nodes of the sense amplifier to each other.
A control signal (C2), a third control signal (C3) for adjusting a low voltage precharge of the bit line of the main cell, the bit line of the reference cell, and the sense amplifier node; A fourth output of a fourth control signal (C4) for adjusting the pull-up
The driving circuit according to claim 9, further comprising a controller. 21. The low-voltage operation and noise elimination unit, an eighth delay unit that delays a first synchronization signal of the input buffer unit for a predetermined time, and a rising edge of the first synchronization signal of the input buffer unit. A ninth delay unit, sixth and seventh inverter units for respectively inverting the outputs of the eighth and ninth delay units, a gate electrode and a source electrode are commonly connected to a power supply terminal (Vcc), and the drain electrode is A first NMOS transistor connected to the output terminal of the sixth inverter; a gate electrode connected to the output terminal of the sixth inverter; a source electrode connected to the seventh inverter; and a second NMOS transistor for outputting a signal to the drain electrode. And the gate electrode is grounded, and the source and drain electrodes are connected to the power supply terminal and the drain electrode of the second NMOS transistor, respectively. A first PMOS transistor, an eighth inverter for inverting a fourth internal signal fed back from the second controller, a sixth NAND gate for performing a logical operation on an output of the second NMOS transistor and an output of the eighth inverter, A ninth inverter for inverting an output of the NAND gate; a seventh NA for performing a logical operation on a first synchronization signal of the input buffer unit and an output of the ninth inverter to output a preactive pulse for precharge adjustment of the sense amplifier;
21. The driving circuit according to claim 20, further comprising: an ND gate; and a tenth inverter that inverts an output of the ninth inverter and outputs a low voltage detection and noise removal signal. 22. The low-voltage operation and noise elimination unit, a tenth delay unit that delays a first synchronization signal of the input buffer unit for a predetermined time, and a rising edge of the first synchronization signal of the input buffer unit. An eleventh delay unit, eleventh and twelfth inverter units for inverting the outputs of the tenth and eleventh delay units, respectively, a gate electrode and a source electrode commonly connected to a power supply terminal (Vcc), and a drain electrode A third NMOS transistor connected to the output terminal of the eleventh inverter; a thirteenth inverter for inverting a fourth internal signal fed back from the second controller; a gate electrode connected to the output terminal of the thirteenth inverter; The electrode is a fourth NMOS transistor connected to the output terminal of the twelfth inverter, and the gate electrode is the eleventh transistor. Is connected to an output terminal of Nbata, the source electrode is connected to the drain terminal of the first 4NMOS transistor, the fifth for outputting a signal to the drain electrode
An NMOS transistor, a gate electrode is grounded, a source electrode and a drain electrode are respectively a power supply terminal, a second PMOS transistor connected to a drain electrode of the fourth NMOS transistor, and an output of the fifth NMOS transistor is grounded by the feedback signal. 6th NMOS to turn on / off
A transistor; and a fifteenth, sixteenth, and seventeenth output terminal for inverting an output of the fifth NMOS transistor and outputting a low voltage detection and noise removal signal
An inverter, and an eighth NAND gate for performing a logical operation on the first synchronization signal of the input buffer unit and the output of the fifth NMOS transistor to output a preactive pulse for adjusting the precharge of the sense amplifier. Claim 20
Drive circuit described 23. A low voltage sensing unit for receiving a first synchronizing signal of the input buffer unit instead of the low voltage operation and noise prevention unit to detect a low voltage of a power supply and not operate at a low voltage. 21. The driving circuit according to claim 20, comprising: 24. The driving circuit according to claim 20, further comprising a noise removing unit that removes noise of the first synchronization signal, instead of the low voltage operation and noise preventing unit. 25. The first controller, wherein the first controller divides the low-voltage detection and noise removal signal of the low-voltage operation and noise prevention unit into different times and outputs fifth and sixth delay signals, and outputs the fifth delay signal. A tenth delay unit for outputting a signal as a first internal signal, an eighteenth inverter for inverting a sixth delay signal output from the tenth delay unit, a low-voltage detection and noise of the low-voltage operation and noise prevention unit A ninth NAND gate for performing a logical operation on the removal signal and the output signal of the eighteenth inverter to output a second internal signal; and a nineteenth inverter for inverting the output of the ninth NAND gate and outputting a third internal signal. 21. The drive circuit according to claim 20, comprising: 26. The fourth controller, comprising: a logical operation of a first internal signal of the first controller and a fifth internal signal of a third controller to perform a logical operation on an NM of a sense amplifier;
A sense amplifier control signal output unit for outputting an enable signal (SAN) of the OS element and an enable signal (SAP) of the PMOS element of the sense amplifier; a third internal signal of the first controller and a fifth internal signal of the third controller; A first control signal (C1) for connecting the bit line of the main cell block to the input / output node of the sense amplifier by performing a logical operation on the bit line of the reference cell block and the second input / output node of the sense amplifier. And a bit line switching signal output unit for outputting a second control signal (C2) for performing a logical operation on a second internal signal of the first controller and a fifth internal signal of the third controller to output a column control signal. A column control signal output section for outputting a fourth control signal (C4) to be activated, and a preactive pulse of the low voltage operation and noise prevention section. Claim 2, characterized in that it comprises a precharge control signal output unit and the sixth internal signal of the third controller and logic operation and outputs a precharge third control signal (C3)
0. The driving circuit according to 0.