DE19964457B4 - Circuit for driving a ferroelectric SWL memory - Google Patents

Abstract

Circuit for driving a ferroelectric SWL memory, comprising: - an X post decoder (21) for receiving and decoding addresses X and Z for activating control of a cell array block (23); - A global control pulse generator (16) for supplying a control pulse, as is required for writing or reading data, in response to an externally received signal CSBpad; - a local control pulse generator (20) for receiving the control pulse from the global control pulse generator (16) and for supplying a control signal as is necessary for writing and reading data; - an SWL cell array block (23) for storing data; - An SWL driver (22) for the control signals from the X decoder (21) and from the local control pulse generator (20); - a Y address decoder (18) for decoding an externally received signal for addresses Y; - an old one in response to the control signal from the local control pulse generator (20) and a decoded signal from the Y address decoder (18); and...

Description

The invention relates to a circuit for driving nonvolatile ferroelectric memories, more particularly a ferroelectric SWL (Split Word Line) memory with disk lines.

FRAMs (ferroelectric RAMs) with data speeds as high as those of DRAMs commonly used as semiconductor memories store data even in the voltage-off state, and attract attention as the next-generation memory. Like DRAMs, FRAMs use capacitors as memory cells, but with a ferroelectric substance to exploit the high residual polarization of the ferroelectric substance, so that data is not erased even after removal of a previously applied electric field.

1 shows a general hysteresis loop of a ferroelectric substance, and 1b illustrates the structure of a unit capacitor in a conventional ferroelectric memory.

From the in 1a It can be seen that the polarization induced by an electric field does not disappear even after the removal of an electric field, but remains at a certain value (state d or a), which is due to spontaneous polarization. These states d and a can be assigned the values 1 and 0 to realize a memory cell. In other words, is in 1b the state in which a positive voltage is applied to a node 1, a state c in 1a while the state in which no voltage is applied to the node 1 is the state d. Conversely, the state goes from d to f when a negative voltage is applied to node 1. When no voltage is applied to node 1, the state transitions to state a, and when a positive voltage is again applied, the state transitions via b to c. Finally, even if no voltage is applied to the two ends of the capacitor, a data value can be stored in one of the two stable states a or b. On the hysteresis loop, the state c-d is the state logical 1, and the a-f is the state logical 0.

When reading a data value from the capacitor, the state d is cleared. In the prior art, a sense amplifier is used to read a data value using a voltage generated in a reference voltage generator and a voltage generated in a main cell array. In a ferroelectric reference cell, two polarity 1 and 0 polarity modes are used to produce a reference voltage on a reference bitline. Accordingly, the sense amplifier compares a bit line voltage of a main cell and a reference bit line voltage of a reference cell to read information in the main cell. By rewriting the read data value within the same cycle, the deleted data value can be recovered.

Now, with reference to the attached 2 to 6 a known FRAM explained. There are 1T / 1C FRAMs with one transistor and one capacitor in a unit cell and 2T / 2C FRAMs with two transistors and two capacitors. 2 illustrates a known 1T / 1C FRAM cell array.

According to 2 is the known 1T / 1C FRAM cell array having a plurality of word lines W / L spaced apart in a fixed-interval direction, a plurality of plate lines P / L arranged between word lines in parallel therewith, and one A plurality of bit lines B1, ..., Bn arranged at a fixed interval in the direction orthogonal to each of the word lines W / L and the plate lines P / L. Each of the transistors in a unit memory cell has a gate connected to the word lines W / L, a source connected to an adjacent bit line B / L, and a drain connected to a first electrode of the capacitor, the second electrode of the capacitor being connected to an adjacent plate line P / L is connected.

Now, a driving circuit and the operation of the above-mentioned known 1T / 1C-FRAM will be explained. The 3a and 3b together illustrate a circuit for driving the known 1T / 1C FRAM, 4a illustrates the timing of signals to explain writing to a known 1T / 1C FRAM cell, and 4b illustrates the timing of signals to explain reading from a known 1T / 1C FRAM cell.

The known circuit for driving a 1T / 1C FRAM is provided with: a reference voltage generating part 1 for generating a reference voltage; a reference voltage stabilizer 2 comprising a plurality of transistors Q1-Q4 and a capacitor C1 for stabilizing a reference voltage on two adjacent bit lines B1 and B2, since the reference voltage from the reference voltage generating part 1 can not be supplied directly to a sense amplifier; a first reference voltage storage part 3 comprising a plurality of transistors Q6 and Q7 and capacitors C2 and C3 for storing the logical value 1 and the logic value 0 on adjacent bit lines; a first compensation part 4 a transistor Q5 for equalizing two adjacent bit lines; a first main cell array part 5 comprising a plurality of transistors Q8, Q9, ..., and ferroelectric capacitors C5, C6, ... connected to word lines W / L and plate lines P / L for storing data, a first sense amplifier part 6 multi-transistor Q10-Q15 and P-sense amplifiers PSA for detecting the data value in one by one word line of the plurality of cells in the main cell array part 5 selected cell; a second main cell array part 7 comprising a plurality of transistors Q26, Q27, ... and capacitors C7, C8, ... connected to mutually different word lines and plate lines to store data; a second reference voltage storage part 8th comprising a plurality of transistors Q28 and Q29 and capacitors C9 and C10 for storing the logic value 1 and the logical value 0 in adjacent bit lines; and a second sense amplifier part 9 comprising a plurality of transistors Q16-Q25 and N sense amplifiers NSA for detecting data in the second main cell array part 7 ,

Now, the function of this known 1T / 1C FRAM will be explained. In this case, a writing and a reading mode are explained separately.

According to 4a For example, in order to start the write mode after activating a signal CSBpad, a chip signal is externally transferred from high to low, and a write mode enable signal WEBpad is also transitioned from high to low. In addition, address decoding is started with a low-to-high transition on a selected line to select a cell. While the word line is held high, a high signal is applied during one interval and a low signal is applied to a corresponding plate line P / L during a subsequent interval. To write logic 1 or 0 to the selected cell, a high or low signal is applied to a corresponding bit line in synchronism with the write enable signal. That is, when a high signal is applied to the bit line to write the logical value 1, it is written into the ferroelectric capacitor within the one interval in which the word line is high while the plate line signal is being written is at low and to write the logic 0 when a low signal is applied to the bit line while the plate line signal is high. Thus, either logical 1 or logical 0 is written.

A read is performed as follows.

According to 4b For example, if a signal CSBpad, a chip enable signal, is activated externally from high to low before a corresponding wordline is selected, all bitlines are equalized low by a balance signal. That is, in 3 then, if a high signal to the balancing section 4 is applied and a high signal is applied to transistors Q19 and Q20 to ground the bit lines across these transistors, the bit lines are balanced low. The transistors Q5, Q19 and Q20 are turned off, which deactivates the corresponding bit lines, and an address is decoded to bring a corresponding word line from low to high to select a corresponding cell. Then, a high signal is applied to the plate line of the selected cell to erase a data value stored in the FRAM, which corresponds to logic 1. If the FRAM stores the logical value 0, the corresponding data value is not deleted. A cell with a deleted data value and a cell without a deleted data value provide signals different from each other according to the above-mentioned hysteresis loop principle. The data value supplied via the bit line is detected by the sense amplifier as logical value 1 or 0. That is, according to 1 Since the case of an erased data value is the case where the state changes from d to f, and the case of a non-erased data value is the case where the state changes from a to f, then when the sense amplifier after a certain time is activated, in the case of a deleted data value it is amplified to give a logical 1, whereas in the case of an undeleted data value the same is amplified to provide logic 0. After the sense amplifier amplifies and delivers a signal, the plateline is disabled from high to low because the original data value in the cell should be restored while a high signal is applied to a corresponding line.

However, in the case of a known 1T / 1C FRAM in which a reference cell works more than a main memory cell, the reference cell quickly deteriorates, providing an unstable reference voltage. In addition, adjusting the reference voltage using a voltage regulation circuit is not stable because of influences of external voltage characteristics and noise. These problems with a 1T / 1C FRAM should not exist in a 2T / 2C FRAM which takes into account all practically applicable solutions (development in electrode replacement materials, package density, ferroelectric thin film stability, operational reliability, etc.).

5 illustrates an arrangement of known 2T / 2C FRAM cells, 6a illustrates the timing of various signals for a write to a known 2T / 2C FRAM cell, and 6b illustrates the timing of various signals for a read operation relating to a known 2T / 2C FRAM cell.

According to 5 the array of known 2T / 2C FRAM cells is provided with: a plurality of word lines W / L arranged in a direction spaced from each other; a plurality of plate lines P / L arranged in parallel with the word lines therebetween; and a plurality of bit lines and bit line lines B1, BB1, B2, BB2 sequentially arranged in the direction orthogonal to the word lines W / L and the fixed-interval plate lines P / L. In addition, gate electrodes of the two transistors in a unit memory cell are commonly connected to an adjacent word line W / L, the source electrodes of the transistors are connected to an adjacent bit line B, and the drain electrodes of the transistors are respectively connected to first capacitors to two capacitors. while the second electrodes of the capacitors are commonly connected to an adjacent plate line P / L.

Now, a driving circuit and the operation of the array of the known 2T / 2C FRAM cells will be explained.

In the array of known 2T / 2C FRAM cells, logic values 1 or 0 are written and read in a different way than in the known 1T / 1C FRAM cells. That is, according to 6a in a write mode, when a signal CSBpad, a chip enable signal, is brought externally from high to low, the array is activated, while at the same time a write mode enable signal WEBpad also makes a high to low transition to high and low or low and high signals to be applied to the bit line and the bit rail line depending on the logical value to be written. Then, an address decode is started to make a transition from low to high on a word line of a selected cell to select the cell. Within an interval in which the word line is held high, a corresponding disk line P / L is held high for a fixed interval and then low for a fixed interval. That is, for writing logic 1, a high signal is applied to a bit line Bn and a low signal is applied to a bit line BB-n, and to write logic 0, a low signal to a bit line Bn, and a high signal a bit rail line BB-n is applied. Thus, either logical 1 or logical 0 is written.

Now, the process of reading a data value from a cell will be explained.

According to 6b For example, a read mode is activated by externally switching a signal CSBpad, a chip enable signal, from high to low. That is, a write mode enable signal WEBpad is brought from low to high to terminate the write mode and to activate a read mode. Before a required word line is selected, all bit lines are equalized low by a equalizer signal, which is similar to the one in 3b 1T / 1C FRAM operation is identical. After completion of the equalization to low, an address is decoded to bring a signal on the required word line from low to high, thereby selecting the desired cell. In addition, a high signal is applied to a plate line of the selected cell to erase a data on the bit line or the bit line line. That is, when logic 0 is written, the data in the capacitor connected to the bit line is cleared, while when logic 0 is written, the data in the capacitor connected to the bit line is canceled. Thus, depending on the data value erased on the bit line or the bit rail line, another value is supplied according to the hysteresis loop principle. When the data value supplied via the bit line or the bit rail line is detected by the sense amplifier, the data value is either logic 1 or logic 0. After the sense amplifier has amplified and supplied the data value, the plate line is deactivated from high to low because in the cell Data value should be restored while the required word line is set high.

The following problems exist in the known FRAMs and the circuits for driving them.

First, while FRAM has an advantage in that data is maintained even after the power is turned off, cell plate wiring causes a complicated layout and a complicated manufacturing process, which is disadvantageous for mass production.

Second, providing a control signal to the disk line for reading and writing data affects the efficiency of the memory.

Third, with a known FRAM, the integration problem can not be overcome unless new electrode and new barrier materials are developed.

Fourth, there is another problem in terms of integration in that it is not possible to form a capacitor directly on a substrate of silicon or polysilicon, resulting from heretofore inadequate development of the technique for producing a ferroelectric film directly on a silicon surface, resulting in a FRAM has a larger area than a DRAM with the same storage capacity.

Fifth, particularly in a known 1T / 1C FRAM, the reference cell experiences a rapid deterioration in its ferroelectric properties, resulting in unstable reference voltage, since the reference cell is available for a few hundred main memories for use in read operations, so that it operates much more while the Function of their ferroelectric substance is not completely guaranteed.

The EP 0 671 745 A2 describes a semiconductor memory device. Here, a circuit for driving a ferroelectric memory includes a multiplexer provided with an FN memory for storing mode information of memory cells of a cell array block. In addition, a clock control circuit is provided which determines the mode, such as a read, write or a refresh mode. A control circuit reads out a signal from the FT memory array during a refresh operation and adds +1 to the read signal and writes the accumulated result into the same memory cell, thus updating the continuous refresh operation counter. Further, a word line driver is provided to drive the word lines of the cell array block. A Y decoder decodes a Y address signal to generate a Y select signal. This signal controls a Y-switch, thereby writing the write signal provided by the input / output buffers to the selected memory cell in the matrix in the case of a write operation and, in the case of a read operation, outputting the stored information in the memory cell and a selected one Amplified sense amplifier.

The DE 196 46 197 A1 describes a semiconductor memory device with shared word lines. Here, the semiconductor memory device has divided word lines, by which the degree of integration is increased by reducing the pitch of the word lines. In this case, the size of each word line driver is increased and the number of drivers per word increased, and at least two sub-word lines per main word line can be arranged to reduce the pitch of the sub-word line. The apparatus includes first and second memory cell arrays, a predecoder for receiving row addresses and generating a plurality of predecode signals, a plurality of word lines each divided into four sub-word lines, a first block of word line driver circuits connected to the odd-numbered sub-word lines, a second block of word line driver circuits connected to the even partial word lines, and a third block of word line driver circuits connected to the even partial word lines.

The DE 691 18 928 T2 describes a semiconductor memory array and a data processing device and their use. Here, a circuit for driving an SRAM memory includes an X decoder and a word line buffer circuit for selecting word lines, a Y decoder for selecting transmission element circuits, and a Z address buffer circuit which generates a block signal for selecting one of the plurality of blocks , In addition, an X address buffer circuit is provided which transmits information to the X decoder. A Y address buffer circuit transfers information to the Y decoder, and address change detection circuits detect a change in the address input signals of the X, Y and Z buffer circuits.

The invention has for its object to provide a circuit for driving a ferroelectric SWL memory without cell plate line, in which the driving behavior is improved to the ferroelectric SWL memory.

This object is achieved with respect to the circuit by the teachings of the independent claims 1, 6, 10 and 25.

Advantageous embodiments and modifications of the invention are set forth in the subclaims.

The invention will be more fully understood from the following detailed description and the accompanying drawings, which are given by way of illustration only and thus are not limitative of the invention.

1a illustrates a general hysteresis loop of a ferroelectric substance;

1b Fig. 10 illustrates the structure of a unit capacitor in a conventional ferroelectric memory;

2 illustrates a known 1T / 1C FRAM cell array;

3a and 3b together illustrate a circuit for driving the known 1T / 1C FRAM;

4a Fig. 10 illustrates waveforms of signals to explain a write operation for a known 1T / 1C FRAM cell;

4b Fig. 10 illustrates waveforms of signals to explain a read operation for a known 1T / 1C FRAM cell;

5 illustrates an array of known 2T / 2C FRAM cells;

6a Fig. 10 illustrates waveforms of signals to explain a write operation for a prior art 2T / 2C FRAM cell;

6b Fig. 10 illustrates waveforms of signals to explain a read operation for a known 2T / 2C FRAM cell;

7 illustrates an array of ferroelectric SWL memory cells according to a preferred embodiment of the invention;

8th Figure 12 illustrates a circuit of an array of SWL ferroelectric memory cells according to a first embodiment of the invention;

9 Figure 12 illustrates a circuit of an array of SWL ferroelectric memory cells according to a second embodiment of the invention;

10 Fig. 12 illustrates a circuit of an array of SWL ferroelectric memory cells according to a third embodiment of the invention;

11 Fig. 12 illustrates a block diagram of a circuit for driving an SWL memory according to the invention;

12 Fig. 10 illustrates a block diagram of a global control pulse generator according to a first preferred embodiment of the invention;

13 Fig. 12 illustrates a block diagram of a global control pulse generator according to a second preferred embodiment of the invention;

14 Fig. 12 illustrates a block diagram of a receive buffer according to a first preferred embodiment of the invention;

15 Fig. 12 illustrates a block diagram of a receive buffer according to a second preferred embodiment of the invention;

16 Fig. 12 illustrates a block diagram of a receive buffer according to a third preferred embodiment of the invention;

17 Fig. 12 illustrates a block diagram of a receive buffer according to a fourth preferred embodiment of the invention;

18 Fig. 12 illustrates a circuit diagram of a voltage turn-on detector according to a first preferred embodiment of the invention;

19 Fig. 12 illustrates a circuit diagram of a low-voltage operation and interference elimination device according to a first preferred embodiment of the invention;

20 Fig. 12 illustrates a circuit diagram of a low voltage operation and interference elimination device according to a second preferred embodiment of the invention;

21 Fig. 12 illustrates a circuit diagram of a low-voltage operation and interference signal removal device according to a third preferred embodiment of the invention;

22 Fig. 11 is a circuit diagram of a low-voltage operation and disturbance signal eliminating apparatus according to a fourth preferred embodiment of the invention;

23 Fig. 12 illustrates a circuit diagram of a first control unit according to a first preferred embodiment of the invention;

24 Fig. 12 illustrates a circuit diagram of a second control unit according to a first preferred embodiment of the invention;

25 Fig. 11 is a circuit diagram of a third control unit according to a first preferred embodiment of the invention;

26 Fig. 12 illustrates a circuit diagram of a third control unit according to a second preferred embodiment of the invention;

27 Fig. 11 is a circuit diagram of a third control unit according to a third preferred embodiment of the invention;

28 Fig. 12 illustrates a circuit diagram of a fourth control unit according to a first preferred embodiment of the invention;

29 Fig. 12 illustrates a circuit diagram of a fourth control unit according to a second preferred embodiment of the invention;

30 Fig. 10 illustrates operational timings of the voltage turn-on detector in the invention;

31 Fig. 10 illustrates functional timings of the global control pulse generator in the first embodiment of the invention;

32 Fig. 12 illustrates functional timings of the global control pulse generator in the second embodiment of the invention;

33 Fig. 12 illustrates functional timings of the global control pulse generator in the third embodiment of the invention; and

34 Fig. 12 illustrates functional timings of the global control pulse generator in the fourth embodiment of the invention.

Now preferred embodiments of the invention will be explained in more detail with reference to the accompanying drawings.

According to 7 The ferroelectric memory chip according to the first embodiment of the present invention basically includes SWL drivers each for driving divided word lines, cell arrays for storing data, and cores including a sense amplifier block for detecting data and a bit line control block for controlling bit lines. The cell arrays are located to the left and right of an SWL driver, and the cores are arranged up and down between cell arrays.

Now, a cell array will be explained in detail. 8th FIG. 12 shows a circuit of a sub-block array of ferroelectric SWL memory cells according to a first embodiment of the invention.

According to 8th A ferroelectric SWL memory cell array includes a plurality of divided word lines (hereinafter referred to as SWL) SWL1-n, SWL2-n, ... SWL2-n + 3 arranged in a fixed interval direction, and a plurality of bit lines of bit lines. n, bit-n + 1, ... Rbit-n, Rbit-n + 1, which are arranged in a direction perpendicular to the fixed-interval SWLs. For each pair of two adjacent SWLs and two adjacent bit lines, a unit cell is formed. A unit cell includes a first transistor whose gate electrode is connected to a first SWL of the pair SWLs, and a source electrode connected to a first bit line of the pair of bit lines, a second transistor having a gate electrode connected to the second SWL of the pair SWLs and a source electrode connected to the second bit line of the pair of bit lines, a first capacitor having a first electrode connected to the drain electrode of the first transistor and a second electrode connected to the second SWL, and a second electrode second capacitor having a first electrode connected to the drain electrode of the second transistor and a second electrode connected to the first SWL. The cell array actually includes a main cell area for writing data and a reference cell area for storing a reference value for reading data. Thus, main cells and a plurality of bit lines for the main cells form a main cell sub-block, and a pair of reference cell bit lines RBit-n and RBit-n + 1 for each main cell sub-block form a reference cell sub-block, and a plurality of main cell blocks and a plurality of reference cell sub-blocks form a cell array.

9 Fig. 12 illustrates a circuit of a sub-block array of ferroelectric SWL memory cells according to a second embodiment of the invention. The system of the SWL ferroelectric memory cell array according to the second embodiment of the invention is the same as that according to the first embodiment except that the main cell sub block has eight columns, the reference cell sub block has two columns. In addition, the main cell subblock may have 2n columns (n is an integer greater than 2), where the reference cell block has two columns.

10 Fig. 12 illustrates a circuit of a SWL ferroelectric memory cell array according to a third embodiment of the invention.

According to 10 That ferroelectric SWL memory cell array includes a plurality of divided word lines (hereinafter referred to as SWL) SWL1-n, SWL2-n, ..., SWL2-n + 3 arranged in a fixed interval direction, and a plurality of bit lines Bn , B-n + 1 and bit rail lines BB-n, BB-n + 1, which are alternately arranged in a direction perpendicular to the fixed-interval SWLs. For each pair of two adjacent SWLs and a pair of a bit line B and a bit rail line BB, which are adjacent to each other, a unit cell is formed. That is, the unit cell includes: a first transistor whose gate electrode is connected to a first SWL of the pair SWLs and a source electrode connected to the bit line B; a second transistor whose gate electrode is connected to the second SWL of the pair SWLs, and a source electrode connected to the bit rail line BB; a first capacitor having a first electrode connected to the drain electrode of a first transistor connected to a second electrode connected to the second SWL; and a second capacitor having a first electrode connected to the drain electrode of the second transistor and a second electrode connected to the first SWL. The ferroelectric SWL memory cell array according to the third embodiment of the invention is similar to the SWL ferroelectric memory cell arrays according to the first and second embodiments except that the even-numbered bit lines B in the first and second embodiments are replaced by the bit rail lines BB and all the reference cell sub-blocks at the first and second second embodiment are replaced by main cells.

Now, a circuit for driving a ferroelectric memory according to the present invention will be explained. 11 Figure 12 illustrates a block diagram of a circuit for driving such a memory. The circuit is designed to drive the memory according to the first, second or third embodiment.

According to 11 this circuit includes: an x-buffer 11 for buffering an address X, Y and Z; an X predecoder 12 for predecoding the signal from the X buffer 11 ; a Z-buffer 13 for buffering an address Z among the addresses X, Y and Z; a Z predecoder 14 for predecoding the signal from the Z-buffer 13 ; an (X, Z ATD) generator 15 for detecting address transition points of the signals for the addresses X and Z from the X-buffer 11 or from the Z-buffer 13 ; a global control pulse generator 16 for receiving the signal from the (X, Z-ATD) generator 15 and an external signal CSBpad for self-generating a voltage-on detection signal and for providing a basic pulse for memory control in accordance with the (X, Z-ATD) signal, the signal CSBpad and the power-on detection signal; a Y buffer 17 for buffering the address Y among the externally received addresses X, Y and Z; a Y predecoder 18 for predecoding the signal from the Y buffer 17 ; a Y ATD generator 19 for detecting an address transition point in the signal of the address Y from the Y buffer 17 ; a local control pulse generator 20 for connecting a signal from the global control pulse generator 16 , the Z predecode signal from the Z predecoder 14 and the signal from the Y-ATD generator 19 to a pulse required in each memory block; an X-post decoder 21 for composing the X predecode signal and the Z predecode signal from the X predecoder 12 or from the Z predecoder 14 for selecting a cell block; a SWL driver 22 for composing signals from the X-post decoder 21 and from the local control pulse generator 20 for driving divided word lines in each of SWL cell blocks 23 ; a column control unit 24 for assembling signals from the Y predecoder 18 and from the local control pulse generator 20 for selecting a bit line (or a bit rail line); a sense amplifier with I / O control unit 25 for composing a signal from the local control pulse generator 20 and a signal from the column control unit 24 for controlling the operation of the sense amplifier and the input / output (I / O); and an I / O bus control unit 26 for interfacing between an external data bus and the sense amplifier with I / O control unit 25 ,

Now, the global control pulse generator will be explained in more detail. 12 shows a block diagram thereof according to the first preferred embodiment of the invention.

According to 12 This global control pulse generator includes the following: a receive buffer 31 for receiving a signal comprising at least the signal CSBpad, the (X, Z-ATD) signal from the (X, Z-ATD) generator 15 and the voltage-containing detection signal to provide a first and a second synchronizing signal; a low-voltage operation and interference signal removal device 32 for supplying a low voltage detection signal for stopping the operation at a low voltage, a disturbance canceling signal for filtering a disturbance signal in the first synchronizing signal, a pre-activating pulse for preloading the bit lines, and the like to the first synchronizing signal from the receiving buffer 31 and a feedback signal (fourth control signal from a second control unit); a first control unit 33 which, when detected by the low voltage operation and interference signal eliminator 32 a normal supply voltage is supplied, receives a signal from which the disturbance is eliminated, and a first control signal for controlling an activation timing for the sense amplifier, a second control signal for controlling a Spaltenauswählaktivierungszeitpunkts and a Bitleitungshochziehzeitpunkts for a reference cell and a third control signal for generating a Generates signals for the SWL driver as well as other control signals; a second control unit 34 for receiving the third control signal from the first control unit 33 to generate a basic waveform generation signal S1 for the SWL1 and a basic waveform generation signal S2 for the SWL2 in a pair SWLs for the SWL driver, a fourth control signal which is a basic pulse signal for controlling release time periods of the signals S1 and S2, and a pulse signal P2 with a driving capability improved over that of the fourth control signal, and the fourth control signal as a feedback signal the low-voltage operation and interference signal removal device 32 to deliver and the pulse signal P2 to the local control pulse generator 20 to deliver; a third control unit 35 for receiving the first and second synchronizing signals from the receiving buffer 31 and the fourth control signal from the second control unit 34 and for providing a fifth control signal for controlling synchronism with the signal CSBpad when all signals except for the basic waveform generation signal S1 for the SWL1 and the basic waveform generation signal S2 for the SWL2 are deactivated and a sixth control signal for interrupting a deactivated state of Signal CSBpad when it is deactivated in a state in which the basic waveform generation signal S1 for the SWL1 and the basic waveform generation signal S2 for the SWL2 are activated, and to maintain the activated state until the normal operations for the basic waveform generation signal S1 for the SWL1 and the basic waveform generation signal S2 for the SWL2, and a fourth control unit 36 for receiving the fifth and sixth control signals from the third control unit 35 , the first, second and third control signals from the first control unit 33 and the pre-activation pulse from the low-voltage operation and interference signal removal device 32 and for providing an enable signal SAN for an NMOS device and an enable signal SAP for a PMOS device in the sense amplifier, a control signal C1 for connecting a bit line to a main cell block, and a first I / O node at the sense amplifier to each other, a control signal C2 for connection a bit line at a reference cell block and a second I / O node of the sense amplifier with each other, a control signal C3 for controlling low voltage precharge operations of a bit line at a main cell, a bit line at a reference cell and a node at the sense amplifier, and a control signal C4 for controlling the activation timing of one Column selection operation and a bit-line pull-up operation for a reference cell.

Meanwhile, when the externally supplied signals (the signal CSBpad, the (A, Z-ATD) signal and the power-on detection signal) for the global control pulse generator in the first embodiment are constant, the low-voltage operation and interference elimination means can be omitted. which will be explained with reference to a second embodiment. 13 FIG. 12 illustrates a block diagram of a global control pulse generator according to a second preferred embodiment of the invention. FIG.

According to 13 This global control pulse generator includes the following: a receive buffer 31 for receiving a signal comprising at least the signal CSBpad, the (X, Z-ATD) signal from the (X, Z-ATD) generator 15 and the voltage-on detection signal includes, and to provide a first and a second synchronizing signal; a first control unit 33 for receiving the first synchronizing signal from the receiving buffer 31 and providing a first control signal for controlling the activation timing of the sense amplifier, a second control signal for controlling a column select enable timing and a bitline pullup timing for a reference cell, and a third control signal for providing a signal to the SWL driver and other control signals; a second control unit 34 for receiving the third control signal from the first control unit 33 for generating a basic signal waveform generation signal S1 for the SWL1 and a fundamental waveform generation signal S2 for the SWL2 in a pair SWLs for the SWL driver, a fourth control signal which is a basic pulse signal for controlling activation time periods for the signals S1 and S2, and a pulse signal P2 having a driving capability improved over that of the fourth control signal, and supplying the pulse signal P2 to the local control pulse generator 20 ; a third control unit 35 for receiving the first and second synchronizing signals from the receiving buffer 31 and the fourth control signal from the second control unit 34 and for providing a fifth control signal for controlling synchronism with the signal CSBpad when all signals except for the basic waveform generation signal S1 for the SWL1 and the basic waveform generation signal S2 for the SWL2 are deactivated and a sixth control signal for interrupting the deactivated state of Signal CSBpad when it is deactivated in the state in which the basic waveform generation signal S1 for the SWL1 and the basic waveform generation signal S2 for the SWL2 are activated, and to keep the activated state until the normal operations of the basic waveform generation signal S1 for the SWL2 SWL1 and the basic waveform generation signal S2 for the SWL2 are completed; and a fourth control unit 36 for receiving the fifth and sixth control signals from the third control unit 35 , the first, second and third control signals from the first control unit 33 and the synchronizing signal from the receiving buffer 31 and for providing an enable signal SAN for an NMOS device and an enable signal SAP for a PMOS device in the sense amplifier, a control signal C1 for connecting a bit line to a main cell block and a first I / O node to the sense amplifier, a control signal C2 for connecting a bit line to a reference cell block and a second I / O node to the sense amplifier with each other, a control signal C3 for controlling a low voltage precharge of a bit line at a main cell, a bit line at a reference cell and a node at the sense amplifier, and a control signal C4 for controlling the release timing of a column selection operation and a bit line pull-up operation of a reference cell.

Meanwhile, though not shown, the low-voltage operation and disturbance signal eliminating means in the global control pulse generator of the first embodiment may be a low-voltage operation eliminator which prevents operation at a low voltage or a noise elimination apparatus having the function of disturbance elimination.

Now, various parts of the above-mentioned global control pulse generator in the invention will be explained in more detail. The 14 to 17 show circuit diagrams of receive buffers according to first to fourth preferred embodiments of the invention.

The in 14 illustrated receive buffers according to the first preferred embodiment, which is adapted to use only the externally supplied signal CSBpad, includes the following: three inverters connected in series 41 . 42 and 43 for inverting the signal CSBpad to provide a first synchronizing signal from the inverter 43 and a second synchronizing signal from the inverter 42 , As it is in 15 12, the receiving buffer according to the second preferred embodiment, which is configured to receive the externally supplied signal CSBpad and a power-on detection signal, includes a power-on detector 44 for supplying a high signal until the voltage is stabilized when a low signal for stabilizing the circuit operation is supplied, a NOR gate 45 for applying the externally supplied signal CSBpad and the signal from the power-on detector 44 an OR operation and an inversion, an inverter 46 for inverting the signal from the NOR gate to provide a second synchronizing signal and an inverter 47 for inverting the signal from the inverter 46 for providing a first synchronizing signal. As it is in 16 2, the receive buffer according to the third preferred embodiment, which is configured to receive the externally supplied signal CSBpad and the (X, Z-ATD) signal from the in 11 , represented (X, Z-ATD) generator 15 receives a system that works with the in 15 is identical, except that the NOR gate 45 at its one input terminal receives the (X, Z-ATD) signal. As it is in 17 1, the receive buffer according to the fourth preferred embodiment, which is configured to receive the externally supplied signal CSBpad, the (X, Z-ATD) signal from the in 11 represented (X, Z-ATD) generator 15 and the power-on detection signal receives, a system identical to that in FIG 15 is shown, except that instead of the NOR gate 45 a NOR gate 48 is used with three receiving terminals which subject the (X, Z-ATD) signal, the signal CSBpad and the power-on detection signal to an OR operation and an inversion.

Now, a detail circuit of the power-on detector will be explained. 18 shows a circuit diagram of such a detector according to a first preferred embodiment of the invention.

According to 18 This voltage detector includes the following: a supply voltage rise detector 233 with PMOS transistors 211 - 214 and NMOS transistors 215 - 218 for detecting an increase in the supply voltage; an amplifier 234 with PMOS transistors 219 and 220 and NMOS transistors 221 - 224 to compare the signal from the supply voltage rise detector and the supply voltage to a comparison and a gain; a feedback part 235 with PMOS transistors 225 and 229 , an NMOS transistor 230 as well as inverters 226 - 228 for feeding back a signal from the amplifier 234 for providing a signal that provides stability of the supply voltage; and a power-on delivery unit 236 with inverters 231 and 232 for improving the control capability of a signal from the feedback part 235 for use in the global control pulse generator.

Now, the low-voltage operation and interference signal removal device in the invention will be explained. 19 and 20 Illustrate circuit diagrams thereof according to a first and a second preferred embodiment.

• – Erstens wird durch Erfassen einer niedrigen Spannung und durch Sperren eines Steuerungsimpulses bei niedriger Spannung ein Speicherzellen-Datenwert geschützt.
• – Zweitens wird, durch Verzögern, die Impulsbreite eines Steuerungssignals C3 zur Verwendung beim Steuern eines Niederspannungs-Vorabladevorgangs eines Leseverstärkers gesteuert.
• – Drittens werden Störsignale aus dem von außen zugeführten Signal (Signal CSBpad) beseitigt.

This low-voltage operation and interference elimination device has three functions:

• First, by sensing a low voltage and disabling a control pulse at low voltage, memory cell data is protected.
• Secondly, by delaying, the pulse width of a control signal C3 is controlled for use in controlling a low voltage precharge operation of a sense amplifier.
• Third, noise is removed from the externally applied signal (CSBpad signal).

Accordingly, the low-voltage operation and interference signal removing apparatus according to the first preferred embodiment includes, as shown in FIG 19 the following: a low voltage detection and delay part 68 for detecting a low voltage for delaying the pulse width of the control signal C3 and a noise elimination part 69 for removing interference signals. The low voltage detection and delay part 68 includes a first delay unit 61 with inverters 79 and 80 for delaying the first synchronizing signal from the receiving buffer 31 for a given time; a second delay unit 62 with inverters 76 and 78 for lowering the current driving capabilities of a PMOS transistor as well as inverters 75 and 77 for improving the driving capability of PMOS transistors and NMOS transistors for delaying the rising edge of the first synchronizing signal for reducing the width of a high pulse of the first synchronizing signal from the receiving buffer 31 ; inverter 63 and 64 for inverting the signals from the first and second delay units, respectively 61 and 62 ; an NMOS transistor 65 a gate electrode and a source electrode connected in common to a power supply terminal Vcc and a drain electrode connected to the output terminal of the inverter 63 connected is; an NMOS transistor 67 with a gate electrode connected to the output terminal of the inverter 63 connected to a source electrode that connects to the inverter 64 and a drain electrode configured to pass a signal; and a PMOS transistor 66 having a grounded gate electrode and a source and a drain electrode connected to the power supply terminal and the drain electrode of the NMOS transistor, respectively 67 are connected. The interfering signal eliminating part 69 includes an inverter 70 for inverting the from the second control unit 34 returned fourth control signal; a NAND gate 71 for subjecting the signal from the low voltage sensing and delaying part 68 and the signal from the inverter 70 an AND operation and an inversion; an inverter 72 for inverting the output of the NAND gate 71 , a NAND gate 74 to get the first sync signal from the receive buffer 31 and the output signal from the inverter 72 an AND operation and an inversion to provide a pre-activation pulse for controlling a pre-charge operation for the sense amplifier; and an inverter 73 for inverting the output signal of the inverter 72 for providing a voltage detection and debugging signal.

On the other hand, as in 20 2, the low-voltage operation and interference signal removing apparatus according to the second preferred embodiment includes a noise elimination part between the inverter 64 and the NMOS transistor 67 in the 19 illustrated low voltage detection and delay part 68 , That is, the noise elimination part 69 The following includes: one between the inverters 64 and the NMOS transistor 67 switched NMOS transistor 85 ; an inverter 86 for inverting the feedback signal (the fourth control signal) from the second control unit 34 to connect it to the NMOS transistor 85 to deliver; and an NMOS transistor 87 for connecting the output of the NMOS transistor 67 with mass on the feedback signal. In addition, a system of a low-voltage operation and disturbance signal eliminator may be formed by adding: an inverter 81 for inverting the output signal of the NMOS transistor 67 ; an inverter 82 for inverting the output signal of the inverter 81 ; a NAND gate 84 to the output signal of the inverter 82 and the first sync signal from the receive buffer 31 an AND operation and inversion to provide a pre-activation pulse; and an inverter 83 for inverting the output signal of the inverter 82 to generate a low voltage detection and disturbance cancellation signal. In addition, from the into the 19 or 20 The low-voltage operation and interference signal removal device shown in the low-voltage detection and delay part 68 or the noise elimination part may be omitted. That is, that 21 illustrates a case when only one noise elimination part 69 is present without the low voltage detection delay part in 19 , while 22 illustrates a case where the low voltage detection and delay part 68 without the interfering signal elimination part in 20 is available.

In 23 is a detailed circuit diagram of the first control unit in FIG 12 or 13 illustrated global control pulse generator shown in the invention.

The first control unit includes a third delay unit 104 with inverters 91 - 100 for delaying the low voltage detection and removal signal from the low voltage operation and interference cancellation means or the first synchronization signal from the reception buffer 31 for a certain period of time to provide a first control signal; an inverter 101 for inverting the signal from the third delay unit 104 ; a NAND gate 102 to obtain the low voltage operation and interference removal signal from the low voltage operation and interference cancellation device or the first synchronization signal from the reception buffer 31 and a signal from the inverter 101 undergo an AND operation and inversion to a second To generate control signal; and an inverter 103 for inverting the output of the NAND gate 102 for providing a third control signal.

Now, the second control unit will be explained in the invention. 24 illustrates a circuit diagram of the same according to a first preferred embodiment.

According to 24 This second control unit includes a third delay unit 148 with several inverters 111 . 113 . 115 . 117 and 119 for reducing the current driving capabilities of a PMOS transistor and for improving the current driving capabilities of an NMOS transistor in the sense amplifier and inverter 112 . 114 . 116 . 118 and 120 for improving the current driving capabilities of the PMOS transistors and the NMOS transistors for delaying the falling edge of the third control signal from the first control unit 33 for a predetermined period of time; a NOR gate 121 to the output of the third delay unit 148 and subject the third control signal to an OR operation and inversion; a fourth delay unit 149 with several inverters 123 . 125 . 127 . 129 and 131 for reducing the current driving capabilities of the PMOS transistor and for improving the current driving capabilities of the NMOS transistor in the sense amplifier and inverter 122 . 124 . 126 . 128 and 130 for improving the current driving capabilities of the PMOS transistors and the NMOS transistors for delaying the rising edge of the signal from the NOR gate 121 for a predetermined period of time; an inverter 132 for inverting the third control signal; a NAND gate 133 to the output signals of the inverter 132 , the NOR gate 121 and the fourth delay unit 149 an AND operation and inversion to provide the fourth control signal; a NAND gate 134 to the output signals of the inverter 132 , the third delay unit 148 and the NAND gate 133 undergo an AND operation and inversion; a fifth delay unit 150 with inverters 135 - 138 for delaying the rising edge of the output signal of the NAND gate 133 for a predetermined period of time; a NAND gate 141 to the output signals of the inverter 113 , the NAND gate 134 and the NAND gate 133 undergo an AND operation and inversion; a sixth delay unit 151 with inverters 142 and 143 for delaying the rising edge of the output signal of the NAND gate 141 by a predetermined period of time; a forwarding unit 237 for the signal S1 with a NAND gate 139 and an inverter 140 to the output signals of the fifth delay unit 150 and the NAND gate 133 an AND operation to provide the basic waveform generation signal S1 for the SWL1; a forwarding unit 238 for the signal S2 with a NAND gate 144 and an inverter 145 to the output signals of the sixth delay unit 151 and the NAND gate 133 an AND operation to generate the basic signal waveform generation signal S2 for the SWL2; and a pulse signal forwarding unit 152 with inverters 146 and 147 for improving the signal driving capability of the NAND gate 133 for providing a pulse signal P2.

Now, the third control unit will be explained in the invention. 25 . 26 and 27 show circuit diagrams of the third control unit according to a first, second or third preferred embodiment.

According to 25 The third control unit according to the first preferred embodiment includes a signal extension unit 172 with an inverter 161 and NAND gates 162 . 163 and 164 for receiving the first synchronizing signal from the receiving buffer 31 and the fourth control signal from the second control unit 34 for increasing the high pulse of the pulse signal P2 from the second control unit 34 by the time the signal CSBpad is held low; a seventh delay unit 173 with inverters 165 - 168 for delaying the rising edge of a signal from the signal extension unit 172 by a predetermined period of time; a NAND gate 171 to the inverted fourth control signal and the second synchronizing signal from the receiving buffer 31 an AND operation and inversion to provide the sixth control signal; a control signal forwarding unit 174 with a NAND gate 169 and an inverter 170 to the output signals of the seventh delay unit 173 and the NAND gate 171 an AND operation to provide the fifth control signal.

According to 26 In the third control unit according to the second preferred embodiment, the signal extension unit 172 from the system of in 25 omitted third control unit to the fourth control signal directly to the seventh delay unit 173 to deliver.

According to 27 In the third control unit according to the third preferred embodiment, the eighth delay unit 179 designed to cover all parts (including the rising and falling edges) of the signal from the signal extension unit 172 delayed while in 25 the seventh delay unit 173 is designed so that it only the rising edge of the signal from the signal extension unit 172 delayed.

28 and 29 show circuit diagrams of a first and a second embodiment of a fourth control unit for in 12 illustrated global control pulse generator according to a first preferred embodiment.

According to 28 The fourth control unit according to the first preferred embodiment includes a sense amplifier control signal relay unit 199 with inverters 181 . 183 . 184 and 185 and a NAND gate 182 to the first control signal from the first control unit 33 and the fifth control signal from the third control unit 35 an AND operation and inversion to provide an enable signal SAN for the NMOS transistor in the sense amplifier and an enable signal SAP for the PMOS transistor in the sense amplifier; a bit line switching signal relaying unit 200 with a NAND gate 186 and inverters 187 - 191 to the third control signal from the first control unit 33 and the fifth control signal from the third control unit 35 a logic operation to generate a control signal C1 for connecting a bit line in a main cell block and a first I / O node to the sense amplifier, and a control signal C2 for connecting a bit line in a reference cell block and a second I / O node to the sense amplifier; a column control signal forwarding unit 201 with a NAND gate 192 and inverters 193 . 194 and 195 to the second control signal from the first control unit 33 and the fifth control signal from the third control unit 35 undergoing a logic operation to provide a control signal C4 for generating a column control signal; and a precharge control signal forwarding unit 202 with a NAND gate 196 and inverters 197 and 198 to the pre-activation pulse from the low-voltage operation and interference signal removal device 32 and the sixth control signal from the third control unit 35 a logic operation to generate a Vorabladesteuerungssignal C3.

According to 29 The fourth control unit according to the second preferred embodiment includes a sense amplifier control signal relay unit 199 with inverters 181 . 183 . 184 and 185 and a NAND gate 182 to the first control signal from the first control unit 33 and the fifth control signal from the third control unit 35 an AND operation and an inversion to provide an enable signal SAN for the NMOS transistor in the sense amplifier and an enable signal SAP for the PMOS transistor in the sense amplifier; a bit line switching signal forwarding unit 200 with a NAND gate 186 and inverters 187 - 191 to the third control signal from the first control unit 33 and the fifth control signal from the third control unit 35 performing a logic operation to generate a control signal C1 for connecting a bit line in a main cell block and a first I / O node to the sense amplifier and a control signal C2 for connecting a bit line in the reference cell block and a second I / O node to the sense amplifier; a column control signal forwarding unit 201 with a NAND gate 192 and inverters 193 . 194 and 195 to the second control signal from the first control unit 33 and the fifth control signal from the third control unit 35 undergoing a logic operation to provide a control signal C4 for generating a column control signal; and a precharge control signal forwarding unit 202 with inverters 197 . 198 and 203 to get the first sync signal from the receive buffer 31 or the sixth control signal from the third control unit 35 to provide a logic operation to provide a precharge control signal C3.

Now, a method of driving the above-mentioned ferroelectric SWL memory will be explained. 31 illustrates waveforms in various parts of the voltage turn-on detector in the invention.

For 31 It is assumed that the signal CSBpad, a chip enable signal, is fixed at the ground voltage to place the chip in an activated state in all its sections when the power is turned on. At time t1, when no voltage is applied yet, node signals N1-N6 are in a grounded state.

Interval t1-t2

The voltage is raised from the ground voltage to Vcc. The signal at node N1 rises, but with a gentle slope, because the PMOS transistor 219 is pulled up. The signal at a node N2 rises slowly due to a delay. The signal at node N4 is amplified to become ground voltage. The signal at node N5 rises in a floating state because of the NMOS transistor 230 is in the off state, and the signal at node N6 also increases due to the influence of the signal at node N4.

Interval t2-t3

When the NMOS transistor 221 is turned on, when the signal voltage at node N2 rises above a threshold voltage Vtn, the amplifier is made operative, so that the signal at node N1 falls slowly and the signal at node N4 rises to a voltage which is not sufficient, the output signal of the inverter 226 to invert to keep the signals at nodes N5 and N6 at Vcc.

Interval beyond t3

The signal at node N4 continues to rise to a voltage above a threshold voltage Vt for the inverter 226 when the signals at nodes N5 and N6 are inverted from high to low, to the NMOS transistor 224 turn off what the amplifier 234 disabled. The signal at node N4 rises due to the current from the PMOS transistor 225 to Vcc, and the power-on signal is brought into the low state. Therefore, although the signal CSBpad is fixed low, the voltage-on signal that is one of the received signals is in the receiving buffer 31 from high, the disabled state, to low, the enabled state.

Now, waveforms of the global control pulse generator in the invention using the power-on detector will be explained. The 31 to 34 illustrate operating timings in the first to fourth embodiments of a global control pulse generator in the invention.

The functions of global control pulse generators in the invention differ more or less depending on cell array systems, the switching of addresses X, Z or the switching of addresses Y back and forth. 31 illustrates the function in the case where the cell array is of the form shown in FIG 8th or 9 is shown, and the address Y is switched back and forth. Since the chip is activated when the chip enable signal CSBpad supplied from the outside is low, the chip is turned to the activated state when the signal CSBpad is switched from high to low. Therefore, a high interval disabled interval is required to perform a new read or write operation. As it is in 31 is shown, a complete cycle of operation is divided into intervals from t1 to t15 to allow a convenient explanation of the signal behavior. First, assume that the signal CSBpad is asserted low from the start point of the interval t1 to the end point of the interval t14 while being deactivated from the start point of the interval t15 to high. In addition, it is assumed that there is no transition in the addresses X and Z, and a transition of the address Y exists at the start point of the interval t7 and at the start point of the interval t11 while the signal CSBpad is in the activated state. A Y-ATD unit detects a change of the address Y for generating a high pulse from the intervals t7 to t8 and from t11 to t12. S1 and S2 are pulses for use in generating basic waveforms for word lines SWL1 and SWL2 for a SWL cell. First, the signal CSBpad undergoes a transition from high to low at interval t1 to activate the chip while holding the addresses X, Y, and Z in their states prior to t1. The signal Y-ATD is updated from t7 68 a transition to high if the address Y undergoes transition at the start time of t7. When the address Y undergoes a transition at this start time, the signal Y-ATD undergoes transition to high at intervals t11 to t12. The signal S1 is kept low until the interval t1, from the intervals t2 to t3 to high, to low in the interval t4, to high in the interval t5 and to low from the intervals t6 to t15. S2 is held high by t3 at t4 and otherwise held low. The signal C1, which is the fundamental signal for controlling the signal flow between a main cell bit line and an I / O terminal on the sense amplifier, is kept low only at interval t3 and otherwise held high to prevent the signal flow between the main cell line and an I / O Connection to the sense amplifier only in the interval t3 to prevent. The signal C2, which is the fundamental signal for controlling the signal flow between a reference cell bitline and the other I / O port on the sense amplifier, provides a pulse that is held low from t3 to t14 to control the signal flow between a reference cell bitline and the other I / O connection to the sense amplifier from t3 to t14. The signal C4 controlling the signal transition between a main cell bit line and an external data bus and pulling up a reference cell bit line is held high from t4 to t14, and goes low again at a time when the signal CSBpad is deactivated (for End time of the interval t14) to allow control of the signal transition between a main cell bit line and the external data bus and pulling up a reference cell bit line only from t4 to t14. The signal P2 is kept high from t2 to t5, in which intervals S1 and S2 are held high to protect these signals S1 and S2 from external interference, and again goes from low to low at the start time. The signal C3, which precharges a low voltage to the main cell bit line and the reference cell bit line before S1 and S2 are activated, while being held high until before the interval t1, experiences a transition to low at the start time of t2, where it is held until the end of t14 to deactivate the precharge operation, and again experiences a transition to high at intervals other than this (time at which the signal CSBpad is deactivated). The signal SAN (pre-signal for generating a signal SAN_C), which is a signal for controlling transistors with NMOS transistors for operating the sense amplifier in the sense amplifier with I / O control unit is held low as before, and goes low at the start point from t3 to high and at a time when the signal CSBpad is deactivated. The signal SAP (advance signal of a signal SAP_P, which controls transistors with PMOS transistors for operating the sense amplifier in the sense amplifier with I / O control unit) behaves opposite to the signal SAN; it is held high until the interval t2, a pre-stage, goes to low at the start point of t3, and goes high at the time the signal CSBpad is deactivated. Thus, in a state in which the signal CSBpad is activated, when the address Y undergoes a transition, so that Y-ATD occurs, when the write mode is present, the value of logic 0 at intervals in which both S1 and S2 are high, written in a relevant cell, ie, from the interval t2 to the interval t3, and the value logical 1 is written into the cell at intervals where only one of the signals S1 or S2 is high, ie, from the interval t4 to the interval t5 ,

The operation of the global control pulse generator is the same as that in FIG 32 which is the second embodiment in the case where the cell array system is of the type shown in FIG 8th or 9 is shown and the address X, Z is switched back and forth. A complete cycle of operation is divided into intervals t1 to t21, and the two addresses X, Z undergo a transition to the starting points of the intervals t7 and t14. Since the function of the global control pulse generator in the case of toggling the addresses X, Z is similar to the operation of the global control pulse generator in the case of switching the address Y to and fro, only those functional portions which are different will be described. While the signal Y-ATD experiences a transition to high at the time when the address Y in 31 When, in the second embodiment, it is assumed that both addresses X, Z undergo transition at the start points of the intervals t7 and t14, the (X, Z-ATD) signals are held high during the intervals t7 and t14 they are kept low in the remaining intervals. When the addresses X, Z undergo transition, the global control pulse generator assembles (X, Z-ATD) signals with the CSBpad signal when using them. Therefore, if the (X, Z-ATD) signals are high (t7 and t14), the global control pulse generator detects that the CSBpad signal is re-enabled in the interval. Accordingly, the global control pulse generator again provides all signals to allow normal access to the addresses X, Z. Both signals S1 and S2 start again after a certain interval (t1) from the transition of the signal CSBpad to low, and they also start after a certain interval (t8 and t15) from the time of transitions of the (X, Z-ATD) - Signals low. That is, the signal S1 is held high at the intervals t2 and t3, t5, t9 and t10, t16 and t17 and t19 while being held low in the remaining intervals. In addition, the signal S2 is held high at the intervals t2-t4, t9-t11 and t16-t18, while being kept low at the remaining intervals. The signal C1 undergoes a transition to low, where it is held, for an interval (t3, t10 and t17) of the intervals in which both S1 and S2 are high (t1-t3, t9 and t10 and t16 and t17), and it again experiences a transition to high. The signal C2 transitions from high to low at the time the signal C1 transitions low, and transitions from high to low at the time the (X, Z-ATD) signal experiences a high transition Low on high. The signal C4 undergoes a transition from high to low at a time when the signal C1 goes high, and at a time when the (x, z-ATD) signal goes high, it experiences a transition from High on low. The signal P2 undergoes a transition from low to high at a time when both signals S1 and S2 go high, and it undergoes a transition at a time when the (X, Z-ATD) signals go high Transition from low to high. The signals SAN and SAP undergo a transition to opposite states at the time the signal C2 undergoes a transition. Accordingly, the logical value 0 is written at intervals in which both signals S1 and S2 are high, that is, in the intervals t1-t3, t9 and t10 and t16 and t17 in a relevant cell, while the logic value 0 at such intervals, in which only one of the signals S1 and S2 is high, that is written in the intervals t4 and t5, t11 and t12 and t18 and t19 in a relevant cell.

The function of the global control pulse generator in the case when the cell array is the same as in 10 shown system and the address Y is switched back and forth, is such as in 33 is shown. A complete cycle of operation is divided into intervals t1 to t15 to explain the behavior of signals. This in 10 The cell array system shown does not require signals C1 and C2 because it has bit lines and bit line lines, but no reference cells. It is assumed that the signal CSBpad is deactivated from the start time of the interval t1 to the end time of the interval t14 to low and is deactivated from the start time of the interval t15 to high, and that, while this signal CSBpad is activated, the addresses X, Z does not experience a transition, but the address Y undergoes a transition at the start times of the intervals t7 and t11. Then, the signal Y-ATD is detected upon detecting a transition of the address Y, from the interval t7 to the interval t8, and from the interval t11 to Interval t12 makes a transition to high, where it is held. Signals S1 and S2 used to generate basic waveforms for the divided word lines SWL1 and SWL2 of the SWL memory cell are supplied as pulses S1 as pulses high in the intervals t2 and t3 and t5 and S2 as pulses that are high in the intervals t2-t4. The signal C4, which is a signal for controlling the signal transition between a main cell line and an external data bus and for controlling the pull-up of the main cell bit line and bit rail line, experiences a transition from low to high at the start time of the interval t4, and again goes low to low Time at which the signal CSBpad is deactivated (before the start of t15), which allows a signal transition between a main cell bit line and a data line. Since the signal P2 is made to be high in the intervals P2-P5 in which both signals S1 and S2 have normal pulses (high), it synchronizes the signals S1 and S2 to prevent them be disturbed by other signals. That is to say, in the intervals between t2 to t5 in which the signals S1 and S2 are normal, the signal P2 protects these normal signals S1 and S2 from interference by other signals at these intervals. To deactivate the precharge operation in the intervals t2-t4 and to allow a precharge operation in the remaining intervals, the signal C3 is held high until the interval t1, it changes to low at the start time of t2, and goes high again at the time to which the signal CSBpad is deactivated. The signal SAN, which is a pre-signal for generating a signal SAN_C, which is a signal for controlling NMOS transistors for driving the sense amplifier in the sense amplifier with I / O control unit, is held low and transitions at the start time High, and at the time the signal CSBpad is deactivated, transition to low. The signal SAP, an advance signal of a signal SAP_P, which controls PMOS transistors for operating the sense amplifier in the sense amplifier with I / O control unit, is opposite to the signal SAN; it is held high until the interval t2, it experiences a transition to low at the start time of t3, and it goes high again at the time the signal CSBpad is deactivated. Accordingly, at intervals in which both signals S1 and S2 are high, the logical value 0 is written into a relevant cell, ie at intervals t2 and 3. The logic value 1 becomes at intervals where only one of the signals S1 and S2 is high, ie written in the intervals t4 and t5, in a relevant cell.

The operation of the global control pulse generator in the case when the cell array corresponds to the in 10 has shown system and the addresses X, Z are switched back and forth is in 34 shown, which shows a second embodiment. Since the operation of the global control pulse generator when toggling the addresses X, Z is similar to the operation of switching the address Y to and fro, only different parts will be explained here.

While the signal Y-ATD goes high at the time when the address Y in 33 has a transition, the (X, Z-ATD) signals go high when the (X, Z-ATD) addresses in 34 to undergo a transition. The global control pulse generator assembles the (X, Z-ATD) signals with the signal CSBpad when using them at a transition of the addresses X, Z. Therefore, when the (X, Z-ATD) signals are high (t7 and t14), the global control pulse generator detects that the signal CSBpad is reactivated in the interval. Accordingly, the global control pulse generator again generates all signals to allow normal accesses to the addresses X, Z. The signals S1 and S2 are both started after a certain interval (t1) from the transition of the signal CSBpad to low, and they are also started after a certain interval (t8 and t15) from the time of transitions of the (X, Z-ATD). Signals started low. The signal C4 transitions from high to low at the time when the signal S1 goes low and the signal S2 is held high, and it goes from high to low at the time when the (X, Z-ATD) Signals go high. The signal P2 goes from low to high at the time the two signals S1 and S2 go high, and goes from high to low at the time the signals S1 and S2 go low. The signal C3 goes from high to low at the time both signals S1 and S2 go high, and goes from low to high at the time when the (X, Z-ATD) signals go high above. The signals SAN and SAP undergo a transition after a predetermined delay from the time both signals S1 and S2 are high, and go to high at the time the (X, Z-ATD) signals go high, in the opposite states. Accordingly, in the intervals where both signals S1 and S2 are high, the logical value 0 is written in a relevant cell, that is, in the intervals t2 and t3, t9 and t10, and t16 and t17. In addition, the logical value 1 is written in those relevant intervals in which only one of the signals S1 and S2 is high, that is, in the intervals t4 and t5, t11 and t12, and t18 and t19.

The ferroelectric SWL memory of the present invention and the circuit for driving the same have the following advantages.

Firstly, attaching subdivided wordlines that perform the function of plate lines such that they are lacking, improvements in packing density and memory efficiency facilitate the need for a separate plate line control signal in reading and writing.

Second, interference of the reference cells can be prevented since the ratio of reference cells to corresponding main cells in the invention is significantly lower than in the prior art. This deterioration occurs in the prior art because of the difficulty of the ferroelectric substance and the use of a reference cell in readings for a few hundred main cells, so that each reference cell is heavily stressed, resulting in a rapid deterioration of the ferroelectric properties of the ferroelectric ones present in it Substance leads.

Third, the use of signals X, Y, Z-ATD, in addition to the signal CSBpad commonly used to activate a ferroelectric memory, facilitates the chip function in fast column access mode, allowing for improved chip access speed, along with efficient management of memory operation. That is, the chip can be operated in cases where essentially only the addresses X, Z undergo transition or only the address Y undergoes a transition, the chip operating in terms of interactions between addresses X, Y and Z is protected when the chip is activated by the signal CSBpad. In addition, when only the addresses X, Z undergo transition, the same operation as when the chip is activated by the signal CSBpad can be realized by using a (X, Z-ATD) signal, since valid data is not yet stored in the sense amplifier. and when only the address Y undergoes a transition, a data already stored in the sense amplifier can be read because the divided word lines SWL1 and SWL2 do not undergo transition for the row address, and in a write mode, normal writing can be performed using the signal Y-ATD ,

Claims (34)

Circuit for driving a ferroelectric SWL memory, comprising: - an X-post decoder ( 21 ) for receiving and decoding addresses X and Z for activating a cell array block ( 23 ); A global control pulse generator ( 16 ) for providing a control pulse required for writing or reading data in response to an externally received signal CSBpad; A local control pulse generator ( 20 ) for receiving the control pulse from the global control pulse generator ( 16 ) and to provide a control signal as required for writing and reading data; A SWL cell array block ( 23 ) for storing data; - a SWL driver ( 22 ) for driving the SWL cell array block ( 23 ) on control signals from the X-post decoder ( 21 ) and local control pulse generator ( 20 ); A Y address decoder ( 18 ) for decoding an externally received signal for addresses Y; A column control unit ( 24 ) for controlling columns on the control signal from the local control pulse generator ( 20 ) and a decoded signal from the Y address decoder ( 18 ); and - a sense amplifier with I / O control unit ( 25 ) for reading / recording data from / in the SWL cell array block ( 23 ), wherein the SWL cell array block ( 23 ) - a plurality of pairs of divided word lines (SWL1, SWL2) arranged in a fixed interval direction, and - a plurality of pairs of bit lines (bit_n; Rbit_n; B_n, BB_n) in a direction orthogonal to the divided ones Word lines (SWL1, SWL2) are arranged at fixed intervals, and - has ferroelectric unit memory cells which - each between two adjacent divided word lines (SWL1, SWL2) of a word line pair and between two adjacent bit lines (Bit_n, Bit_n + 1; RBit_n, RBit_n + 1 B_n, BB_n) of a bit line pair are arranged, and - a first transistor whose gate electrode is connected to a first divided word line (SWL1) and whose source electrode is connected to a first bit line (Bit_n; RBit_n; B_n), - a second transistor whose Gate electrode having a second divided word line (SWL2) and its source electrode having a second bit line (Bit_n + 1; RBit_n +1; BB_n), a first capacitor whose first electrode is connected to the drain electrode of the first transistor and whose second electrode is connected to the second divided word line (SWL2), and a second capacitor whose first electrode is connected to the drain electrode of the second transistor and the second electrode thereof is connected to the first divided word line (SWL1). Circuit according to Claim 1, characterized in that the global control pulse generator ( 16 ) Comprises: - a receive buffer ( 31 ) for receiving signals including an external signal CSBpad and for providing a first and a second synchronizing signal; A low-voltage operation and interference signal removal device ( 32 ) for receiving the first synchronizing signal from the receiving buffer ( 31 and a feedback signal thereof and for providing a low-voltage detection signal for preventing operation at a low voltage and a disturbance elimination signal for filtering noise from the first synchronizing signal; A first control unit ( 33 ) for receiving a signal having noise removed thereon and for providing a first control signal for controlling the activation timing of the sense amplifier, a second control signal for controlling the activation timing for column selection and controlling the pull up of a reference cell bitline, and a third control signal for providing a signal for the SWL driver ( 22 ) and other control signals when the normal supply voltage from the low voltage operation and interference signal eliminator ( 32 ) is delivered; A second control unit ( 34 ) for receiving the third control signal from the first control unit ( 33 ) for generating a first divided word line basic signal waveform generation signal S1 and a second divided word line basic waveform generating signal S2 in a pair of divided word lines SWL1, SWL2 for the SWL driver 22 ), a fourth control signal which is a basic pulse signal for controlling the activation time periods of the signals S1 and S2, and a pulse signal P2 having a driving capability improved over that of the fourth control signal and for supplying the fourth control signal to the low-voltage operation and interference signal removing means (Fig. 32 ) as the feedback signal and the pulse signal P2 to the local control pulse generator ( 20 ); A third control unit ( 35 ) for receiving the first and the second synchronizing signal from the receiving buffer ( 31 ) and the fourth control signal from the second control unit ( 34 ) and for providing a fifth control signal for controlling synchronism with the signal CSBpad when all the signals except the first divided word line basic waveform generating signal S1 and the second divided word line basic waveform generating signal S2 are deactivated , and a sixth control signal for interrupting the deactivated state of the signal CSBpad when it has been deactivated in the state in which the first divided word line basic waveform generation signal S1 and the second divided word line basic waveform generation signal S2 (SWL2) and maintaining the activated state until the completion of the normal operations of the first divided word line basic waveform generating signal S1 and the second divided word line basic waveform generating signal S2, and SWL2; and a fourth control unit ( 36 ) for receiving the fifth and sixth control signals from the third control unit ( 35 ) and the first, second and third control signals from the first control unit ( 33 ) and for providing an enable signal SAN for an NMOS device and an enable signal SAP for a PMOS device in the sense amplifier, a control signal C1 for connecting a bit line to a main cell block and a first I / O node at the sense amplifier to each other, a control signal C2 to Connecting a bit line to a reference cell block and a second I / O node to the sense amplifier with each other, a control signal C3 for controlling low voltage precharge operations of a bit line at a main cell, a bit line at a reference cell and a node at the sense amplifier, and a control signal C4 for controlling the activation time for the column selection and the pulling up of the bit line of a reference cell. Circuit according to Claim 1, characterized in that the global control pulse generator ( 16 ) Provides the following when the activation period of the externally received signal CSBpad is divided into intervals t1-t14: a first basic waveform generation signal S1 for a SWL held high in the intervals t2 and t3 and in the interval t5 while kept low in the remaining intervals; A second basic signal waveform generation signal S2 for a SWL held high in the intervals t2-t4 while being kept low in the remaining intervals; A control signal C1 which goes low at the interval t3 and is held high in the remaining intervals to connect a bit line to a main cell and a first node to the sense amplifier; A control signal C2 held low at intervals t3-t14 and held high in the remaining intervals to connect a bit line to a reference cell and a second node to the sense amplifier; A control signal C4 held high at intervals t4-t14 and kept low in the remaining intervals to control the activation timing for column selection and pull-up of a reference cell bit line; A pulse signal P2 maintained high at intervals t2-t5 and kept low in the remaining intervals to control activation timings for the first and second basic waveform generation signals S1 and S2, respectively; A control signal C3 maintained low at intervals t2-t14 and held high in the remaining intervals to control the low voltage precharge of a main cell bitline, a reference cell bitline, and a sense amplifier node; A first activation signal SAP for the sense amplifier, which is held high in intervals t3-t14 and low in the remaining intervals; and a second sense signal SAN for the sense amplifier which is held low at intervals t3-t14 and high at the remaining intervals. Circuit according to Claim 1, characterized in that the global control pulse generator ( 16 ), when the activation period of the externally received signal CSBpad is divided into intervals t1-t20 and address signals for X, Z undergo transition at the start timings of the intervals t7 and t14, provides: a first basic waveform generation signal S1 for a SWL which is kept high in the intervals t2 and t3, t5, t9 and t10, t12, t16 and t17 and t19 and low in the remaining intervals; A second basic signal waveform generation signal S2 for a SWL which is held high in the intervals t2-t4, t9-t11 and t16-t18 and low in the remaining intervals; A control signal C1 held low at intervals t3, t10 and t17 and high at the remaining intervals to connect a bit line to a main cell and a first node to the sense amplifier; A control signal C2 transitioning from high to low at the end timings of the intervals t2, t10 and t17 and transitioning from low to high at the start times t7 and t14 to connect a bit line to a reference cell and a first node to the sense amplifier; A control signal C4 held high at intervals t4-t6, t11-t13, and t18-t20 and held high in the remaining intervals to control an activation timing for column selection and pull-up of a reference cell bit line; A pulse signal P2 held high at intervals t2-t5, t9-t12 and t16-t19 and low at the remaining intervals to control activation time periods of the first and second basic waveform generation signals S1 and S2, respectively; A control signal C3 kept low at intervals t2-t6, t9-t13 and t16-t20 and high in the remaining intervals to control a low-voltage precharge operation of a main cell bit line, a reference cell bit line and a sense amplifier node; A first activation signal SAP for the sense amplifier which is kept high in intervals t3-t6, t10-t13 and t17-t20 and low in the remaining intervals; and a second sense signal SAN for the sense amplifier which is held low at intervals t3-t6, t10-t13 and t17-t20 and high at the remaining intervals. Circuit according to Claim 1, characterized in that the global control pulse generator ( 16 ) Comprises: - a receive buffer ( 31 ) for receiving signals including an external signal CSBpad and for providing first and second synchronizing signals; A first control unit ( 33 ) for receiving the first synchronizing signal from the receiving buffer ( 31 and providing a first control signal for controlling an activation timing of the sense amplifier, a second control signal for controlling an enable timing for column selection, and for controlling pull-up of a reference cell bitline, and a third control signal for providing a signal to the SWL driver ( 22 ) as well as other control signals; A second control unit ( 34 ) for receiving the third control signal from the first control unit ( 33 ) for generating a first divided word line basic signal waveform generation signal S1 and a second divided word line basic waveform generating signal S2 in a pair of divided word lines SWL1, SWL2 for the SWL driver 22 ), a fourth control signal which is a basic pulse signal for controlling the activation time periods of the signals S1 and S2, and a pulse signal P2 having a driving capability improved from that of the fourth control signal and for supplying the pulse signal P2 to the local control pulse generator (FIG. 20 ); A third control unit ( 35 ) for receiving the first and the second synchronizing signal from the receiving buffer ( 31 ) and the fourth control signal from the second control unit ( 34 ) and for providing a fourth control signal for controlling synchronism with the signal CSBpad when all the signals except the basic waveform generation signal S1 for the first divided second word line (SWL1) and the basic signal waveform generation signal S2 for the second divided word line (SWL2) are disabled, and a sixth control signal for interrupting a deactivated state of the signal CSBpad when it is deactivated in the state in which the basic waveform generation signal S1 for the first divided word line (SWL1) and the second divided word line basic waveform generation signal S2 are activated, and maintaining the activated state until completion of normal operations of the first divided word line basic signal waveform generation signal S1 and the first divided word line (SWL1) Basic signal waveform generation signal S2 for the second divided word line (SWL2); and a fourth control unit ( 36 ) for receiving the fifth and sixth control signals from the third control unit ( 35 ), the first, second and third control signals from the first control unit ( 33 ) and the first sync signal from the receive buffer ( 31 ) and for supplying an activation signal SAN for an NMOS device and an activation signal SAP for a PMOS device in the sense amplifier, a control signal C1 for connecting a bit line to a main cell block and a first I / O node at the sense amplifier to each other, a control signal C2 to Connecting a bit line to a reference cell block and a second I / O node to the sense amplifier with each other, a control signal C3 for controlling low voltage precharge operations of a bit line at a main cell, a bit line at a reference cell and a node at the sense amplifier, and a control signal C4 for controlling the activation time for the column selection and for controlling the pull-up of the bit line of a reference cell. Circuit for driving a ferroelectric SWL memory, comprising: X, Y, Z buffers ( 11 . 17 . 13 ) for buffering each of externally received signals for addresses X, Y and Z; X, Y, Z predecoders ( 12 . 17 . 14 ) for predecoding respective addresses X, Y, Z from the X, Y, Z buffers ( 11 . 17 . 13 ); An X-post decoder ( 21 ) for receiving and predecoding the addresses X and Z from the X, Y, Z predecoders ( 12 . 17 . 14 ) activating activation of a cell array block ( 23 ); A global control pulse generator ( 16 ) for providing a control pulse required for writing or reading data in response to an externally received signal CSBpad; A local control pulse generator ( 20 ) for generating a control signal on the control pulse from the global control pulse generator ( 16 ); A SWL cell array block ( 23 ) for storing data; - a SWL driver ( 22 ) for driving the SWL cell array block ( 23 ) on control signals from the X-post decoder ( 21 ) and local control pulse generator ( 20 ); A column control unit ( 24 ) for controlling columns on the control signal from the local control pulse generator ( 20 ) and a Y predecode signal from the X, Y, Z predecoders ( 12 . 17 . 14 ); and - a sense amplifier with I / O control unit ( 25 ) for acquiring / recording data from / in the SWL cell array block ( 23 ) to the control signal from the local control pulse generator ( 20 ), under the control of the column control unit ( 24 ), wherein the SWL cell array block ( 23 ) - a plurality of pairs of divided word lines (SWL1, SWL2) arranged in a fixed interval direction, and - a plurality of pairs of bit lines (bit n; RBit_n; B_n, BB_n) oriented in a direction orthogonal to the are arranged at fixed intervals, and - comprise ferroelectric unit memory cells, each between two adjacent divided word lines (SWL1, SWL2) of a word line pair and between two adjacent bit lines (Bit_n, Bit_n + 1; RBit_n, RBit_n + 1, B_n, BB_n) of a bit line pair, and the - a first transistor whose gate electrode is connected to a first divided word line (SWL1) and whose source electrode is connected to a first bit line (Bit_n; RBit_n; B_n), - a second transistor, its gate electrode having a second divided word line (SWL2) and its source electrode having a second bit line (Bit_n + 1; RBit_n +1; BB_n), a first capacitor whose first electrode is connected to the drain electrode of the first transistor and whose second electrode is connected to the second divided word line (SWL2), and a second capacitor whose first electrode is connected to the drain electrode of the second transistor and the second electrode thereof is connected to the first divided word line (SWL1). Circuit according to Claim 6, characterized in that the global control pulse generator ( 16 ) Comprises: - a receive buffer ( 31 ) for receiving signals including an external signal CSBpad and for providing first and second synchronizing signals; A low-voltage operation and interference signal removal device ( 32 ) for receiving the first synchronizing signal from the receiving buffer ( 31 and a feedback signal thereof and for providing a low-voltage detection signal for preventing operation at a low voltage and a disturbance elimination signal for filtering noise from the first synchronizing signal; A first control unit ( 33 ) for receiving a signal having noise removed thereon and for providing a first control signal for controlling the activation timing of the sense amplifier, a second control signal for controlling the activation timing for column selection and controlling the pull up of a reference cell bitline, and a third control signal for providing a signal for the SWL driver ( 22 ) and other control signals when the normal supply voltage from the low voltage operation and interference signal eliminator ( 32 ) is delivered; A second control unit ( 34 ) for receiving the third control signal from the first control unit ( 33 ) for generating a first divided word line basic signal waveform generation signal S1 and a second divided word line basic waveform generating signal S2 in a pair of divided word lines SWL1, SWL2 for the SWL driver 22 ), a fourth control signal which is a basic pulse signal for controlling the activation time periods of the signals S1 and S2, and a pulse signal P2 having a driving capability improved over that of the fourth control signal and for supplying the fourth control signal to the low-voltage operation and interference signal removing means (Fig. 32 ) as the feedback signal and the pulse signal P2 to the local control pulse generator ( 20 ); A third control unit ( 35 ) for receiving the first and the second synchronizing signal from the receiving buffer ( 31 ) and the fourth control signal from the second control unit ( 34 ) and for providing a fifth control signal for controlling synchronism with the signal CSBpad when all the signals except the basic waveform generation signal S1 for the first divided sixth word line (SWL1) and the basic signal waveform generation signal S2 for the second divided word line (SWL2) are disabled, and a sixth control signal for interrupting the deactivated state of the signal CSBpad, if it has been deactivated in the state in which the basic waveform generation signal S1 for the first divided word line (SWL1) and the second divided word line basic waveform generation signal S2 (SWL2) are activated, and maintaining the activated state until completion of the normal operations of the first divided word line basic signal waveform generation signal S1 and SWL1 the basic signal waveform generation signal S2 for the second divided word line (SWL2); and a fourth control unit ( 36 ) for receiving the fifth and sixth control signals from the third control unit ( 35 ) and the first, second and third control signals from the first control unit ( 33 ) and for providing an enable signal SAN for an NMOS device and an enable signal SAP for a PMOS device in the sense amplifier, a control signal C1 for connecting a bit line to a main cell block and a first I / O node at the sense amplifier to each other, a control signal C2 to Connecting a bit line to a reference cell block and a second I / O node to the sense amplifier with each other, a control signal C3 for controlling low voltage precharge operations of a bit line at a main cell, a bit line at a reference cell and a node at the sense amplifier, and a control signal C4 for controlling the activation time for the column selection and the pulling up of the bit line of a reference cell. Circuit according to Claim 6, characterized in that the global control pulse generator ( 16 ) Comprises: - a receive buffer ( 31 ) for receiving signals including an external signal CSBpad and for providing first and second synchronizing signals; A first control unit ( 33 ) for receiving the first synchronizing signal from the receiving buffer ( 31 and providing a first control signal for controlling an activation timing of the sense amplifier, a second control signal for controlling an enable timing for column selection, and for controlling pull-up of a reference cell bitline, and a third control signal for providing a signal to the SWL driver ( 22 ) as well as other control signals; A second control unit ( 34 ) for receiving the third control signal from the first control unit ( 33 ) for generating a first divided word line basic signal waveform generation signal S1 and a second divided word line basic waveform generating signal S2 in a pair of divided word lines SWL1, SWL2 for the SWL driver 22 ), a fourth control signal which is a basic pulse signal for controlling the activation time periods of the signals S1 and S2, and a pulse signal P2 having a driving capability improved from that of the fourth control signal and for supplying the pulse signal P2 to the local control pulse generator (FIG. 20 ); A third control unit ( 35 ) for receiving the first and the second synchronizing signal from the receiving buffer ( 31 ) and the fourth control signal from the second control unit ( 34 and supplying a fourth control signal for controlling synchronism with the signal CSBpad when all the signals except the first divided word line basic waveform generation signal S1 and the second divided word line basic waveform generation signal S2 are deactivated , and a sixth control signal for interrupting a deactivated state of the signal CSBpad when it is deactivated in the state in which the first divided word line basic waveform generation signal S1 and the second divided word line basic waveform generation signal S2 (SWL2) and maintaining the activated state until the completion of normal operations of the first divided word line basic signal waveform generation signal S1 and the second divided word line basic waveform generation signal S2, and SWL2; and a fourth control unit ( 36 ) for receiving the fifth and sixth control signals from the third control unit ( 35 ), the first, second and third control signals from the first control unit ( 33 ) and the first sync signal from the receive buffer ( 31 ) and for supplying an activation signal SAN for an NMOS device and an activation signal SAP for a PMOS device in the sense amplifier, a control signal C1 for connecting a bit line to a main cell block and a first I / O node at the sense amplifier to each other, a control signal C2 to Connecting a bit line to a reference cell block and a second I / O node to the sense amplifier with each other, a control signal C3 for controlling low voltage precharge operations of a bit line at a main cell, a bit line at a reference cell and a node at the sense amplifier, and a control signal C4 for controlling the activation time for the column selection and for controlling the pull-up of the bit line of a reference cell. Circuit according to Claim 6, characterized in that the global control pulse generator ( 16 ) Provides the following when the activation period of the externally received signal CSBpad is divided into intervals t1-t14: a first basic waveform generation signal S1 for a SWL held high in the intervals t2 and t3 and in the interval t5 while kept low in the remaining intervals; A second basic signal waveform generation signal S2 for a SWL held high in the intervals t2-t4 while being kept low in the remaining intervals; A control signal C1 which goes low at the interval t3 and is held high in the remaining intervals to connect a bit line to a main cell and a first node to the sense amplifier; A control signal C2 held low at intervals t3-t14 and held high in the remaining intervals to connect a bit line to a reference cell and a second node to the sense amplifier; A control signal C4 held high at intervals t4-t14 and kept low in the remaining intervals to control the activation timing for column selection and pull-up of a reference cell bit line; A pulse signal P2 maintained high at intervals t2-t5 and kept low in the remaining intervals to control activation timings for the first and second basic waveform generation signals S1 and 52, respectively; A control signal C3 maintained low at intervals t2-t14 and held high in the remaining intervals to control the low voltage precharge of a main cell bitline, a reference cell bitline, and a sense amplifier node; A first activation signal SAP for the sense amplifier, which is held high in intervals t3-t14 and low in the remaining intervals; and a second sense signal SAN for the sense amplifier which is held low at intervals t3-t14 and high at the remaining intervals. Circuit for driving a ferroelectric SWL memory, comprising: - an SWL cell array block ( 23 ) for storing data; A receive buffer ( 31 ) for receiving signals including a signal CSBpad and for providing a first and a second synchronizing signal; A first control unit ( 33 ) for receiving the first synchronizing signal from the receiving buffer ( 31 and supplying a first control signal for controlling the activation timing of the sense amplifier, a second control signal for controlling the activation timing for the column selection and for controlling the pull-up of a reference cell bit line, and a third control signal for providing a signal for a SWL driver ( 22 ) for driving the SWL cell array block ( 23 ); A second control unit ( 34 ) for receiving the third control signal from the first control unit ( 33 ) for generating a first divided word line basic signal waveform generation signal S1 and a second divided word line basic signal waveform generation signal S2 in a pair of divided word lines SWL1, SWL2 for the SWL driver (FIG. 22 ), a fourth control signal which is a basic pulse signal for controlling the activation time periods of the signals S1 and S2, and a pulse signal P2 having a driving capability improved from that of the fourth control signal and for supplying the pulse signal P2 to the local control pulse generator (FIG. 20 ); A third control unit ( 35 ) for receiving the first and second synchronizing signals from the receiving buffer ( 31 ) and the fourth control signal from the second control unit ( 34 ) and for providing a fifth control signal for controlling synchronism with the signal CSBpad when all the signals except the first divided word line basic waveform generating signal S1 and the second divided word line basic waveform generating signal S2 are deactivated , and a sixth control signal for interrupting a deactivated state of the signal CSBpad when it is deactivated in the state where the first divided word line basic waveform generation signal S1 and the second divided word line basic waveform generation signal S2 are activated and maintaining the activated state until the completion of normal operations of the first divided word line basic waveform generating signal S1 and the second divided word line basic waveform generating signal S2 (SWL2); and a fourth control unit ( 36 ) for receiving the fifth and sixth control signals from the third control unit ( 35 ), the first, second and third control signals from the first control unit ( 33 ) and the first sync signal from the receive buffer ( 31 ) and for supplying an activation signal SAN for an NMOS device and an activation signal SAP for a PMOS device in the sense amplifier, a control signal C1 for connecting a bit line to a main cell block and a first I / O node at the sense amplifier with each other, a control signal C2 mm Connecting a bit line to a reference cell block and a second I / O node to the sense amplifier with each other, a control signal C3 for controlling a low voltage precharge of a bit line at a main cell, a bit line at a reference cell and a node at the sense amplifier, and a control signal C4 for controlling the activation time for the column selection and the pulling up of the bit line of a reference cell, wherein the SWL cell array block ( 23 ) - a plurality of pairs of divided word lines (SWL1, SWL2) arranged in a fixed interval direction, and - a plurality of pairs of bit lines (bit_n; Rbit_n; B_n, BB_n) in a direction orthogonal to the divided ones Word lines (SWL1, SWL2) are arranged at fixed intervals, and - has ferroelectric unit memory cells which - each between two adjacent divided word lines (SWL1, SWL2) of a word line pair and between two adjacent bit lines (Bit_n, Bit_n + 1; RBit_n, RBit_n + 1 B_n, BB_n) of a bit line pair are arranged, and - a first transistor whose gate electrode is connected to a first divided word line (SWL1) and whose source electrode is connected to a first bit line (Bit_n; RBit_n; B_n), - a second transistor whose Gate electrode having a second divided word line (SWL2) and its source electrode having a second bit line (Bit_n + 1; RBit_n +1; BB_n), a first capacitor whose first electrode is connected to the drain electrode of the first transistor and whose second electrode is connected to the second divided word line (SWL2), and a second capacitor whose first electrode is connected to the drain electrode of the second transistor and the second electrode thereof is connected to the first divided word line (SWL1). Circuit according to Claim 10, characterized in that the receiving buffer ( 31 ) applies the externally received signal CSBpad to an inversion and a non-inversion to produce the first and second sync signals, respectively. Circuit according to Claim 10, characterized in that the receiving buffer ( 31 ) Includes: a voltage turn-on detector ( 44 ) for detecting a voltage turn-on signal of a power supply; A first NOR gate ( 45 ) to subject the externally received signal CSBpad and the power-on detection signal to logic operation; A first inverter ( 46 ) for inverting the output signal of the first NOR gate ( 45 ) to generate the second synchronizing signal; and - a second inverter ( 47 ) for inverting the output signal of the first inverter ( 46 ) to generate the first synchronizing signal. Circuit according to Claim 10, characterized in that the receiving buffer ( 31 ) Includes: - a second NOR gate ( 45 ) to subject the externally received signal CSBpad and (X, Z-ATD) signals to logic operation; A third inverter ( 46 ) for inverting the output signal of the second NOR gate ( 45 ) to provide the second synchronizing signal; and - a fourth inverter ( 47 ) for inverting the output signal of the third inverter ( 46 ) to deliver the first synchronizing signal. Circuit according to Claim 10, characterized in that the receiving buffer ( 31 ) Includes: - a third NOR gate ( 45 ) to subject (X, Z-ATD) signals, the signal CSBpad and a power-on detection signal, all of which are received from the outside, to a logic operation; A fifth inverter ( 46 ) for inverting the output signal of the third NOR gate ( 45 ) to provide the second synchronizing signal; and - a sixth inverter ( 47 ) for inverting the output signal of the fifth inverter ( 46 ) to deliver the first synchronizing signal. Circuit according to Claim 10, characterized in that the voltage turn-on detector ( 44 ) Includes: A supply voltage rise detector ( 233 ) for detecting an increase in the supply voltage; - an amplifier ( 234 ) for comparing and amplifying the output signal from the supply voltage increase detector ( 233 ) and the supply voltage; A feedback part ( 235 ) for feeding back the output signal of the amplifier ( 234 ) for providing a signal representing the stability of the supply voltage; and - a power-on forwarding device ( 236 ) for improving the driving capability of the output signal of the feedback part (FIG. 235 ) for delivery to the receive buffer ( 31 ). Circuit according to Claim 10, characterized in that the first control unit ( 33 ) Includes: - a first delay unit ( 104 ) for providing a first and a second signal obtained by dividing the first synchronizing signal from the receiving buffer ( 31 ) having mutually different values, and delaying and propagating the first delayed signal as a first control signal; A seventh inverter ( 101 ) for inverting the second delay signal from the first delay unit ( 104 ); A first NAND gate ( 102 ) to receive the first sync signal from the receive buffer ( 31 ) and the signal from the seventh inverter ( 101 ) to perform a logic operation to provide the second control signal; and - an eighth inverter ( 103 ) for inverting the output signal of the first NAND gate ( 102 ) to provide the third control signal. Circuit according to Claim 10, characterized in that the second control unit ( 34 ) Includes: - a second delay unit ( 148 ) for providing a third and a fourth delay signal which the third control signal from the first control unit ( 33 ) whose falling edge is divided and delayed by different values; A fourth NOR gate ( 121 ), the fourth delay signal from the second delay unit ( 148 ) and the third control signal from the first control unit ( 33 ) to undergo a logic operation; A third delay unit ( 149 ) for delaying the rising edge of the signal from the fourth NOR gate ( 121 ) for a predetermined period of time; A ninth inverter ( 132 ) for inverting the third control signal; A second NAND gate ( 133 ), the output signals of the ninth inverter ( 132 ), the fourth NOR gate ( 121 ) and the third delay unit ( 149 ) to perform a logical operation to provide a fourth control signal; A third NAND gate ( 134 ), the output signal of the ninth inverter ( 132 ), the fourth delay signal from the second delay unit ( 148 ) and the output signal of the second NAND gate ( 133 ) to undergo a logic operation; A fourth delay unit ( 150 ) for delaying the rising edge of the output signal of the third NAND gate ( 134 ) by a predetermined period of time; A fourth NAND gate ( 141 ) for the third delay signal from the second delay unit ( 148 ), the output signal of the third NAND gate ( 134 ) and the output signal of the second NAND gate ( 133 ); - a fifth delay unit ( 151 ) for delaying the rising edge of the output signal of the fourth NAND gate ( 141 ) for a predetermined period of time; A forwarding unit for the signal S1 ( 237 ), the output signal of the fourth delay unit ( 150 ) and the output signal of the second NAND gate ( 133 ) to pass a logical operation to pass the basic waveform propagation signal S1 for the first divided word line (SWL1); A forwarding unit for the signal S2 ( 238 ), the output signal of the fifth delay unit ( 151 ) and the output signal of the second NAND gate ( 133 ) to carry out a logic operation to pass the basic signal waveform generation signal S2 for the second divided word line (SWL2); and - a pulse signal forwarding unit ( 152 ) for improving the drive capability of the signal from the second NAND gate ( 133 ) for forwarding a pulse signal P2. Circuit according to Claim 17, characterized in that the second delay unit ( 148 The following includes: a plurality of inverters for reducing the current driving capability of a PMOS transistor and improving the current drive capability of an NMOS transistor in the sense amplifier, and a plurality of inverters for improving the current driving capability of the PMOS and NMOS transistors. Circuit according to Claim 17, characterized in that the third delay unit ( 149 The following includes: a plurality of inverters for reducing the current driving capability of a PMOS transistor and improving the current drive capability of an NMOS transistor in the sense amplifier, and a plurality of inverters for improving the current driving capability of the PMOS and NMOS transistors. Circuit according to Claim 10, characterized in that the third control unit ( 35 ) Includes: - a signal extension unit ( 172 ) for receiving the first synchronizing signal from the receiving buffer ( 31 ) and the fourth control signal from the second control unit ( 34 ) and for prolonging the high pulse of the pulse signal P2 from the second control unit ( 34 ) until a time when the signal CSBpad is held low; A seventh delay unit ( 173 ) for delaying the rising edge of the signal from the signal extension unit ( 172 ) by a predetermined period of time; - a fifth NAND gate ( 171 ) to the inverted fourth control signal from the second control unit ( 34 ) and the second synchronizing signal from the receiving buffer ( 31 ) to perform a logic operation to provide the sixth control signal; and a control signal forwarding unit ( 174 ), the outputs of the sixth delay unit and the fifth NAND gate ( 171 ) to perform a logic operation to provide the fifth control signal. Circuit according to Claim 10, characterized in that the third control unit ( 35 ) Includes: - a seventh delay unit ( 173 ) for delaying the rising edge of the fourth control signal from the second control unit ( 34 ) for a predetermined period of time; A sixth NAND gate ( 171 ) to the inverted fourth control signal from the second control unit ( 34 ) and the second synchronizing signal from the receiving buffer ( 31 ) to perform a logic operation to provide the sixth control signal; and a control signal forwarding unit ( 174 ), the output signals of the seventh delay unit ( 173 ) and the sixth NAND gate ( 171 ) to perform a logic operation to provide the fifth control signal. Circuit according to Claim 10, characterized in that the third control unit ( 35 ) Includes: - a signal extension unit ( 172 ) for receiving the first synchronizing signal from the receiving buffer ( 31 ) and the fourth control signal from the second control unit ( 34 ) and for prolonging the high pulse of the pulse signal P2 from the second control unit ( 34 ) until the time CSBpad is held low; An eighth delay unit ( 173 ) for delaying the rising edge and the falling edge of the signal from the signal extension unit ( 172 ) by predetermined time periods; A seventh NAND gate ( 171 ) to the inverted fourth control signal from the second control unit ( 34 ) and the second synchronizing signal from the receiving buffer ( 31 ) to perform a logic operation to provide the sixth control signal; and a control signal forwarding unit ( 174 ), the outputs of the eighth delay unit ( 173 ) and the fifth NAND gate ( 171 ) to perform a logic operation to provide the fifth control signal. Circuit according to Claim 10, characterized in that the fourth control unit ( 36 ) Comprises: - a sense amplifier control signal forwarding unit ( 199 ) to receive the first control signal from the first control unit ( 33 ) and the fifth control signal from the third control unit ( 35 ) to perform a logic operation to provide an enable signal SAN for the NMOS device in the sense amplifier and an enable signal SAP for the PMOS device in the sense amplifier; A bit line switching signal forwarding unit ( 200 ) to receive the third control signal from the first control unit ( 33 ) and the fifth control signal from the third control unit ( 35 ) to provide a logic operation to provide a control signal C1 for connecting a bit line in a main cell block and a first I / O node to the sense amplifier, and a control signal C2 for connecting a bit line in a reference cell block and a second I / O node to the sense amplifier ; A column control signal forwarding unit ( 201 ) to receive the second control signal from the first control unit ( 33 ) and the fifth control signal from the third control unit ( 35 ) to provide a logic operation to provide a signal C4 which is a column control signal; and - a precharge control signal forwarding unit ( 202 ) to receive the first sync signal from the receive buffer ( 31 ) or the sixth control signal from the third control unit ( 35 ) to provide a logic operation to provide a precharge control signal C3. Circuit according to Claim 23, characterized in that the bit line switching signal forwarding unit ( 200 ) the third control signal from the first control unit ( 33 ) and the fifth control signal from the third control unit ( 35 ) performs a logic operation to provide a control signal C1 for connecting a bit line and a first I / O node to the sense amplifier and a control signal C2 for connecting a bit line and a second I / O node to the sense amplifier. Circuit for driving a ferroelectric SWL memory, comprising: - an SWL cell array block ( 23 ) for storing data; A receive buffer ( 31 ) for receiving signals including an external signal CSBpad and for providing first and second synchronizing signals; A low-voltage operation and interference signal removal device ( 32 ) for receiving the first synchronizing signal from the receiving buffer ( 31 and a feedback signal thereof and for providing a low-voltage detection signal for preventing operation at a low voltage and a disturbance elimination signal for filtering noise from the first synchronizing signal; A first control unit ( 33 and receiving a first control signal for controlling the activation timing of the sense amplifier, a second control signal for controlling the activation timing for column selection, and pulling up a reference cell bitline, and a third control signal for providing a signal for one SWL driver ( 22 ) for driving the SWL cell array block ( 23 ), when the low-voltage operation and interference signal removal device ( 32 ) the normal supply voltage is supplied; A second control unit ( 34 ) for receiving the third control signal from the first control unit ( 33 ) for generating a basic signal waveform generation signal S1 for a first divided word line (SWL1) and a basic signal waveform generation signal S2 for a second divided word line (SWL2) in a pair of divided word lines (SWL1, SWL2) of the SWL driver ( 22 ), a fourth control signal, which is a basic pulse signal for controlling the activation time periods of the signals S1 and 52, and a pulse signal P2 having a driving capability improved over that of the fourth control signal, and for supplying the fourth control signal to the low-voltage operation and interference signal removing means (Fig. 32 ) as a feedback signal and the pulse signal P2 to a local control pulse generator ( 20 ); A third control unit ( 35 ) for receiving the first and second synchronizing signals from the receiving buffer ( 31 ) and the fourth control signal from the second control unit ( 34 ) and for providing a fifth control signal for controlling synchronism with the signal CSBpad when all the signals except the first divided word line basic waveform generating signal S1 and the second divided word line basic waveform generating signal S2 are deactivated and a sixth control signal for interrupting the deactivated state of the signal CSBpad when it is deactivated in the state where the first divided word line basic waveform generation signal S1 and the second divided word line basic waveform generation signal S2 are SWL2. and maintaining the activated state until the completion of the normal operations of the first divided word line basic waveform generating signal S1 and the second divided word line basic waveform generating signal S2, and SWL2; and a fourth control unit ( 36 ) for receiving the fifth and sixth control signals from the third control unit ( 35 ) and the first, second and third control signals from the first control unit ( 33 ) and supply an activation signal SAN for an NMOS device and an activation signal SAP for a PMOS device in the sense amplifier, a control signal C1 for connecting a bit line to a main cell block and a first I / O node at the sense amplifier with each other, a control signal C2 to Connecting a bit line to a reference cell block and a second I / O node to the sense amplifier with each other, a control signal C3 for controlling low voltage precharge operations of a bit line at a main cell, a bit line at a reference cell and a node at the sense amplifier, and a control signal C4 for controlling the Activation timing of a column selection operation and pulling up the bit line of a reference cell, wherein the SWL cell array block ( 23 ) - a plurality of pairs of divided word lines (SWL1, SWL2) arranged in a fixed interval direction, and - a plurality of pairs of bit lines (bit_n; Rbit_n; B_n, BB_n) in a direction orthogonal to the divided ones Word lines (SWL1, SWL2) are arranged at fixed intervals, and - has ferroelectric unit memory cells which - each between two adjacent divided word lines (SWL1, SWL2) of a word line pair and between two adjacent bit lines (Bit_n, Bit_n + 1; RBit_n, RBit_n + 1 B_n, BB_n) of a bit line pair are arranged, and - a first transistor whose gate electrode is connected to a first divided word line (SWL1) and whose source electrode is connected to a first bit line (Bit_n; RBit_n; B_n), - a second transistor whose Gate electrode having a second divided word line (SWL2) and its source electrode having a second bit line (Bit_n + 1; RBit_n +1; BB_n), - a first capacitor whose first electrode is connected to the drain electrode of the first transistor and whose second electrode is connected to the second divided word line (SWL2), and - Have a second capacitor whose first electrode is connected to the drain electrode of the second transistor and the second electrode to the first divided word line (SWL1). Circuit according to Claim 25, characterized in that the low-voltage operation and interference signal removal device ( 32 ) Includes: - a low voltage sensing and delaying part ( 68 ) for receiving the first synchronizing signal and for detecting and delaying a low voltage of a power supply and - a fault elimination part ( 69 ) for removing interference signals from the low-voltage detection and delay part ( 68 ). Circuit according to Claim 26, characterized in that the low-voltage detection delay part ( 68 ) Comprises: - a ninth delay unit ( 61 ) for delaying the first synchronizing signal from the receiving buffer ( 31 ) for a given time; - a tenth delay unit ( 62 ) for delaying the rising edge of the first synchronizing signal; - one tenth ( 63 ) and an eleventh ( 64 ) Inverter for inverting the output signals of the ninth ( 61 ) or tenth ( 62 ) Delay unit; A first NMOS transistor ( 65 ) having a gate electrode and a source electrode connected in common to a power supply terminal Vcc and a drain electrode connected to the output terminal of the tenth inverter (10). 63 ) connected is; A second NMOS transistor ( 67 ) with a gate electrode connected to the output terminal of the tenth inverter ( 63 ), a source electrode connected to the eleventh inverter ( 64 ) and a drain electrode configured to pass a signal, and a first PMOS transistor ( 66 ) having a grounded gate electrode, a source electrode and a drain electrode connected to the voltage supply terminal and the drain electrode of the second NMOS transistor ( 67 ) are connected. Circuit according to Claim 26, characterized in that the fault elimination part ( 69 ) Includes: - a twelfth inverter ( 69 ) for inverting the fourth, from the second control unit ( 34 ) Feedback control signal; - an eighth NAND gate ( 71 ), the output signals of the low-voltage detection and delay part ( 68 ) and the twelfth inverter ( 69 ) to undergo a logic operation; A thirteenth inverter ( 72 ) for inverting the output signal of the eighth NAND gate ( 71 ); - a ninth NAND gate ( 74 ) to receive the first sync signal from the receive buffer ( 31 ) and the output of the thirteenth inverter ( 72 ) to perform a logic operation to provide a pre-activation pulse for controlling a pre-charge operation for the sense amplifier; and - a fourteenth inverter ( 73 ) for inverting the output signal of the thirteenth inverter ( 72 ) to provide a low voltage sense and noise removal signal. Circuit according to Claim 27, characterized in that the fault elimination part ( 69 ) Includes: a third NMOS transistor ( 85 ), which is between the eleventh inverter ( 64 ) and the second NMOS transistor ( 67 ) is switched; A fifteenth inverter ( 86 ) for inverting one of the second control unit ( 34 ) and supplying it to the gate electrode of the third NMOS transistor ( 85 ); and a fourth NMOS transistor ( 87 ) for turning on / off the output of the second NMOS transistor ( 67 ) with respect to a ground connection to the feedback signal. Circuit according to Claim 25, characterized in that the low-voltage operation and interference signal removal device ( 32 ) is replaced by a low-voltage detecting part which receives the first synchronizing signal from the receiving buffer ( 31 ) and detects low voltage of the power supply to prevent operation at low voltage. Circuit according to Claim 25, characterized in that the low-voltage operation and interference signal removal device ( 32 ) by a fault elimination part ( 69 ), which eliminates spurious signals from the first sync signal. Circuit according to Claim 25, characterized in that the first control unit ( 33 ) Includes: - an eleventh delay unit ( 104 ) for delaying the low-voltage detection and disturbance removal signal from the low-voltage operation and interference signal removal device ( 32 ) by time periods different from each other to provide a first and a second delay signal, thereby the first delay signal as the first control signal; A sixteenth inverter ( 101 for inverting the second delay signal from the eleventh delay unit (FIG. 104 ); - a tenth NAND gate ( 102 ) to detect the low voltage sense and disturbance removal signal from the low voltage operation and disturbance signal eliminator ( 32 ) as well as the signal from the sixteenth inverter ( 101 ) to perform a logic operation to provide a second control signal; and a seventeenth inverter ( 103 ) for inverting the output of the tenth NAND gate ( 102 ) to provide the third control signal. Circuit according to Claim 25, characterized in that the fourth control unit ( 36 ) Includes: a sense amplifier control signal routing unit ( 199 ) to receive the first control signal from the first control unit ( 33 ) and the fifth control signal from the third control unit ( 35 ) to perform a logic operation to provide an enable signal SAN for the NMOS device in the sense amplifier and an enable signal SAP for the PMOS device in the sense amplifier; A bit line switching signal forwarding unit ( 200 ) to receive the third control signal from the first control unit ( 33 ) and the fifth control signal from the third control unit ( 35 ) to provide a logic operation to provide a control signal C1 for connecting a bit line in a main cell and a first I / O node to the sense amplifier, and a control signal C2 for connecting a bit line in a reference cell block and a second I / O node to the sense amplifier ; A column control signal forwarding unit ( 201 ) to receive the second control signal from the first control unit ( 33 ) and the fifth control signal from the third control unit ( 35 ) to provide a logic operation to provide a control signal C4 for providing a column control signal; and - a precharge control signal forwarding unit ( 202 ) to activate the pre-activation pulse from the low-voltage operation and interference signal removal device ( 32 ) and the sixth control signal from the third control unit ( 35 ) to provide a logic operation to provide a precharge control signal C3. Circuit according to Claim 33, characterized in that the bit line switching signal forwarding unit ( 200 ) the third control signal from the first control unit ( 33 ) and the fifth control signal from the third control unit ( 35 ) performs a logic operation to provide the control signal C1 for connecting a bit line and a first I / O node to the sense amplifier, and the control signal C2 for connecting a bit rail line and a second I / O node to the sense amplifier.

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