KR100268908B1 - Split word line ferroelectric memory device and driving circuit for the same - Google Patents

Abstract

PURPOSE: A split word line(SWL) ferroelectric memory device and its driving circuit are provided to improve the level of integration by configuring the ferroelectric memory device to have a cell plate function using split word lines without using separate plate lines. CONSTITUTION: A final X decoding part(21) decodes input X and Z addresses and allows a corresponding cell array to be operated. A global control pulse generating part(16), responsive to a chip enable signal CSBpad provided externally, generates a control pulse required to write and read data. A local control pulse generating part(20), responsive to the control pulse from the global control pulse generating part(16), generates a control pulse required to write and read data. A split word line(SWL) cell array block(23) specifies data. An SWL driving part(22), responsive to the control signals of the final X decoding part(21) and the local control pulse generating part(20), drives the SWL cell array block(23). A Y-address decoding part(18) decodes Y address signals provided externally. A column controlling part(24), responsive to the control signal of the local control pulse generating part(20) and the decoding signal of the Y-address decoding part(18), controls columns. A sensing and data input/output controlling part(25), responsive to the control signals of the local control pulse generating part(20) and the column controlling part(24), senses data of the SWL cell array block(23) and writes the sensed data.

Description

SL U ferroelectric memory device and driving circuit thereof

The present invention relates to a nonvolatile ferroelectric memory, and more particularly, to a split word line (SWL) ferroelectric memory device that does not use a plate line and a driving circuit thereof.

In general, Ferroelectric Memory, or FRAM (Ferroelectric Random Access Memory), which has data processing speed of about DRAM (Dynamic Random Access Memory) which is most commonly used as semiconductor memory device and retains data even when power supply is turned off, is the next generation memory device. I am getting it.

FRAM uses a capacitor as a memory element like DRAM, but uses a ferroelectric material as the dielectric material of the capacitor, and uses a high residual polarization characteristic of the ferroelectric material to remove data even when the electric field is removed.

1 (a) is a characteristic diagram showing a hysteresis loop of a general ferroelectric, and FIG. 1 (b) is a unit capacitor configuration diagram of a general ferroelectric memory.

That is, as in the hysteresis loop of FIG. 1A, it can be seen that the polarization induced by the electric field maintains a constant amount (d, a state) without being eliminated due to the presence of spontaneous polarization even when the electric field is removed. The d and a states correspond to 1,0, respectively, and are applied as memory elements.

That is, a state in which a positive voltage is applied to Node 1 in FIG. 1 (b) is a state of c in FIG. 1 (a), and a state in which no voltage is applied thereafter is d. Conversely, applying a negative voltage to node 1 moves from d to f. If no voltage is applied to the node 1, the state is a, and if a positive voltage is applied to the node 1, the state is changed to the state of c through the state of b.

As a result, data is stored in two stable states, a and d, even when there is no voltage across the capacitor. On the hysteresis loop, the c and d states are the states of the logic value "1", and the a and f states are the states of the logic value "0".

As a method of reading the data stored in the capacitor, the data stored in the capacitor is read using a method of destroying the d state.

The prior art uses a sense amplifier for reading data using the voltage generated in the reference voltage generator and the voltage generated in the main cell array.

In the ferroelectric reference cell, two mode states of one polarity and zero polarity are used to generate a reference voltage on the reference bit line. Therefore, the sense amplifier compares the bit line voltage of the main cell with the reference bit line voltage of the reference cell, thereby reading the information of the main cell.

The read data is rewritten in the same cycle to recover the destroyed data. In particular, the related art relates to a sense amplifier circuit technique related to a plurality of ferroelectric cells configured to supply a reference voltage, and a sense amplifier and a main cell array circuit technique for sensing and amplifying data stored in a main cell in a main memory cell array. .

The number of ferroelectric reference cells is an even number, with one half being in one polarity state and the other half being in zero polarity state.

Hereinafter, a ferroelectric memory of the related art will be described with reference to the accompanying drawings.

Such a FRAM includes a 1T / 1C FRAM in which a unit cell consists of one transistor and one capacitor, and a 2T / 2C FRAM consisting of two transistors and two capacitors.

2 is a configuration diagram of a conventional 1T / 1C ferroelectric memory cell array.

The unit cell structure of a conventional 1T / 1C FRAM is 1T / 1C composed of one transistor and one capacitor similar to DRAM.

That is, a plurality of word lines (W / L) are formed in one direction at regular intervals, and a plurality of plate lines (P / L) are formed in parallel with the word lines between each word line (W / L). The plurality of bit lines B1... Bn are formed at regular intervals in a direction perpendicular to the word lines W / L and the plate lines P / L. The gate electrode of one transistor constituting the unit memory cell is connected to a word line (W / L), the source electrode of the transistor is connected to an adjacent bit line (B / L), and the drain electrode of the transistor is formed of a capacitor. It is connected to the first electrode and the second electrode of the capacitor is connected to the adjacent plate line (P / L).

The driving circuit and operation of the conventional 1T / 1C ferroelectric memory device will be described below.

3 (a) to 3 (b) are diagrams illustrating a driving circuit of a conventional 1T / 1C ferroelectric memory device, and FIG. 4 (a) is a timing diagram for explaining a write operation of a conventional 1T / 1C ferroelectric memory cell. (b) is a timing diagram for explaining a read operation of a conventional 1T / 1C ferroelectric memory cell.

A driving circuit of a conventional 1T / 1C ferroelectric memory device includes a reference voltage generator 1 for generating a reference voltage, a plurality of transistors Q1 to Q4, a capacitor C1, and the like. Since the reference voltage outputted from the signal cannot be directly supplied to the sense amplifier, the reference voltage stabilizer 2, the plurality of transistors Q6 to Q7, and the capacitor (for stabilizing the reference voltages of two adjacent bit lines B1 and B2) C2 to C3), each of which includes a first reference voltage storage unit 3 that stores a reference voltage having a logic value "1" and a logic value "0" in adjacent bit lines, and a transistor Q5. A first equalizer 4 for equalizing the bit line, a plurality of transistors Q8, Q9, ..., ferroelectric capacitors C5, C6, ..., and the like, and a word line W / L. And data connected to the plate line (P / L) The first main cell array unit 5 to be stored, and a plurality of transistors Q10 to Q15, a P-sense amplifier PSA, etc. are formed by the word line of the plurality of cells of the main cell array unit 5. A first sense amplifier 6 for sensing data of the selected cell, a plurality of transistors Q26, Q27, ..., capacitors C7, C8, ..., and the like, connected to different word lines and plate lines And a second main cell array unit 7 for storing data, a plurality of transistors Q28 to Q29, capacitors C9 to C10, and the like, and logic values "1" and logic values "0", respectively, on adjacent bit lines. A second reference voltage storage unit 8 storing a reference voltage of the plurality of transistors; and a plurality of transistors Q16 to Q25, an N-sense amplifier NSA, and the like. And a second sensing amplifier unit 9 for sensing and outputting.

The operation of the conventional 1T / 1C ferroelectric memory cell configured as described above is as follows.

First, the recording mode and the reading mode are described separately as follows.

In the recording mode, as shown in FIG. 4A, when the CSBpad signal, which is a chip enable signal, is externally enabled from "high" to "low", the recording mode enable signal WEBpad is also set to "high". Transition to " low " starts recording mode. Then, the decoding of the address starts and the word line of the selected cell is shifted from "low" to "high" to select the cell. In the period in which the word line maintains "high", the "high" signal of a certain period and the "low" signal of a predetermined period are sequentially applied to the plate line P / L. In order to write a logic value "1" or "0" in the selected cell, a "high" or "low" signal is applied to the corresponding bit line in synchronization with the write enable signal.

In other words, when the "high" signal is applied to the bit line to write the logic value "1", the logic value "1" is written to the ferroelectric capacitor when the plate line signal is "low" in the section where the word line is "high". When a "low" signal is applied to the bit line to write the logic value "0", the logic value "0" is written to the ferroelectric capacitor when the plate line signal is "high".

In this way, the logic value "1" or "0" is recorded.

The operation for reading data stored in a cell is as follows.

First, as shown in FIG. 4 (b), when the CSBpad signal, which is a chip enable signal, is externally enabled from "high" to "low", all bit lines are equalized by the equalizer signal before the corresponding advice line is selected. Equipotential to low. That is, in FIG. 3, when the "high" signal is applied to the equalizer unit 4 and the "high" signal is applied to the transistors Q19 and Q20, the bit line is grounded through the transistors Q19 and Q20, so the potential is low at a low voltage. Becomes Then, by turning off the transistors Q5, Q19, and Q20, each bit line is deactivated, and then the address is decoded, and a signal transitions from "low" to "high" to the word line by the decoded address to select the corresponding cell. . Then, the "high" signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value "1" stored in the ferroelectric memory. If the logic value "0" is stored in the ferroelectric memory, the corresponding data is not destroyed. Thus, the data destroyed and the data not destroyed are different from each other according to the principle of hysteresis rope as described above. Will print

Therefore, when the sense amplifier senses the data output through the bit line, the logic value "1" or "0" is sensed.

In other words, when the data is destroyed, the data is changed from d to f in the hysteresis loop of FIG. 1, and when the data is not destroyed, it is changed from a to f. If it is destroyed, it is amplified to output a logic value "1". If the data is not destroyed, it is amplified to output a logic value "0".

Since the sense amplifier amplifies and outputs the original data, the plate line is deactivated from "high" to "low" while "high" is applied to the corresponding word line.

However, in the conventional ferroelectric memory cells of 1T / 1C, since the reference cell needs to operate more than the main memory cell, the deterioration characteristic of the reference cell deteriorates rapidly and the reference voltage is not stable. In addition, in the method of generating a reference voltage by the voltage adjusting circuit, the reference voltage is influenced by the external power supply characteristic, which is not stable and also influences the external noise characteristic.

The 2T / 2C ferroelectric memory cell has been proposed in consideration of all practical matters (development degree, integration degree, stability of ferroelectric thin film, operational reliability, etc.) of 1T / 1C FRAM having such a problem.

FIG. 5 is a configuration diagram of a conventional 2T / 2C ferroelectric memory cell array, FIG. 6A is a timing diagram illustrating a write operation of a conventional 2T / 2C ferroelectric memory cell, and FIG. 6B is a conventional 2T / 2C. A timing diagram for explaining a read operation of a ferroelectric memory cell.

In the conventional 2T / 2C ferroelectric memory cell configuration, the unit cell is composed of two transistors and two capacitors.

That is, a plurality of word lines (W / L) are formed in one direction at regular intervals, and a plurality of plate lines (P / L) are formed in parallel with the word lines between each word line (W / L). And a plurality of bit lines and bit bar lines B1, BB1, B2, and BB2 are formed continuously at regular intervals in a direction perpendicular to the word lines W / L and plate lines P / L. do. The gate electrodes of the two transistors constituting the unit memory cell are connected to one word line (W / L) adjacent in common, and the source electrodes of the transistors are adjacent to the bit line (b) and the bit bar line (BB). The drain electrode of each transistor is connected to the first electrode of the two capacitors, respectively, and the second electrode of the two capacitors is connected to the common adjacent plate line P / L.

The driving circuit and operation of the conventional 2T / 2C ferroelectric memory cell are as follows.

A conventional 2T / 2C ferroelectric memory cell writes and reads a logic value "1" or "0" unlike a 1T / 1C ferroelectric memory cell.

That is, as shown in FIG. 6A, when the CSBpad signal, which is a chip enable signal, is externally transitioned from "high" to "low" and enabled in the recording mode, the write mode enable signal WEBpad is simultaneously enabled. In addition to the transition from "high" to "low", the "high" and "low" or "low" and "high" signals are respectively applied to the bit line and the bit bar line according to the logic value to be written.

The decoding of the address is started and the word line of the selected cell is shifted from "low" to "high" to select the cell. In the period in which the word line maintains "high", the "high" signal of a certain period and the "low" signal of a predetermined period are sequentially applied to the plate line P / L.

That is, a "high" signal is applied to the bit line Bn to write a logic value "1", a "low" signal is applied to the bit bar line BB-n, and a bit is written to write a logic value "0". The "low" signal may be applied to the line Bn and the "high" signal may be applied to the bit bar line BB-n. In this way, a logic value "1" or "0" is recorded.

The operation for reading data stored in a cell is as follows.

As illustrated in FIG. 6B, when the CSBpad signal, which is a chip enable signal, is externally enabled from "high" to "low", the read mode is enabled. That is, the write mode enable signal WEBpad signal transitions from " low " to " high " to enable the write mode and to read mode.

All bit lines are then equipotentially low by the equalizer signal before the word line is selected. This is the same as the operation of the 1T / 1C ferroelectric memory of FIG.

After completion of the equipotential with a low voltage, the address is decoded and a signal transitions from "low" to "high" on the word line by the decoded address to select the cell. Then, the "high" signal is applied to the plate line of the selected cell to destroy the data of the bit line or the bit bar line. That is, if the logic value "1" is written, the data of the capacitor connected to the bit line will be destroyed. If the logic value "0" is written, the data of the capacitor connected to the bit bar line will be destroyed. Thus, different values are output according to the principle of the hysteresis loop as described above depending on which of the bit lines or the bit bar lines is destroyed.

Therefore, when the sense amplifier senses the data output through the bit line and the bit bar line, the logic value "1" or "0" is sensed.

Since the sense amplifier amplifies and outputs the original data, the plate line is deactivated from "high" to "low" while "high" is applied to the corresponding word line.

The conventional ferroelectric memory device and driving circuit have the following problems.

First, despite the advantage that data is preserved even when the power is off, the conventional FRAM requires a separate cell plate line, so the layout is complicated, and the manufacturing process is also complicated, which is disadvantageous in terms of mass production.

Second, since a separate plate line must be used, a control signal must be supplied to the plate line in data read and write operations, thereby reducing efficiency as a memory device.

Third, the conventional ferroelectric memory cell cannot solve the integration degree unless a new electrode material and barrier material are presented.

Fourth, another reason for the problem in terms of integration is that because the technology of directly forming the ferroelectric film on the silicon surface is insufficient, the capacitor can not be formed directly on the silicon substrate or polysilicon, resulting in a larger area than the DRAM of the same capacity.

Fifth, especially in the conventional 1T / 1C, since the reference cell is configured to be used for the read operation of the main memory more than several hundred times more than the characteristics of the ferroelectric film, the reference cell is more than the main memory cell. Since many operations must be performed, the deterioration characteristics of the reference cell deteriorate rapidly, and thus the reference voltage is not stable.

The present invention has been made to solve the problems of the conventional FRAM, and an object thereof is to provide a ferroelectric memory device and a driving circuit that do not constitute a separate cell plate line.

Figure 1 (a) is a characteristic diagram showing a hysteresis loop of a typical ferroelectric

1 (b) is a unit capacitor configuration of a typical ferroelectric memory

2 is a configuration diagram of a conventional 1T / 1C ferroelectric memory cell array

3 (a) to 3 (b) are diagrams illustrating a driving circuit of a conventional 1T / 1C ferroelectric memory cell.

4A is a timing diagram for explaining a write operation of a conventional 1T / 1C ferroelectric memory cell.

4B is a timing diagram illustrating a read operation of a conventional 1T / 1C ferroelectric memory cell.

5 is a configuration diagram of a conventional 2T / 2C ferroelectric memory cell array

6 (a) is a timing diagram for explaining a write operation of a conventional 2T / 2C ferroelectric memory cell.

FIG. 6B is a timing diagram illustrating a read operation of a conventional 2T / 2C ferroelectric memory cell.

7 is a block diagram of an SWL ferroelectric memory cell array configuration of the present invention.

8 is a schematic diagram of an SWL ferroelectric memory cell array circuit according to a first embodiment of the present invention.

9 is a schematic diagram of an SWL ferroelectric memory cell array circuit according to a second embodiment of the present invention.

Fig. 10 is a schematic diagram of the SWL ferroelectric memory structure array circuit of the third embodiment of the present invention.

11 is a block diagram of a driving circuit of the SWL ferroelectric memory device according to the present invention.

12 is a block diagram of a global control pulse generator according to the first embodiment of the present invention.

13 is a block diagram of a global control pulse generator of a second embodiment of the present invention;

Fig. 14 is a circuit diagram of the input buffer section of the first embodiment of the present invention.

Fig. 15 is a circuit diagram of the input buffer section of the second embodiment of the present invention.

Fig. 16 is a circuit diagram of the input buffer section of the third embodiment of the present invention.

17 is a circuit diagram of the input buffer section according to the fourth embodiment of the present invention.

18 is a circuit diagram of a power-supply detector of the first embodiment of the present invention.

19 is a circuit diagram of a low voltage operation and a noise preventing unit according to a first embodiment of the present invention;

20 is a circuit diagram of a low voltage operation and a noise preventing unit according to a second embodiment of the present invention.

21 is a circuit diagram of a low voltage operation and a noise preventing unit according to a third embodiment of the present invention.

22 is a circuit diagram of a low voltage operation and a noise preventing unit according to a fourth embodiment of the present invention.

Fig. 23 is a circuit diagram of the first control unit according to the first embodiment of the present invention.

24 is a circuit diagram of the second control unit according to the first embodiment of the present invention.

25 is a circuit diagram of the third control unit according to the first embodiment of the present invention.

Fig. 26 is a circuit diagram of the third control unit in the second embodiment of the present invention.

27 is a circuit diagram of the third control unit according to the third embodiment of the present invention.

28 is a circuit diagram of the fourth control unit in accordance with the first embodiment of the present invention.

29 is a circuit diagram of the fourth control unit according to the second embodiment of the present invention.

30 is an operation timing diagram of the power-up detection unit of the present invention.

31 is a timing chart of the operation of the global control pulse generator according to the first embodiment of the present invention.

32 is an operation timing diagram of the global control pulse generator according to the second embodiment of the present invention.

33 is a timing chart of the global control pulse generator according to the third embodiment of the present invention.

34 is an operation timing diagram of the global control pulse generator according to the fourth embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

11: X-address buffer part 12: X pre-decoder part

13: Z-address buffer part 14: Z pre-decoder part

15: X, Z-ATD generator 16: global control pulse generator

17: Y-address buffer section 18: Y pre-decoder section

19: Y-ATD generator 20: local control pulse generator

21: the final X decoder 22: SWL driver

23: SWL cell array unit 24: column control unit

25: sense amplifier and input / output control unit 26: input / output bus control unit

31: input buffer unit 32: low voltage operation and noise prevention unit

33: first control unit 34: second control unit

35: third controller 36: fourth controller

44: power-up detection unit 68: low voltage detection and delay unit

61, 62, 104, 148, 149, 150, 151, 173, 179

69: noise removing unit 152: P2 pulse signal output unit

172: signal extension unit 174: fifth control signal output unit

199: sense amplifier control signal output unit 200: bit line control signal output unit

201: column control signal output unit 202: pre-charge control signal output unit

233: power supply voltage rise detection unit 234: amplification unit

235: feed-back section 236: power-up signal output section

237: S1 signal output unit 238: S2 signal output unit

The ferroelectric memory device of the present invention for achieving the above object is a plurality of split word lines (SWL) arranged in one direction with a predetermined interval, and a plurality of arranged in a direction perpendicular to the respective SWL It is characterized by including a bit line and a unit cell formed in each pair by pairing two adjacent SWL and two adjacent bit lines.

In addition, the driving circuit of the ferroelectric memory device of the present invention for achieving the above object is a final X decoder unit for controlling the operation of the cell array block by decoding the input X, Z-address, and the CSBpad signal input from the outside A global control pulse generator for outputting control pulses required for data recording and reading, a local control pulse generator for inputting control pulses of the global control pulse generator and outputting a control signal for data recording and reading; A SWL cell array block for storing a signal; An address decoder and a control signal of the local control pulse generator and the Y-address A column control unit for controlling a column according to a decoding signal of a signal decoder unit, a data signal for sensing the data of the SWL cell array block under the control signal of the local control pulse generator and a control unit of the column control unit, and writing data to the SWL cell array block. It is characterized by including the sensing and data input and output control unit.

Such a ferroelectric memory device and a driving circuit thereof according to the present invention will be described in detail with reference to the accompanying drawings.

A ferroelectric memory device of the present invention is as follows.

Fig. 7 is a block diagram showing a simple structure of the entire ferroelectric memory device of the present invention.

The chip of the ferroelectric memory device of the present invention has a large SWL driver for driving a split word line, a cell array for storing data, and a sense for sensing data. It consists of a core part (Core) which contains an amp block and the bart line control block which controls a bit line.

Here, the cell array units are arranged on the left and right sides with respect to one SWL driving unit, and the core unit is disposed between the cell array units in the up and down direction of each cell array unit.

The cell array unit of the present invention configured as described above will be described in more detail as follows.

8 is a schematic diagram of an SWL ferroelectric memory cell sub-block array according to a first embodiment of the present invention.

The structure of the SWL ferroelectric memory cell array of the first embodiment of the present invention is a plurality of split word lines (hereinafter referred to as " SWL ") in one direction at regular intervals (SWL1-n, SWL2-n, ... SWL2). -n + 3) are arranged, and a plurality of bit lines Bit-n, Bit-n + 1, ... RBit-n, RBit-n + 1 are arranged at regular intervals in a direction perpendicular to the respective SWLs. .

A unit cell is formed in each pair by using two adjacent SWLs and two adjacent bit lines as a pair. That is, a unit cell has a gate electrode connected to a first SWL of a pair of SWLs, a source electrode connected to a first bit line of a pair of bit lines, and a gate electrode of a second SWL of a pair of SWLs. A second transistor connected to the second bit line of the pair of bit lines, a first capacitor connected to a drain electrode of the first transistor, and a second electrode connected to a second SWL; And a second capacitor connected to the drain electrode of the second transistor and the second electrode connected to the first SWL.

In this case, as described above, the cell array unit includes a main cell block for substantially recording data and a reference cell block for storing reference values for reading data. Accordingly, a plurality of bit lines for the main cell are arranged to form one main cell sub-block, and a pair of reference cell bit lines RBit-n and RBit-n per main cell sub-block. +1) is arranged to form a reference cell sub-block, and a plurality of such main cell sub-blocks and reference cell sub-blocks are configured to form one cell array unit.

In the SWL cell array according to the first embodiment of the present invention, the main cell sub-block is composed of four columns and the reference cell sub-block is composed of two columns.

9 is a configuration diagram of an SWL ferroelectric memory cell sub-block array according to a second embodiment of the present invention.

The configuration of the SWL ferroelectric memory cell array of the second embodiment of the present invention is the same as that of the SWL cell array of the first embodiment of the present invention, but the main cell sub-block is composed of eight columns and the reference cell sub-block is composed of two columns.

In addition, if necessary, the main cell sub-block may be configured in 2n column units (n = 2 or more natural numbers), and the reference cell block may be configured in 2 column units.

Fig. 10 is a configuration diagram of the SWL ferroelectric memory cell array unit in the third embodiment of the present invention.

The SWL ferroelectric memory cell array configuration of the third embodiment of the present invention has a plurality of split word lines (hereinafter referred to as " SWL ") in one direction at regular intervals (SWL1-n, SWL2-n, ... SWL2-). n + 3) is arranged, and a plurality of bit lines Bn and B-n + 1 and bit bar lines BB-n and BB-n + 1) are formed at a predetermined interval in a direction perpendicular to the respective SWLs. They are arranged alternately with each other.

Then, a unit cell is formed in each pair by using two adjacent SWLs, an adjacent bit line b and a bit bar line BB as a pair. That is, a unit cell has a gate electrode connected to a first SWL of a pair of SWLs, and a source electrode connected to a bit line b, a gate electrode connected to a second SWL of a pair of SWLs, and a source electrode. A second transistor connected to a silver bit bar line BB, a first capacitor connected to a drain electrode of the first transistor, and a second electrode connected to a second SWL, and a drain of the second transistor A first electrode is connected to the electrode and the second electrode is composed of a second capacitor connected to the first SWL.

The SWL ferroelectric memory cell array of the third embodiment of the present invention is almost similar to the cell array of the first and second embodiments of the present invention. However, the third embodiment replaces the even-numbered bit lines b of the first and second embodiments of the present invention with bit bar lines BB, and the reference cell sub-blocks of the first and second embodiments of the present invention are all It has been replaced for use as the main cell.

The driving circuit of the ferroelectric memory device of the present invention configured as described above is as follows.

11 is a block diagram of a ferroelectric memory device driving circuit of the present invention.

The driving circuit of the ferroelectric memory device of the present invention is configured to be used in all the cell array configurations of the first, second and third embodiments.

An X-address buffer unit 11 for buffering an X address signal among X, Y, and Z addresses input from the outside, and an X-pre-decoder for pre-decoding a signal output from the X-address buffer unit 11 ( An X-Pre-Decoder) 12, a Z-address buffer unit 13 for buffering a Z address among X, Y, and Z addresses input from the outside, and an output from the Z-address buffer unit 13 Z-pre-decoder section 14 for pre-decoding the signal, and X-address and Z- output from the X-address buffer section 11 and the Z-address buffer section 13. Inputs an X, Z-ATD generator 15 for detecting and outputting an address transition point of an address signal, an output signal of the X, Z-ATD generator 15, and a CSB-pad signal input from the outside, and then Generates a power-up detection signal and outputs a basic pulse related to memory control according to the X, Z-ATD signal, CSBpad signal, and power-up detection signal A global control pulse generator 16, a Y-address buffer unit 17 for buffering an Y address among X, Y, and Z addresses input from the outside, and a signal output from the Y-address buffer unit 17 An X-Pre-Decoder unit 18 for preliminarily decoding the signal, and a Y-ATD for detecting and outputting an address transition point of the Y-address signal output from the Y-address buffer unit 17. The generator 19, the signal output from the global control pulse generator 16, the Z-free decoded signal output from the Z-free decoder 14, and the output signal of the Y-ATD generator 19 And a local control pulse generator 20 for generating a pulse required for each memory block, and an X-predecoded signal output from the X-pre-decoder section 12 and the Z-pre-decoder section 14. And an X-final-decoder section 21 for synthesizing a Z-precoded decoded signal and selecting a corresponding memory cell block. An SWL driver 22 for synthesizing the signals output from the post-decoder 21 and the local control pulse generator 20 to drive each split word line of each SWL cell block 23; A column control unit 24 for synthesizing the output signals of the pre-decoder unit 18 and the local control pulse generator 20 to select the corresponding bit line (or bit bar line), and the local control pulse generator 20 A sense amplifier and input / output control unit 25 for controlling the operation and input / output (I / O) of the sense amplifier by synthesizing the output signal of the column controller 24 with the output signal of And an input / output bus control section 26 for interfacing the sense bus and the input / output control section 25 with the data bus.

Here, the global control pulse generator will be described in more detail.

12 is a block diagram of a global control pulse generator according to the first embodiment of the present invention.

The global control pulse generator of the first embodiment of the present invention inputs a signal including at least a CSBpad signal among an externally input CSBpad signal, an X, Z-ATD signal of the X, Z-ATD generator 15, or a power-up detection signal. An input buffer unit 31 which receives the first and second synchronization signals; Receiving the first synchronization signal and the feedback signal (the fourth control signal of the second control unit) of the input buffer unit 31 for filtering the low voltage detection signal and the noise of the first synchronization signal to prevent the operation is performed at low voltage A low voltage operation and noise prevention unit 32 for outputting a noise removing signal and a preliminary activation pulse for precharging the bit line and the like; When the low voltage operation and noise prevention unit 32 is supplied with the normal power supply voltage, the first control signal for adjusting the enable timing of the sense amplifier and the column select enable timing are controlled by inputting the noise-removed signal. A first control unit for outputting a second control signal for adjusting the pull-up of the bit line of the reference cell, and a third control signal for generating the input signal and other control signal of the SWL driver ( 33); A basic waveform generation signal S1 of SWL1 and a basic waveform generation signal S2 of SWL2 for the pair of SWLs of the SWL driver by inputting a third control signal of the first controller 33, and the signal ( Generating a fourth control signal, which is a basic pulse signal for adjusting the activation period of S1 and S2, and a pulse signal P2 having improved driving ability of the fourth control signal, respectively, so that the fourth control signal is operated in the low voltage operation; And a second control part 34 outputting the feedback signal of the noise prevention part 32 and outputting the pulse signal P2 to the local control pulse generating part 20. The basic waveform generation signal S1 of the SWL1 and the basic waveform generation signal of the SWL2 by inputting the first and second synchronization signals of the input buffer unit 31 and the fourth control signal of the second control unit 34. A fifth control signal for adjusting to be synchronized with the CSBpad signal when all signals other than (S2) are disabled, and a basic waveform generation signal S1 of the SWL1 and a basic waveform generation signal S2 of the SWL2 are enabled; In the state, if the CSBpad signal is disabled, the disable is disabled to extend the enable state until the basic waveform generation signal S1 of SWL1 and the basic waveform generation signal S2 of SWL2 are normally completed. A third control unit 35 outputting a sixth control signal for the control unit; Preliminary activation of the fifth and sixth control signals of the third control unit 35 and the first, second and third control signals of the first control unit 33 and the low voltage operation and noise prevention unit 32. A pulse is input to enable the enable signal (SAN) of the n-MOS device of the sense amplifier and the enable signal (SAP) of the p-MOS device, the bit line of the main cell block and the first input / output node of the sense amplifier. The control signal C1 for connecting, the control signal C2 for connecting the bit line of the reference cell block and the second input / output node of the sense amplifier, the bit line of the main cell and the bit line of the reference cell; A control signal C3 for adjusting the low voltage precharge of the sense amplifier node, and a control signal C4 for adjusting pull-up of the bit line of the reference cell and the time of column selection enable; It comprises a four control unit 36.

On the other hand, assuming that the external input signals (CSBpad signal, A, Z-ATD signal, and power-up detection signal) are stably input from the global control pulse generator of the first embodiment, the low voltage operation and the noise protection unit are sufficient. It works. This will be described as a second embodiment as follows.

Fig. 13 is a block diagram showing the global control pulse generator of the second embodiment of the present invention.

That is, the global control pulse generator according to the second embodiment of the present invention includes a signal including at least a CSBpad signal of an externally input CSBpad signal, an X, Z-ATD signal of the X, Z-ATD generator 15, or a power-up detection signal. An input buffer unit 31 for receiving the first and second synchronization signals; A first control signal for adjusting an enable timing of a sense amplifier by inputting a first synchronization signal of the input buffer unit 31, a column selection enable timing, and a pull-pull of a bit line of a reference cell; a first control unit 33 for outputting a second control signal for adjusting -up) and a third control signal for generating an input signal of the SWL driver and other control signals; A basic waveform generation signal S1 of SWL1 and a basic waveform generation signal S2 of SWL2 for the pair of SWLs of the SWL driver by inputting a third control signal of the first controller 33, and the signal ( Generating a fourth control signal, which is a basic pulse signal for adjusting the activation period of S1, S2, and a pulse signal P2 having improved driving ability of the fourth control signal, and converting the pulse signal P2 into a local control pulse. The second control unit 34 outputs to the generation unit 20, the first and second synchronization signals of the input buffer unit 31 and the fourth control signal of the second control unit 34 are input to the A fifth control signal for adjusting to be synchronized with the CSBpad signal when all signals other than the basic waveform generating signal S1 of SWL1 and the basic waveform generating signal S2 of SWL2 are disabled, and the basic waveform generating signal of SWL1 ( S1) and the basic waveform generation signal S2 of SWL2 are In the enabled state, if the CSBpad signal is disabled, the disable is interrupted to extend the enabled state until the basic waveform generation signal S1 of SWL1 and the basic waveform generation signal S2 of SWL2 are normally completed. A third control unit 35 outputting a sixth control signal; The fifth and sixth control signals of the third control unit 35 and the first, second and third control signals of the first control unit 33 and the first synchronization signal of the input buffer unit 31 are Input to connect the enable signal (SAN) of the n-MOS device of the sense amplifier and the enable signal (SAP) of the p-MOS device with the bit line of the main cell block and the first input / output node of the sense amplifier. The control signal C1 for connecting the bit line of the reference cell block and the second input / output node of the sense amplifier to each other, the bit line of the main cell and the bit line and sense amplifier of the reference cell. A fourth control for outputting a control signal C3 for adjusting the low voltage precharge of the node and a control signal C4 for adjusting the pull-up of the bit line of the reference cell and the time of column selection enable; It is comprised including the part 36.

On the other hand, although not shown in the drawing, the low voltage operation and noise prevention unit in the global control pulse generator of the first embodiment is a low voltage operation prevention unit or a noise removing unit having only a function of removing noise to prevent operation at low voltage. It can also be configured.

Each part of the global control pulse generator of the present invention configured as described above will be described in more detail as follows.

14 is a circuit diagram of the input buffer section of the first embodiment of the present invention, FIG. 15 is a circuit diagram of the input buffer section of the second embodiment of the present invention, and FIG. 16 is a circuit diagram of the input buffer section of the third embodiment of the present invention. Fig. 17 is a circuit diagram of the input buffer section of the fourth embodiment of the present invention.

The configuration of the input buffer unit according to the first embodiment of the present invention uses only CSBpad signals input from the outside, as shown in FIG. 14. The three inverters 41, 42, and 43 are connected in series to invert the CSBpad signals, thereby inverting the inverter 43. ) Is output as the first synchronous signal and the output of the inverter 42 is output as the second synchronous signal.

The configuration of the input buffer unit according to the second embodiment of the present invention uses the CSBpad signal and the power-up detection signal input from the outside, as shown in FIG. That is, in order to operate the circuit in a stable state, a power-up detection unit 44 which emits a "high" signal until the power is stabilized and then transitions to a "low" signal when the power is stabilized, and an externally input CSBpd A NOR gate 45 for performing a logical sum operation on the signal and the signal output from the power-up detection unit 44, inverting the signal, and outputting the second sync signal by inverting the output of the NOR gate 45. The inverter 46 outputs, and the inverter 47 which inverts the output of the inverter 46, and outputs it as a 1st synchronous signal.

The configuration of the input buffer unit according to the third embodiment of the present invention uses a CSBpad signal input from the outside and an X, Z-ATD signal output from the X, Z-ATD generation unit 15 of FIG. The configuration is the same as that of FIG. 15, and only the X, Z-ATD signals are input to one input terminal of the NOR gate 45.

As shown in FIG. 17, the input buffer unit according to the fourth embodiment of the present invention is an externally input CSBpad signal and an X, Z-ATD signal and a power-up detection signal output from the X, Z-ATD generator 15 of FIG. Will be used. The configuration is the same as that in FIG. 15, and instead of only the noah gate 45, the three-input noah gate 48 is used to perform a logical sum operation on the X, Z-ATD signal, the CSBpad signal, and the power-up detection signal to invert the output. It is.

Here, the detailed circuit configuration of the power-up detection unit is as follows.

18 is a circuit configuration diagram of the power-up detection unit of the present invention.

As shown in FIG. 18, the power-supply detector of the present invention includes the PMOS transistors 211 to 214, the NMOS transistors 215 to 218, and the like. And an amplifier unit 234 configured to compare and amplify and output the output signal of the power supply voltage rise detection unit and the power supply voltage, including the PMOS transistors 219 to 220 and the NMOS transistors 221 to 224. 229), an NMOS transistor 230, inverters 226 to 228, and the like, which feed-back the output of the amplifier 234 to output a signal capable of indicating a stable state and an unstable state of the power supply voltage. A power-up output unit configured to include a back unit 235 and inverters 231 and 232 to improve the driving capability so that the output of the feed-back unit 235 can be used by the global control pulse generator 16. And 236.

The configuration of the low voltage operation and noise prevention unit of the present invention is as follows.

Fig. 19 is a circuit diagram of the low voltage operation and noise preventing unit of the first embodiment of the present invention, and Fig. 20 is a circuit diagram of the low voltage operation and noise preventing unit of the second embodiment of the present invention.

The low voltage operation and the noise protection unit of the present invention can be largely divided into three functions.

First, the low voltage is sensed so that the control pulse is disabled at the low voltage to protect the memory cell data.

Second, the pulse width of the control signal C3 for adjusting the low voltage precharge of the sense amplifier is performed by performing a delay role.

Third, noise of a signal input from the outside (CSBpad signal) is removed.

Therefore, the low voltage operation and noise prevention unit of the first embodiment of the present invention, as shown in Figure 19, the low voltage detection and delay unit 68 for delaying the pulse width of the low voltage detection and control signal (C3) and noise removal for removing noise Reject 69.

The low voltage detection and delay unit 68 is composed of inverters 79 and 80, and the first delay unit 61 for delaying the first synchronization signal of the input buffer unit 31 for a predetermined time and the current driving capability of the PMOS. Inverters 76 and 78 for reducing the size, and inverters 75 and 77 for increasing the PMOS and NMOS driving capabilities, so as to reduce the "high" pulse width of the first synchronization signal of the input buffer unit 31. The second delay unit 62 for delaying the rising edge of the first synchronization signal, the inverters 63 and 64 for inverting the outputs of the first and second delay units 61 and 62, respectively, the gate electrode and the source electrode. The NMOS transistor 65 is connected to the power terminal Vcc in common and the drain electrode is connected to the output terminal of the inverter 63, the gate electrode is connected to the output terminal of the inverter 63, and the source electrode is connected to the inverter. An NMOS transistor 67 connected to 64 and outputting a signal to a drain electrode 67 ), The gate electrode is grounded, and the source electrode and the drain electrode are composed of a PMOS transistor 66 connected to a power supply terminal and a drain electrode of the NMOS transistor 67, respectively.

The noise removing unit 69 may include an inverter 70 for inverting a fourth control signal fed back from the second control unit 34, an output of the low voltage detection and delay unit 68, and The NAND GATA 71 for performing logical multiplication on the output of the inverter 70 and inverting the output, the inverter 72 for inverting the output of the NAND gate 71, and the input buffer unit 31. A NAND gate 74 that logically multiplies and inverts the first synchronous signal and the output of the inverter 72 to output a pre-activation pulse for precharge adjustment of the sense amplifier, and inverts the output of the inverter 72 to low voltage And an inverter 73 for outputting detection and noise removal signals.

On the other hand, as shown in Fig. 20, the low voltage operation and the noise preventing unit of the second embodiment of the present invention, between the inverter 64 and the NMOS transistor 67 of the low voltage sensing and delay unit 69 of the first embodiment of the present invention. The noise removing unit 69 is provided.

That is, the noise removing unit 69 inverts the NMOS transistor 85 connected between the inverter 64 and the NMOS transistor 67 and the feedback signal (fourth control signal) of the second control unit 34. An inverter 86 for outputting to the NMOS transistor 85 and an NMOS transistor 87 for grounding the output of the NMOS transistor 67 in accordance with the feedback signal. An inverter 81 for inverting the output of the NMOS transistor 67, an inverter 82 for inverting the output of the inverter 81, an output of the inverter 82, and an input buffer unit 31. And a NAND gate 84 for logically multiplying and inverting the first synchronous signal and outputting the preliminary activation pulse, and an inverter 83 for inverting the output of the inverter 82 and outputting a low voltage detection and noise removal signal. The low voltage operation and the noise protection unit can be configured.

In addition, in the low voltage operation and noise prevention unit as shown in FIGS. 19 and 20, the low voltage detection and delay unit 68 may be omitted, or conversely, the noise removal unit 69 may be omitted.

That is, FIG. 21 illustrates a case in which only the noise removing unit 69 is installed except for the low voltage sensing and delay unit in FIG. 19.

FIG. 22 illustrates a case in which only the low voltage sensing and delay unit 68 is installed except for the noise removing unit in FIG. 20.

The configuration of the first control unit of the global control pulse generator of the present invention is as shown in FIG.

FIG. 23 is a circuit diagram illustrating the first control unit of the present invention of FIG. 12 or FIG. 13.

The first control unit of the present invention is composed of inverters 91 to 100 to delay the low voltage operation and the low voltage detection signal of the noise protection unit 32 and the first synchronization signal of the input buffer unit 31 for a predetermined time. The third delay unit 104 for outputting the first control signal, the inverter 101 for inverting the signal output from the third delay unit 104, and the low voltage detection of the low voltage operation and noise prevention unit 32 And a NAND gate 102 that logically multiplies and inverts the noise canceling signal or the first synchronization signal of the input buffer unit 31 with the output signal of the inverter 101, and outputs a second control signal, and the NAND gate ( And an inverter 103 that inverts the output of the output 102 and outputs a third control signal.

The configuration of the second control unit of the present invention is as follows.

24 is a circuit diagram of the second control unit of the present invention.

The configuration of the second control unit includes a plurality of inverters 111, 113, 115, 117, and 119 for reducing the current driving capability of the PMOS of the sense amplifier unit and increasing the current driving capability of the NMOS, and the current driving capability of the PMOS and the NMOS. A third delay unit 148 composed of inverters 112, 114, 116, 118, and 120 for increasing the delay time of the falling edge of the third control signal output from the first control unit 33; To reduce the current driving capability of the PMOS and the NMOS gate 121 for logically calculating and inverting the output of the third delay unit 148 and the third control signal, and increasing the current driving capability of the NMOS. A plurality of inverters 123, 125, 127, 129, and 131 and inverters 122, 124, 126, 128, and 130 for increasing the current driving capability of the PMOS and NMOS. Delay the rising edge of the output signal for a predetermined time The fourth delay unit 149, the inverter 132 for inverting the third control signal, the output of the inverter 132, the output of the Noah gate 121, and the fourth delay unit 149. A NAND gate 133 that logically multiplies and inverts an output to output a fourth control signal, and logically multiplies an output of the inverter 132, an output of the third delay unit 148, and an output of the NAND gate 133. A fifth delay unit 150 including an NAND gate 134 for inverting and outputting the inverter, and inverters 135 to 138 to delay a rising edge of the output of the NAND gate 133 for a predetermined time, and the inverter 113. NAND gate 141 for performing a logical multiplication on the output of the NAND gate 134 and the output of the NAND gate 133, and the inverters 142 and 143. A sixth delay unit 151 for delaying the rising edge for a predetermined time; The gate 139 and the inverter 140 are configured to perform a logical multiplication on the output of the fifth delay unit 150 and the output of the NAND gate 133 to output the basic waveform generation signal S1 of the SWL1. A basic waveform of SWL2 is formed by S1 signal output unit 237, NAND gate 144, and inverter 145, which performs a logic operation on the output of the NAND gate 133 and the output of the sixth delay unit 151. S2 signal output unit 238 for outputting the generated signal (S2) and inverters (146, 147) to increase the driving capability of the signal of the NAND gate 133 to output a pulse signal (P2) pulse signal The output unit 152 is configured.

The configuration of the third control unit of the present invention is as follows.

FIG. 25 is a circuit diagram of the third control section of the first embodiment of the present invention, and FIG. 26 is a circuit diagram of the third control section of the second embodiment of the present invention, and FIG. 27 is a circuit diagram of the third control section of the third embodiment of the present invention. It is also.

As shown in FIG. 25, the third control unit according to the first embodiment of the present invention includes an inverter 161, NAND gates 162, 163, and 164, and the first synchronization signal and the second control of the input buffer unit 31. A signal extension unit for inputting the fourth control signal of the unit 34 and sliding the high pulse of the pulse signal P2 output from the second control unit 34 until the CSBpad signal is enabled as "low". 172, inverters 165 to 168, and the like, and a seventh delay unit 173 for delaying the rising edge of the output signal of the signal expansion unit 172 by a predetermined time; And a NAND gate 171 for outputting a sixth control signal by logically multiplying and inverting the second synchronization signal of the input buffer unit 31, a NAND gate 169, and an inverter 170. Logically multiply the output of the delay unit 173 and the output of the NAND gate 171 by It consists of the control signal output unit 174 which outputs a control signal 5.

In the configuration of the third control unit according to the second exemplary embodiment of the present invention, the signal extension unit 172 is omitted in FIG. 25 as shown in FIG. 26. That is, the fourth control signal is directly input to the seventh delay unit 173.

In the configuration of the third control unit according to the third embodiment of the present invention, as shown in FIG. 27, in FIG. 25, although the seventh delay unit 173 delays the rising edge of the output signal of the signal extension unit 171, the signal extension unit 171 is used. The eighth delay unit 179 delays all of the output signals (including the rising edge and the falling edge).

FIG. 28 is a circuit diagram of a fourth control unit according to the global control pulse generator of FIG. 12 of the present invention. FIG. 29 is a fourth control unit according to the global control pulse generator of FIG. 13. The configuration circuit diagram.

First, the configuration of the fourth control unit according to the first embodiment of the present invention is composed of inverters 181, 183, 184, and 185, NAND gates 182, and the like, as shown in FIG. 28. A sense for outputting the enable signal SAN of the NMOS element of the sense amplifier and the enable signal SAP of the PMOS element of the sense amplifier by performing a logic operation on the first control signal and the fifth control signal of the third control unit 35. The amplifier control signal output unit 199, the NAND gate 186, inverters (187 to 191) and the like, the third control signal of the first control unit 33 and the fifth of the third control unit 35 Logically the control signal to connect the control signal C1 for connecting the bit line of the main cell block and the first input / output node of the sense amplifier and the bit line of the reference cell block and the second input / output node of the sense amplifier. A bit line switching signal output unit 200 for outputting a control signal C2 for The gate 192, the inverters 193, 193, 195, and the like, and perform a logic operation on the second control signal of the first control unit 33 and the fifth control signal of the third control unit 35 to perform a column control signal. And a column control signal output unit 201 for outputting a control signal C4, a NAND gate 196, inverters 197 and 198, and the like, and preliminarily activating the low voltage operation and noise prevention unit 32. And a pre-charge control signal output unit 202 for outputting the pre-charge control signal C3 by performing a logic operation on the pulse and the sixth control signal of the third control unit 35.

In addition, the configuration of the fourth control unit according to the second embodiment of the present invention is composed of an inverter (181, 183, 184, 185), NAND gate 182, etc. as shown in FIG. A sense for outputting the enable signal SAN of the NMOS element of the sense amplifier and the enable signal SAP of the PMOS element of the sense amplifier by performing a logic operation on the first control signal and the fifth control signal of the third control unit 35. The amplifier control signal output unit 199, the NAND gate 186, inverters (187 to 191) and the like, the third control signal of the first control unit 33 and the fifth of the third control unit 35 Logically the control signal to connect the control signal C1 for connecting the bit line of the main cell block and the first input / output node of the sense amplifier and the bit line of the reference cell block and the second input / output node of the sense amplifier. A bit line switching signal output unit 200 for outputting a control signal C2 for The gate 192, the inverters 193, 193, 195, and the like, and perform a logic operation on the second control signal of the first control unit 33 and the fifth control signal of the third control unit 35 to perform a column control signal. The first control signal or the third control unit of the input buffer unit 31 is composed of a column control signal output unit 201 and an inverter 197, 198, 203 for outputting a control signal (C4) for outputting And a pre-charge control signal output unit 202 for outputting the pre-charge control signal C3 by performing a logical operation on the sixth control signal of (35).

The driving method of the SWL ferroelectric memory device of the present invention configured as described above is as follows.

31 is an output waveform diagram of each part of the power-up detection unit of the present invention.

First, it is assumed that the chip enable signal CSBpad signal is fixed to the ground voltage (Ground Voltage) so that the chip is in the enabled state in all sections during power-up.

First, each node N1 to N6 is in a ground state without power being applied before t1.

[t1-t2]

In the period t1 to t2, the power is turned on from the ground state to the Vcc state.

The signal of the node N1 rises to the pull-up of the PMOS transistor 219 but the slope becomes gentle.

The signal of the node N2 is delayed and gradually rises.

The signal at node N4 is amplified to become the ground voltage.

Since the NMOS transistor 230 is off, the signal of the node N5 rises to a floating state, and the signal of the node N6 also rises due to the influence of the signal of the node N4.

[t2-t3]

When the signal voltage of the node N2 rises above the threshold voltage Vtn and turns on the NMOS transistor 221, the amplification unit operates so that the signal of the node N1 gradually falls, and the signal of the node N4 is the inverter 226. The signal of the nodes N5 and N6 maintains Vcc without rising to the voltage to invert the output of the circuit.

[t3 and above]

When the signal of the node N4 continues to rise and passes the threshold value Vt of the inverter 226, the signals of the nodes N5 and N6 are inverted from high to low to turn off the NMOS transistor 224 to turn off the amplifier 234. Disable).

The node N4 rises to Vcc by the current of the PMOS transistor 225 and the power down signal goes low.

Therefore, the CSBpad signal is fixed low, but the power-up signal, which is one of the input signals, is changed from the disabled state high to the enabled state low in the input buffer unit 31.

Referring to the operation output waveform of the global control pulse generator of the present invention using the power-up detection as described above is as follows.

FIG. 31 is an operation timing diagram of the global control pulse generator of the first embodiment of the present invention, FIG. 32 is an operation timing diagram of the global control pulse generator of the second embodiment of the present invention, and FIG. 33 is a global control pulse of the third embodiment of the present invention. 34 is an operation timing diagram of the generator, and FIG. 34 is an operation timing diagram of the global control pulse generator of the fourth embodiment of the present invention.

The operation of the global control pulse generator of the present invention operates somewhat differently according to the configuration of the cell array and the X, Z-address toggle or the Y-address toggle.

That is, the operation of the global control pulse generator in the case where the cell array configuration is configured as shown in FIG. 8 or 9 and the Y-address is toled is the same as in FIG. 31, which is the first embodiment.

The CSBpad signal, which is a chip enable signal, is externally applied through the chip enable pin. Since the chip enable signal makes the "low" state enabled, the CSBpad signal is "high" to "low". low) "is enabled.

Therefore, in order to perform a new read operation or a write operation, a disable period to the "high" state is required.

First, when FIG. 31 is divided into t1 to t15 sections, the change state of the signal for each section is described as follows.

It is assumed that the CSBpad signal is activated low from the start point of the t1 section to the end point of the t14 section and becomes inactive at the start of the t15 section.

In addition, while the CSBpad signal is active, the X and Z addresses do not change, but the Y address assumes that the transition occurs at the start point of the t7 section and the start point of t11, respectively.

The Y-ATD senses a change in the Y address and generates a high pulse during the t8 section at t7 and the t12 section at t11.

Here, S1 and S2 are pulses used to form the basic waveforms of the word lines SWL1 and SWL2 of the SWL cell.

First, in the t1 period, the CSBpad signal is enabled from high to low.

At this time, the X, Y, Z-address keeps the state before t1, and if the Y-address transitions at the time t7 starts, the Y-ATD signal becomes high from t7 to t8.

When the Y-address transitions at the time t11 starts, the Y-ATD signal goes high from t11 to t12.

The S1 signal remains "low" until the t1 interval, remains "high" from the t2 to t3 intervals, becomes "low" in the t4 interval, becomes "high" at the t5 interval, and at t6. The state is "low" until t15.

At this time, the S2 signal remains high for a period from t3 to t4, and otherwise goes to "low".

The C1 signal, which is a basic signal for controlling the signal flow between the main cell bit line and one input / output terminal of the sense amplifier, becomes Low only in the t3 section, and goes high in other sections.

Therefore, the signal flow between the main cell bit line and one input / output terminal of the sense amplifier is cut off only in the period t3.

The C2 signal, which is a basic signal for controlling the signal flow between the reference cell bit line and the other input / output terminal of the sense amplifier, generates a pulse that goes low for a period t3 to t14.

Therefore, the signal flow between the main cell bit line and the other input / output terminal of the sense amplifier is interrupted during the period t3 to t14.

The C4 signal, which adjusts the signal transfer between the main cell bit line and the external data bus and adjusts the pull-up of the reference cell bit line, becomes "high" from t4 to t14 and the point at which the CSBpad signal is disabled (end point of the interval t14). Transitions to low again.

Therefore, it is possible to adjust the signal transmission of the bit line of the main cell and the external data bus only during the period t4 to the period t14, and it is possible to adjust the pullup of the reference cell bitline.

The P2 signal, which prevents interference by other pulses in the section where S1 and S2 generate the normal pulse, becomes "high" from the section t2 to the section t5 where the signals S1 and S2 become high, and at the time t6 starts It transitions back to the low state.

The signal C3, which precharges the low voltages of the main cell and the reference cell bit line before S1 and S2 is activated, is kept high until the period t1, and then transitions to the low state when t2 starts. The pre-charge is deactivated by maintaining the "low" state for the period t14, and the state transitions to the "high" state again in an area other than this period (the time when the CSBpad signal is disabled).

The SAN signal (a preliminary signal for making a SAN_C signal, which is a signal for controlling a transistor composed of NMOS to operate a sense amplifier of the sense amplifier & input / output control unit), is kept low until a period t2. It transitions to the high state at the start and transitions to the low state when the CSBpad signal is disabled.

The SAP signal (a preliminary signal of the SAP_P signal, which is a signal for controlling a transistor configured by PMOS for operating the sense amplifier and the sense amplifier of the input / output control unit) changes opposite to the SAN signal. That is, while the previous state is maintained high until the period t2, the state transitions to the low state at the time t3 starts and transitions to the high state when the CSBpad signal is disabled.

As described above, when the Y-address is changed while the CSDpad signal is activated, the Y-ATD is generated. In the recording mode, the S1 and S2 signals are both in the "high" state, that is, in the period t2 to t3. Logic "0" is written to the cell. The logic " 1 " is written in the corresponding cell during the section in which only one of the S1 or S2 signals is in the " high " state, that is, the section t4 and t5.

Meanwhile, the operation of the global control pulse generator in the case where the cell array configuration is configured as shown in FIG. 8 or 9 and the X, Z-address is toled is the same as that in FIG. 32 according to the second embodiment.

The entire timing section will be described by dividing the section from t1 to t21 sections, and it is assumed that the X and Z-addresses change at the starting points of the t7 section and the t14 section, respectively.

That is, since the operation of the global control pulse generator in the X, Z-address toggle is similar to the operation in the Y-address toggle, only the parts that perform different operations are as follows.

In FIG. 31, since the Y-ATD signal becomes high at the time when the Y-address changes, while in the second embodiment of the present invention, it is assumed that the X, Z-address is changed at the start of the t7 and t14 sections, The Z-ATD signal becomes "high" in the t7 and t14 sections and "low" in the remaining sections.

In the global control pulse generator, when the X and Z addresses change, the X and Z-ATD signals are combined with the CSBpad signal.

Therefore, if there are "high" state sections t7 and t14 of the X and Z-ATD signals, the global control pulse generator recognizes that the CSBpad signal is enabled again during the period.

Therefore, in the global control pulse generator, all output signals are generated again so that the corresponding X and Z-addresses are normally accessed.

The S1 and S2 signals are started after a predetermined period (t1) when the CSBpad signal is enabled in a "low" state and also starts after a predetermined period (t8 and t15) when the X, Z-ATD signal transitions to "low". .

That is, the S1 signal maintains a "high" state in the t2-t3 section, the t5 section, the t9-t10 section, the t12 section, the t16-t17 section, and the t19 section, and the "low" state in the remaining sections. The S2 signal maintains the "high" state in the t2-t4 section, the t9-t11 section and the t16-t18 section, and the "low" state in the remaining sections.

The C1 signal transitions to Low during one period (t3, t10, t17) in the period (t2-t3, t9-t10, t16-t17) in which both signals S1 and S2 are high, and then transitions back to "high" again. do.

As described above, the C2 signal transitions from the high state to the low state when the C1 signal transitions to the low state, and transitions from the low state to the high state when the X, Z-ATD signal transitions to the high state.

The C4 signal transitions from high to low when the C2 signal transitions to high, and transitions from high to low when the X and Z-ATD signals transition to high.

The P2 signal transitions from low to high when the S1 and S2 signals all transition high, and transitions from high to low when the S1 and S2 signals all transition low.

The C3 signal transitions from high to low when the S1 and S2 signals both transition to high, and transitions from low to high when the X and Z-ATD signals transition to high.

The SAN signal and the SAP signal are shifted in opposite states at the time when the C2 signal changes.

Therefore, a logic "0" is written in the corresponding cell in a section in which both S1 and S2 signals are "high", that is, in a section of t2-t3, t9-t10, t16-t17, and the like. Logic " 1 " is written in the corresponding cell in a section in which only one of the S1 or S2 signals is "high", that is, a section of t4-t5, t11-t12, t18-t19, and the like.

Meanwhile, the operation of the global control pulse generator in the case where the cell array configuration of the present invention is as shown in FIG. 10 and the Y-address is toggled is as shown in FIG.

That is, the waveform of FIG. 33 is divided into t1 to t15 sections to explain the change state of the signal for each section.

10 is composed of a bit line and a bit bar line and does not require a reference cell, thus eliminating the need for the C1 and C2 signals.

The CSBpad signal is activated "low" from the start of t1 to the end of t14 and deactivated high at the start of t15. The X and Z-addresses do not change while the CSBpad signal is active. The address assumes that transitions occur at the beginning of t7 and at the beginning of t11, respectively.

Then, the Y-ATD signal detects the change in the Y-address and becomes "high" during the t8 section and the t12 section and the t12 section, respectively.

Since the S1 and S2 signals are used to form the basic waveforms of the SWL1 and SWL2 split word lines of the SWL memory cell, the S1 signal is generated as a "high" pulse in the t2-t3 and t5 sections, and S2 The signal is generated as a pulse "high" in the period t2-t4.

The C4 signal is used to adjust the signal transmission of the bit line and the external data bus of the main cell and to adjust the full-up of the bit line and the bit bar line of the main cell. It transitions to "high" in the "low" state and transitions back to the "low" state at the time when the CSBpad signal is disabled (before t15 starts).

Accordingly, signal transmission between the bit line and the data line of the main cell is possible during the period t4 to period t14.

The P2 signal is a signal that maintains the "high" state in the t2-t5 section, in which the S1 and S2 signals generate a normal pulse (high state). During this period, other signals do not disturb the normal pulse of the S1 and S2 signals. Interlock function to prevent this.

That is, the signal maintains a high state between the sections t2 to t5 where the signals S1 and S2 generate a normal signal and prevents other signals from interfering with the normal signals of the signals S1 and S2 during this period.

The C3 signal is for pre-charging to be deactivated in the t2-t4 section and pre-charging is activated in the other section. The signal C3 is maintained high until the t1 section and then transitions to the low state at the start of the t2 section. And again transitions to a high state when the CSBpad signal is disabled.

The SAN signal is a preliminary signal for making the SAN_C signal that controls the NMOS transistor to operate the sense amplifier and the sense amplifier of the input / output controller. The SAN signal is “low” until the period t2, and at the time t3 starts. Transitions to " high " state and transitions back to " low " state at the time when the CSBpad signal is disabled.

The SAP signal is a preliminary signal of the SAP_P signal, which is a signal for controlling the PMOS transistor in order to operate the sense amplifier and the sense amplifier of the input / output controller, and is reversed from the SAN signal. In other words, while maintaining the "high" state until the section t2, the state transitions to the "low" state at the time t3 starts and transitions to the "high" state again when the CSBpad signal is disabled.

Accordingly, logic "0" is written in the corresponding cell during the period in which both the S1 and S2 signals are in the "high" state, that is, in the period t2 to the period t3. The logic " 1 " is written in the corresponding cell during the section in which only one of the S1 or S2 signals is in the " high " state, that is, the section t4 and t5.

Meanwhile, the operation of the global control pulse generator in the case where the cell array configuration is the same as that of FIG. 10 and the X, Z-address is toe is the same as that of FIG. 34 of the second embodiment.

That is, since the operation of the global control pulse generator in the X, Z-address toggle is similar to the operation in the Y-address toggle, only the parts that perform different operations are as follows.

In FIG. 33, the Y-ATD signal becomes high at the time when the Y-address changes, whereas in the case of X, Z-address changes in FIG.

In the global control pulse generator, when the X and Z addresses change, the X and Z-ATD signals are combined with the CSBpad signal.

Therefore, if there are high state sections t7 and t14 of the X and Z-ATD signals, the global control pulse generator recognizes that the CSBpad signal is high during the period.

Therefore, in the global control pulse generator, all output signals are generated again so that the corresponding X and Z-addresses are normally accessed.

That is, the signals S1 and S2 are started after a predetermined period (t1) when the CSBpad signal is enabled in a "low" state, and after a predetermined period (t8, t15) at the time when the X, Z-ATD signal transitions to "low". Begins.

The C4 signal transitions from high to low when the S1 signal transitions to "low" and the S2 signal "high", and transitions from high to low when the X and Z-ATD signals transition to high.

The P2 signal transitions from low to high when the S1 and S2 signals all transition high, and transitions from high to low when the S1 and S2 signals all transition low.

The C3 signal transitions from high to low when the S1 and S2 signals both transition to high, and transitions from low to high when the X and Z-ATD signals transition to high.

The SAN signal and the SAP signal change after a predetermined time delay at the time when both the S1 and S2 signals are "high", and then transition to the opposite state at the time when the A, Z-ATD signal is transitioned to "high".

Therefore, a logic "0" is written in the corresponding cell in a section in which both S1 and S2 signals are "high", that is, in a section of t2-t3, t9-t10, t16-t17, and the like. Logic " 1 " is written in the corresponding cell in a section in which only one of the S1 or S2 signals is "high", that is, a section of t4-t5, t11-t12, t18-t19, and the like.

As described above, the SWL ferroelectric memory device and the driving circuit of the present invention have the following effects.

First, since the ferroelectric memory device is configured to have a cell plate function by using a split word line instead of a separate plate line, the integration can be improved, and a plate line control signal is not required for double-read data read and write operations. The efficiency as a storage element is improved.

Second, since the reference cell has to be operated more than the main memory cell because the reference cell is configured to be used for the read operation of the main memory more than several hundred times in the state where the characteristics of the ferroelectric film are not completely secured. The deterioration characteristics of the cell deteriorated sharply and the reference voltage was not stable. However, since the present invention significantly lowers the ratio of the reference cell to the corresponding main memory cell, deterioration characteristics of the reference cell can be prevented.

Third, although only the CSBpad signal is used as a signal for enabling the ferroelectric memory, the present invention uses the X, Y, and X-ATD signals in addition to the CSBpad signal, so that the fast column access mode is used. It can operate the memory operation efficiently such as improve the chip access speed and performance.

That is, the change of address is classified into the case of changing only X, Z-address only and the case of only Y-address changing, and when it is enabled by CSBpad signal and the operation is not finished yet, X, Y, Z -Do not disturb the operation even if the address comes in.

When only the X and Z addresses are changed, since there is no valid data latched in the sense amplifier, an operation such as enabling the CSBpad signal can be implemented using the X and Z-ATD signals, and only the Y address is changed. In this case, since the split word lines SWL1 and SWL2 corresponding to the row address are not changed, the data latched to the sense amplifier can be read. In the write mode, the write operation is normally performed using the Y-ATD signal. Can be lost.

Claims (31)

An SWL driver which drives the split word line SWL, A cell array for storing data; And a core unit having a sense amplifier block for sensing data and a bart line control block for controlling bit lines, wherein the cell array unit is arranged at left and right sides around a single SWL driver, and the core unit SWL ferroelectric memory device, characterized in that disposed between the cell array portion in the vertical direction of each cell array portion. The method of claim 1, And the cell array unit comprises a main cell block for substantially writing data and a reference cell block for storing a reference value for reading data. The method of claim 1, The main cell sub-block consists of a plurality of even column units, and the reference cell sub-block consists of two column units. A plurality of main cell sub-blocks and reference cell sub-blocks constitute one cell array unit SWL ferroelectric memory device characterized in that the configuration. The method of claim 1, The cell array unit includes a plurality of split word lines SWLs arranged in one direction at predetermined intervals; A plurality of bit lines arranged at regular intervals in a direction perpendicular to each of the SWLs; And a ferroelectric unit memory cell formed in each pair by pairing the two adjacent SWLs and two adjacent bit lines as a pair. The method of claim 4, wherein The ferroelectric unit memory cell may include a first transistor having a gate electrode connected to a first SWL of the pair of SWLs, and a source electrode connected to a first bit line of a pair of bit lines; A second transistor having a gate electrode connected to a second SWL of the pair of SWLs, and a source electrode connected to a second bit line of the pair of bit lines; A first capacitor connected to a drain electrode of the first transistor and a second electrode connected to the second SWL; And a second capacitor connected to the drain electrode of the second transistor and the second electrode connected to the first SWL. The method of claim 4, wherein The plurality of bit lines are divided into a plurality of sub-blocks, each sub-block being a bit line of a plurality of columns for a main cell for storing data and a bit of two columns for a reference cell for generating a reference voltage required for data sensing. SWL ferroelectric memory device, characterized in that consisting of lines. The method of claim 1, The cell array configuration may include: a plurality of split word lines SWL arranged in one direction at regular intervals; A plurality of bit lines and bit bar lines alternately arranged at regular intervals in a direction perpendicular to the respective SWLs; And unit cells formed in each pair by pairing two adjacent SWLs and a pair of adjacent bit lines and bit bar lines. The method of claim 7, wherein A first transistor having a gate electrode connected to a first SWL of the pair of SWLs, and a source electrode connected to a bit line; A second transistor having a gate electrode connected to a second SWL of the pair of SWLs, and a source electrode connected to a bit bar line; A first capacitor connected to a drain electrode of the first transistor and a second electrode connected to a second SWL; And a second electrode connected to the drain electrode of the second transistor, and the second electrode connected to the first SWL. A final X decoder unit for decoding the input X, Z-address to control a corresponding cell array block to operate; A global control pulse generator for outputting control pulses for data recording and reading in accordance with an externally input CSBpad signal; A local control pulse generator for inputting a control pulse of the global control pulse generator to output a control signal for data recording and reading; An SWL cell array block storing data; An SWL driver for driving an SWL cell array block according to control signals of the final X decoder and the local control pulse generator; A Y-address decoder unit for decoding and outputting an externally input Y-address signal; A column controller for controlling a column according to a control signal of the local control pulse generator and a decoded signal of the Y-address decoder; And a sensing and data input / output controller configured to sense data of the SWL cell array block and write data to the SWL cell array block according to the control signal of the local control pulse generator and the control of the column controller. Driving circuit of the memory device. The method of claim 9, The global control pulse generator may include: an input buffer unit configured to receive a signal including an input CSBpad signal and generate first and second synchronization signals; A first control signal for adjusting an enable timing of a sense amplifier by inputting a first synchronization signal of the input buffer unit, a column select enable timing, and a pull-up of a bit line of a reference cell; A first control unit for outputting a second control signal for adjustment and a third control signal for generating an input signal of the SWL driver and other control signals, respectively; A basic waveform generation signal S1 of SWL1 and a basic waveform generation signal S2 of SWL2 for the pair of SWLs of the SWL driver by inputting a third control signal of the first control unit, and the signals S1 and S2; Generating a fourth control signal, which is a basic pulse signal for adjusting the activation period of the signal, and a pulse signal P2 having improved driving ability of the fourth control signal, and outputting the pulse signal P2 to the local control pulse generator. A second control unit; All signal signals except the basic waveform generation signal S1 of SWL1 and the basic waveform generation signal S2 of SWL2 by inputting the first and second synchronization signals of the input buffer unit and the fourth control signal of the second control unit. When the CSBpad signal is disabled when the fifth control signal for adjusting to be synchronized with the CSBpad signal and the basic waveform generation signal S1 of the SWL1 and the basic waveform generation signal S2 of the SWL2 are enabled when the signal is enabled, And disabling the disable to output a sixth control signal extending the enable state until the basic waveform generation signal S1 of the SWL1 and the basic waveform generation signal S2 of the SWL2 are normally completed. 3 control unit; Enable the n-MOS device of the sense amplifier by inputting the fifth and sixth control signals of the third control unit, the first, second and third control signals of the first control unit and the first synchronization signal of the input buffer unit. The signal SAN and the enable signal SAP of the p-MOS device, the control signal C1 for connecting the bit line of the main cell block and the first input / output node of the sense amplifier, and the reference cell block. A control signal C2 for connecting the bit line and the second input / output node of the sense amplifier to each other, and a control signal for adjusting the bit line of the main cell and the bit line of the reference cell and the low voltage precharge of the sense amplifier node ( And a fourth controller for outputting a control signal C4 for adjusting the column select enable timing and the pull-up of the bit line of the reference cell. Driving circuit. The method of claim 10, The input buffer unit detects and outputs a state of power; A first NOR gate for performing a logic operation on an X, Z-ATD signal, a CSBpad signal, and an output signal of the power-up detection unit, which are externally input; A first inverter for inverting the output of the first NOR gate to output the second synchronization signal; And a second inverter for inverting the output of the first inverter and outputting a first synchronous signal. The method of claim 11, The power-up detection unit detects and outputs a power voltage rise, and outputs a voltage rise detection unit; An amplifier for comparing and amplifying and outputting an output signal of the power supply voltage rise detector and a power supply voltage; A feed-back unit which feeds back the output of the amplifier unit and outputs a signal indicating a stable state and an unstable state of a power supply voltage; And a power-supply output unit for directing the driving capability of the feed-back output and outputting it to the input buffer unit. The method of claim 10, The first controller may include a first delay unit configured to output first and second delay signals obtained by dividing the first synchronization signal of the input buffer unit into different time periods and delay the first synchronization signal, and output the first delay signal as a first control signal; , A third inverter for inverting the second delay signal of the first delay; A first NAND gate for performing a logic operation on the first synchronization signal of the input buffer unit and the output signal of the third inverter, and outputting a second control signal; And a fourth inverter for inverting the output of the first NAND gate and outputting a third control signal. The method of claim 10, The second controller may include a second delay unit configured to output third and fourth delay signals obtained by dividing the falling edge of the third control signal output from the first controller into different time periods and delaying the divided edges; A second NOR gate for performing a logic operation on the fourth delay signal of the second delay unit and the third control signal of the first control unit; A third delay unit configured to delay a rising edge of the output signal of the second NOR gate for a predetermined time; A fifth inverter for inverting the third control signal; A second NAND gate configured to logically perform an output of the fifth inverter, an output signal of the second NOR gate, and an output of the third delay unit, and output a fourth control signal; A third NAND gate for performing a logic operation on an output of the fifth inverter, a fourth delay signal of the second delay unit, and an output of the second NAND gate; A fourth delay unit configured to delay a rising edge of the third NAND gate output for a predetermined time; A fourth NAND gate for performing a logic operation on a third delay signal of the second delay unit, an output of the third NAND gate, and an output of the second NAND gate; A fifth delay unit configured to delay a rising edge of the fourth NAND gate output for a predetermined time; An S1 signal output unit configured to perform a logic operation on the output of the fourth delay unit and the output of the second NAND gate, and output a basic waveform generation signal S1 of the SWL1; An S2 signal output unit configured to logically perform an output of the second NAND gate and an output of the fifth delay unit, and output a basic waveform generation signal S2 of the SWL2; And a pulse signal output unit for outputting a pulse signal (P2) by increasing the driving capability of the signal of the second NAND gate. The method of claim 10, The third control unit inputs the first synchronization signal of the input buffer unit and the fourth control signal of the second control unit to convert the high pulse of the pulse signal P2 output from the second controller to the CSBpad signal as “low”. A signal extension that extends while enabled, A sixth delay unit for delaying a rising edge of the output signal of the signal extension unit for a predetermined time; A fifth NAND gate configured to perform a logic operation on the inverted signal of the fourth control signal of the second control unit and the second synchronization signal of the input buffer unit, and output a sixth control signal; And a control signal output unit configured to perform a logical multiplication of the output of the sixth delay unit and the output of the fifth NAND gate to output a fifth control signal. The method of claim 10, The third control unit includes a seventh delay unit for delaying the rising edge of the fourth control signal of the second control unit for a predetermined time; A sixth NAND gate configured to logically operate an inverted signal of the fourth control signal of the second control unit and a second synchronization signal of the input buffer unit, and output a sixth control signal; And a control signal output unit configured to output a fifth control signal by performing a logic operation on an output of the seventh delay unit and an output of the sixth NAND gate. The method of claim 10, The third control unit inputs the first synchronization signal of the input buffer unit and the fourth control signal of the second control unit to convert the high pulse of the pulse signal P2 output from the second controller to the CSBpad signal as “low”. A signal extension that extends while enabled, An eighth delay unit configured to delay a rising edge and a falling edge of the output signal of the signal expansion unit for a predetermined time; A seventh NAND gate configured to perform a logic operation on the inverted signal of the fourth control signal of the second control unit and the second synchronization signal of the input buffer unit 31 to output a sixth control signal; And a control signal output unit configured to logically multiply the output of the eighth delay unit and the output of the fifth NAND gate to output a fifth control signal. The method of claim 10, The fourth control unit may be configured to logically operate the first control signal of the first control unit and the fifth control signal of the third control unit to enable the enable signal SAN of the NMOS device of the sense amplifier and the PMOS device of the sense amplifier. A sense amplifier control signal output unit for outputting a signal SAP, A control signal C1 and a reference cell for logically operating the third control signal of the first control unit and the fifth control signal of the third control unit to connect the bit line of the main cell block and the first input / output node of the sense amplifier. A bit line switching signal output unit for outputting a control signal C2 for connecting the bit line of the block and the second input / output node of the sense amplifier, A column control signal output unit configured to perform a logic operation on the second control signal of the first control unit and the fifth control signal of the third control unit to output a C4 signal which is a column control signal; SWL ferroelectric memory device characterized in that it comprises a pre-charge control signal output unit for outputting a pre-charge control signal (C3) by performing a logic operation on the first synchronization signal of the input buffer unit or the sixth control signal of the third control unit. Driving circuit. The method of claim 18, The bit line switching signal output unit performs a logic operation on a third control signal of the first control unit and a fifth control signal of the third control unit to connect a bit line and a first input / output node of the sense amplifier (C1). And a control signal (C2) for connecting the bit bar line and the second input / output node of the sense amplifier. The method of claim 9, The global control pulse generator may include: an input buffer unit configured to receive a signal including a CSBpad signal input from the outside and generate first and second synchronization signals; A low voltage operation and noise prevention unit for receiving a first synchronization signal and a feedback signal of the input buffer unit and outputting a low voltage detection signal for preventing operation during low voltage and a noise removing signal for filtering out noise of the first synchronization signal; A first control signal for adjusting an enable timing of a sense amplifier by inputting the noise canceled signal when the normal power supply voltage is supplied from the low voltage operation and noise prevention unit, and adjusting a column selection enable timing and adjusting a reference cell A first control unit for outputting a second control signal for adjusting a pull-up of the bit line and a third control signal for generating an input signal and other control signals of the SWL driver; A basic waveform generation signal S1 of SWL1 and a basic waveform generation signal S2 of SWL2 for the pair of SWLs of the SWL driver by inputting a third control signal of the first control unit, and the signals S1 and S2; Generating a fourth control signal, which is a basic pulse signal for adjusting the activation period of the pulse signal, and a pulse signal P2 having improved driving ability of the fourth control signal, respectively, and the fourth control signal is generated by the low voltage operation and noise prevention unit. A second controller which outputs a feedback signal and outputs the pulse signal P2 to a local control pulse generator; All signal signals except the basic waveform generation signal S1 of SWL1 and the basic waveform generation signal S2 of SWL2 by inputting the first and second synchronization signals of the input buffer unit and the fourth control signal of the second control unit. When the CSBpad signal is disabled when the fifth control signal for adjusting to be synchronized with the CSBpad signal and the basic waveform generation signal S1 of the SWL1 and the basic waveform generation signal S2 of the SWL2 are enabled when the signal is enabled, Outputting a sixth control signal for extending the enable state until the basic waveform generation signal S1 of SWL1 and the basic waveform generation signal S2 of SWL2 are normally completed by blocking the disable. A third control unit; The enable signal (SAN) and the p-MOS device of the n-MOS device of the sense amplifier by inputting the fifth, sixth and third control signals of the third controller and the first, second, and third control signals of the first controller. Enable signal SAP, a control signal C1 for connecting the bit line of the main cell block and the first input / output node of the sense amplifier, and the second input of the bit line and sense amplifier of the reference cell block. The control signal C2 for connecting the output / output nodes to each other, the control signal C3 for adjusting the low voltage precharge of the bit line of the main cell and the bit line of the reference cell and the sense amplifier node, and a column select enable time And a fourth control unit for outputting a control signal (C4) for adjusting pull-up of the bit line of the reference cell. The method of claim 20, The low voltage operation and noise removing unit comprises: an eighth delay unit configured to delay a first synchronization signal of the input buffer unit for a predetermined time; A ninth delay unit configured to delay the rising edge of the first synchronization signal of the input buffer unit; A sixth and seventh inverter unit inverting the outputs of the eighth and ninth delay units, respectively; A first NMOS transistor having a gate electrode and a source electrode commonly connected to a power supply terminal Vcc, and a drain electrode connected to an output terminal of the sixth inverter; A second NMOS transistor connected to an output terminal of the sixth inverter and a source electrode connected to the seventh inverter and outputting a signal to a drain electrode; A first PMOS transistor having a gate electrode grounded and a source electrode and a drain electrode connected to a power supply terminal and a drain electrode of a second NMOS transistor, respectively; An eighth inverter for inverting a fourth control signal fed back from the second controller; A sixth NAND gate for logically calculating the output of the second NMOS transistor and the output of the eighth inverter; A ninth inverter for inverting the output of the sixth NAND gate; A seventh NAND gate configured to perform a logic operation on the first synchronization signal of the input buffer unit and an output of the ninth inverter, and output a precharge adjustment pulse for precharge adjustment of the sense amplifier; And a tenth inverter configured to invert the output of the ninth inverter to output a low voltage detection and noise removal signal. The method of claim 20, The low voltage operation and noise removing unit may include a tenth delay unit configured to delay the first synchronization signal of the input buffer unit for a predetermined time; An eleventh delay unit configured to delay the rising edge of the first synchronization signal of the input buffer unit; An eleventh and twelfth inverter unit inverting the outputs of the tenth and eleventh delay units, respectively; A third NMOS transistor having a gate electrode and a source electrode commonly connected to a power supply terminal Vcc, and a drain electrode connected to an output terminal of the eleventh inverter; A thirteenth inverter for inverting a fourth control signal fed back from the second controller; A fourth NMOS transistor connected to an output terminal of the thirteenth inverter and a source electrode connected to an output terminal of the twelfth inverter; A fifth NMOS transistor connected to an output terminal of the eleventh inverter and a source electrode connected to a drain terminal of the fourth NMOS transistor and outputting a signal to the drain electrode; A second PMOS transistor having a gate electrode grounded and a source electrode and a drain electrode connected to a power supply terminal and a drain electrode of the fourth NMOS transistor, respectively; A sixth NMOS transistor for turning on / off an output of the fifth NMOS transistor to a ground terminal according to the feedback signal; A fifteenth, sixteenth, seventeenth inverter for inverting the output of the fifth NMOS transistor and outputting a low voltage detection and noise removal signal; And an eighth NAND gate configured to perform a logic operation on the first synchronization signal of the input buffer unit and an output of the fifth NMOS transistor to output a pre-activation pulse for precharge adjustment of the sense amplifier. in. The method of claim 20, And a low voltage detector configured to input a first synchronization signal of the input buffer unit to sense a low voltage of the power supply so as not to operate at a low voltage instead of the low voltage operation and noise prevention unit. The method of claim 20, And a noise removing unit for removing noise of the first synchronizing signal instead of the low voltage operation and noise preventing unit. The method of claim 20, The first controller divides the low voltage detection and noise removal signals of the low voltage operation and the noise prevention unit into different time periods, and outputs fifth and sixth delay signals and outputs the fifth delay signal as a first control signal. Delay part, An eighteenth inverter for inverting the sixth delay signal output from the tenth delay unit; A ninth NAND gate configured to logically operate the low voltage detection and noise cancellation signal of the low voltage operation and noise prevention unit and the output signal of the eighteenth inverter, and output a second control signal; And a nineteenth inverter for inverting the output of the ninth NAND gate to output a third control signal. The method of claim 20, The fourth control unit may be configured to logically operate the first control signal of the first control unit and the fifth control signal of the third control unit to enable the enable signal SAN of the NMOS device of the sense amplifier and the PMOS device of the sense amplifier. A sense amplifier control signal output unit for outputting a signal SAP, A control signal C1 and a reference cell for logically operating the third control signal of the first controller and the fifth control signal of the third controller to connect the bit line of the main cell block and the first input / output node of the sense amplifier A bit line switching signal output unit for outputting a control signal C2 for connecting the bit line of the block and the second input / output node of the sense amplifier, A column control signal output unit configured to output a control signal C4 for outputting a column control signal by performing a logic operation on the second control signal of the first control unit and the fifth control signal of the third control unit; And a pre-charge control signal output unit configured to output a pre-charge control signal C3 by performing a logic operation on the preliminary activation pulse of the low voltage operation and the noise protection unit and the sixth control signal of the third control unit. Driving circuit of the memory device. The method of claim 26, The bit line switching signal output unit performs a logic operation on a third control signal of the first control unit and a fifth control signal of the third control unit to connect a bit line and a first input / output node of the sense amplifier (C1). And a control signal (C2) for connecting the bit bar line and the second input / output node of the sense amplifier. The method of claim 9, The global control pulse generator divides the enable section of the CSBpad signal input from the outside into t1-t14, and maintains the "high" state in the t2-t3 and t5 sections and maintains the "low" state in the remaining sections. 1 SWL basic waveform generation signal S1, a second SWL basic waveform generation signal S2 that maintains a "high" state in the period t2-t4 and a "low" state in the remaining period; a control signal C1 for connecting the bit line of the main cell and the first node of the sense amplifier, which transitions to “low” in a period t3 and maintains a “high” state in the remaining periods; a control signal C2 for connecting the bit line of the reference cell and the second node of the sense amplifier to maintain the "low" state in the interval t3-t14 and the "high" state in the remaining interval, the control signal C4 for adjusting the column select enable timing and the pull-up of the bit line of the reference cell to maintain the "high" state in the t4-t14 period and to maintain the "low" state in the remaining period. , a pulse signal P2 for adjusting an activation period of the first and second basic waveform generating signals S1 and S2 which are maintained in a "high" state in a period t2-t5 and a "low" state in the remaining period, a control signal C3 for adjusting the low voltage precharge of the bit line of the main cell, the bit line of the reference cell, and the sense amplifier node, which is maintained in the "low" state in the t2-t14 period and in the "high" state in the remaining intervals; a first enable signal SAP of the sense amplifier that maintains the "high" state in the t3-t14 interval and the "low" state in the remaining intervals; and a second enable signal SAN of a sense amplifier that maintains a "low" state in a period t3-t14 and a "high" state in the remaining periods. The method of claim 9, The global control pulse generator divides the enable section of the CSBpad signal input from the outside into t1-t20, and assumes that the X and Z-address signals transition from the start point of the t7 section and the t14 section. The first SWL basic waveform generating signal S1 which maintains the "high" state in the t2-t3, t5, t9-t10, t12, t16-t17, and t19 sections and the "low" state in the remaining sections. , a second SWL basic waveform generation signal S2 that maintains a "high" state in the t2-t4, t9-t11, and t16-t18 sections, and the "low" state in the remaining sections; a control signal C1 for connecting the bit line of the main cell and the first node of the sense amplifier which are transitioned to "low" in sections t3, t10 and t17 and remain "high" in the remaining sections, bit nodes of the reference cell transitioned from "high" to "low" at the end points of the sections t2, t10, t17, and "low" to "high" at the start points of the sections t7, t14, and the second node of the sense amplifier. Control signal C2 for connection, Column-select enable points that remain “high” in t4-t6, t11-t13, and t18-t20, and “low” in the remaining intervals, and the pull-pull of the bit line of the reference cell. control signal C4 for adjusting up), Adjust the activation periods of the first and second basic waveform generation signals S1 and S2 which are maintained in the "high" state in the t2-t5, t9-t12 and t16-t19 sections and in the "low" state in the remaining sections. Pulse signal P2 for Low voltage free of the bit line of the main cell, the bit line of the reference cell, and the sense amplifier node, which remain "low" in the t2-t6, t9-t13, and t16-t20 sections, and remain "high" in the remaining sections. A control signal C3 for adjusting the charge, a first enable signal SAP of the sense amplifier which maintains a "high" state in the t3-t6 section, the t10-t13 section and the t17-t20 section, and the "low" state in the remaining sections, SWL ferroelectric, characterized by outputting a second enable signal SAN of a sense amplifier that remains "low" in t3-t6, t10-t13, and t17-t20, and remains "high" in the remaining sections. Driving circuit of the memory device. An X, Y and Z address buffer unit for buffering externally input X, Y and Z address signals; An X, Y, and Z pre-decoder unit which preliminarily decodes and outputs the X, Y, and Z addresses output from the X, Y, and Z address buffer units; A final X decoder unit for decoding the X, Z pre-decoded signal of the X, Y, Z pre-decoder unit to control a corresponding cell array block to operate; A global control pulse generator for outputting control pulses for data recording and reading in accordance with an externally input CSBpad signal; A local control pulse generator for outputting a control signal according to the control pulse of the global control pulse generator; An SWL cell array block storing data; An SWL driver for driving an SWL cell array block according to control signals of the final X decoder and the local control pulse generator; A column controller for controlling a column according to a control signal of the local control pulse generator and a Y pre-decoded signal of the X, Y, and Z free decoders; And a sensing and data input / output controller configured to sense data of the SWL cell array block and write data to the SWL cell array block according to the control signal of the local control pulse generator and the control of the column controller. Driving circuit of the memory device. The method of claim 30, The global control pulse generator may include: an input buffer unit configured to receive a signal including a CSBpad signal input from the outside and generate first and second synchronization signals; A low voltage operation and noise prevention unit for receiving a first synchronization signal and a feedback signal of the input buffer unit and outputting a low voltage detection signal for preventing operation during low voltage and a noise removing signal for filtering out noise of the first synchronization signal; A first control signal for adjusting an enable timing of a sense amplifier by inputting the noise canceled signal when the normal power supply voltage is supplied from the low voltage operation and noise prevention unit, and adjusting a column selection enable timing and adjusting a reference cell A first control unit for outputting a second control signal for adjusting a pull-up of the bit line and a third control signal for generating an input signal and other control signals of the SWL driver; A basic waveform generation signal S1 of SWL1 and a basic waveform generation signal S2 of SWL2 for the pair of SWLs of the SWL driver by inputting a third control signal of the first control unit, and the signals S1 and S2; Generating a fourth control signal, which is a basic pulse signal for adjusting the activation period of the pulse signal, and a pulse signal P2 having improved driving ability of the fourth control signal, respectively, and the fourth control signal is generated by the low voltage operation and noise prevention unit. A second controller which outputs a feedback signal and outputs the pulse signal P2 to a local control pulse generator; All signal signals except the basic waveform generation signal S1 of SWL1 and the basic waveform generation signal S2 of SWL2 by inputting the first and second synchronization signals of the input buffer unit and the fourth control signal of the second control unit. When the CSBpad signal is disabled when the fifth control signal for adjusting to be synchronized with the CSBpad signal and the basic waveform generation signal S1 of the SWL1 and the basic waveform generation signal S2 of the SWL2 are enabled when the signal is enabled, Outputting a sixth control signal for extending the enable state until the basic waveform generation signal S1 of SWL1 and the basic waveform generation signal S2 of SWL2 are normally completed by blocking the disable. A third control unit; The enable signal (SAN) and the p-MOS device of the n-MOS device of the sense amplifier by inputting the fifth, sixth and third control signals of the third controller and the first, second, and third control signals of the first controller. Enable signal SAP, a control signal C1 for connecting the bit line of the main cell block and the first input / output node of the sense amplifier, and the second input of the bit line and sense amplifier of the reference cell block. The control signal C2 for connecting the output / output nodes to each other, the control signal C3 for adjusting the low voltage precharge of the bit line of the main cell and the bit line of the reference cell and the sense amplifier node, and a column select enable time And a fourth control unit for outputting a control signal (C4) for adjusting pull-up of the bit line of the reference cell.