JP2006092696A - Buffer circuit and semiconductor storage device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a write buffer circuit specially contriving a reduction of a leak current of a data writing circuit, and also to provide a semiconductor storage device using this circuit, as to the semiconductor storage device and its data writing circuit. <P>SOLUTION: This buffer circuit is provided with: a 1st arithmetic circuit in which a 1st control signal and the data are supplied and logically operated; a 2nd arithmetic circuit in which an output signal of the 1st arithmetic circuit and a 2nd control signal are supplied and logically operated; and a drive section in which the output of the 1st arithmetic circuit and an output of the 2nd arithmetic circuit are supplied to simultaneously interrupt output transistors of a final stage in accordance with the 2nd control signal. The leak currents of the output transistors at the interruption are reduced thereby. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device and a data write circuit thereof, and more particularly to a semiconductor memory device such as a DRAM in which leakage current of the data write circuit is reduced.

FIG. 9 shows an overall view of a memory, taking a conventional DRAM 200 as an example. Memory cell array (214, 216, 218, 220, 224, 226, 228, 230) in which a fixed number of memory cells arranged in a matrix are collected, and a sense amplifier for amplifying data stored in the memory cell array (213, 215, 217, 219, 221, 223, 225, 227, 229, 231) and write buffers (212, 222) for writing data to the sense amplifier are shown in the figure.
The write buffer (212, 222) is supplied with a control signal (write enable pulse) WEp to control the write timing.

FIG. 10 is a diagram illustrating a configuration example of a conventional DRAM 200. In the example of FIG. 10, only the circuits related to the three memory cells (MC11 to MC13) are extracted and shown for easy understanding.
Memory cells MC11-1 to MC13-1 are connected to a common word line WL1-1.
The memory cell MC11-1 is connected to the bit line BL1-1, the memory cell MC12-1 is connected to the bit line BL2-1, and the memory cell MC13-1 is connected to the bit line BL3-1.

Each of the memory cells MC11-1 to MC13-1 has an information storage capacitor C (C11, C12,...) And an access transistor Q (Q11, Q12,...).
The capacitor C is connected to the bit lines (BL1 to BL3) via the transistor Q, and the gate of the transistor Q is connected to the word line WL1.

The bit line BL1-1 is paired with the bit line XBL1-1, and each has a predetermined voltage (for example, half of the power supply voltage VDD (1/2 VDD)) by a precharge circuit (not shown) before performing write or read access. Voltage).
Similarly, the bit line BL2 is paired with the bit line XBL2-1 and the bit line BL3-1 is paired with the bit line XBL3-1, respectively, and both are precharged to the predetermined voltage before access.

  The sense amplifier SA1-1 is a bit line pair (BL1-1, XBL1-1), the sense amplifier SA2-1 is a bit line pair (BL2-1, XBL2-1), and the sense amplifier SA3-1 is a bit line pair. The voltage difference of (BL3-1, XBL3-1) is amplified.

The write circuit WC1-1 inputs a write signal to the bit line pair (BL1-1, XBL1-1) according to the control signal WA1-1 at the time of write access. That is, one of the write data line pairs (WD1-1, XWD1-1) is driven to the power supply voltage VDD and the other to the ground level GND by the write buffer, and this is driven according to the control signal WA1-1. XBL1-1).
Similarly, the write circuit WC2-1 inputs a write signal to the bit line pair (BL2-1, XBL2-1) according to the control signal WA2-1. The write circuit WC3-1 inputs a write signal to the bit line pair (BL3-1, XBL3-1) according to the control signal WA3.

FIG. 11 shows a specific circuit example of the write (buffer) circuits WC1-1 to WC3-1,.
The output of the AND circuit 251 to which the write enable pulse (WEp) and data (DATA) are input is connected to the gate of the PMOS transistor 256 and to the gate of the NMOS transistor 257. The source of the PMOS transistor 256 is connected to the power supply VDD, and the drain is connected to the drain of the NMOS transistor. The source of the NMOS transistor 257 is connected to the ground.
Further, DATA is connected to one input terminal of the AND circuit 253 via the inverter 252, and a write enable pulse (WEp) is input to the other input terminal. The output of the AND circuit 253 is connected to the gate of the PMOS transistor 258 and to the gate of the NMOS transistor 259. The source of the PMOS transistor 258 is connected to the power supply VDD, and the drain is commonly connected to the drain and drain of the NMOS transistor 259. The source of the NMOS transistor 259 is connected to the ground.

Next, the operation of the write buffer circuit 250 will be described with reference to FIGS.
A RAS (row address strobe) signal (not shown) is supplied from the outside, and transitions from the “L” level to the “H” level at time t41. The word line (WL1) takes a rise time due to the wiring capacity and the like, and transitions from the “L” level to the “H” level at time t42 and is activated. Next, after WL1 is activated, the sense amplifiers (SA1-1,...) Are activated.
When the word line is activated, the access transistor Q11A is turned on, and the voltage slightly varies corresponding to the charge stored in the memory capacitor C11A (time t42 to t43 in FIG. 12C).
At time t43, the sense amplifiers (SA1-1,...) Amplify the memory data read to the bit lines (BL-1,...). At time t44, a WEp pulse is input, and write bit data (DATA) is also supplied to the write buffer circuit 250.
The path of the output terminal WD1-1 will be described.
When WEp and DATA are both at the “H” level and the output of the AND circuit 251 is at the “H” level, the “H” level is input to the gate of the PMOS transistor 256, so that it is turned off. On the other hand, the NMOS transistor 257 is turned on because the "H" level voltage is input to the gate. As a result, the drain common connection point (output; WD1-1) becomes the “L” level.

The path of the output terminal XWD1-1 will be described.
On the other hand, since DATA is at “H” level, the output of inverter 252 is at “L” level, and the output of AND circuit 253 is at “L” level even if WEp at that time is at “H” level. This “L” level is input to the gate of the PMOS transistor and is turned on. However, the NMOS transistor 259 is turned off because the gate is at the “L” level. As a result, the drain output (XWD1-1) becomes “H” level.
That is, the level of the common drain output of the PMOS transistor 256 and the NMOS transistor 257 and the level of the common drain output of the PMOS transistor 258 and the NMOS transistor 259 are opposite to each other.
Next, the case where the DATA level is “L” will be described.
The path of the output terminal WD1-1 will be described.
Although WEp is at “H” level, since WEp is at “L” level, the output of the AND circuit 251 becomes “L” level. Since the “L” level voltage is input to the gate of the PMOS transistor 256, it is turned on. On the other hand, the NMOS transistor 257 is turned off because the “L” level voltage is input to the gate. As a result, the drain common connection point (output; WD1-1) becomes the “H” level.
The path of the output terminal XWD1-1 will be described.
Since DATA is at the “L” level and WEp is at the “L” level, the output of the inverter 252 is at the “H” level. Since WEp is at “L” level, the output of the AND circuit 253 is at “L” level. This “L” level is input to the gate of the PMOS transistor and is turned on. However, the NMOS transistor 259 is turned off because the gate is at the “L” level. As a result, the drain output (XWD1-1) becomes “H” level.

  Thus, when DATA is at “H” level, the common drain output of PMOS transistor 256 and NMOS transistor 257 is at “H” level, the common drain output of PMOS transistor 258 and NMOS transistor 259 is at “L” level, and DATA is At the “L” level, the common drain output of the PMOS transistor 256 and the NMOS transistor 257 and the common drain output of the PMOS transistor 258 and the NMOS transistor 259 are both at the “H” level.

As shown in FIG. 12D, when the WEp pulse becomes “H” level at time t44, the output of WD1-1 is “L” level in accordance with the “H” level or “L” level of DATA. On the other hand, the output of the XWD 1-1 becomes “H”, “L” level. Then, the sense amplifier SA1-1 amplifies according to the output level “H” or “L” level from the circuit 250. This waveform is shown at time t45 to t46 in FIG.
Since the circuit configuration of the sense amplifier SA1-1 is a latch circuit, even when WEp becomes “L” level, the voltage at the “H” level or “L” level when amplified at time t45 is held ( FIG. 12 (C)).

  After time t46, WEp becomes “L” level and writing is prohibited. Under these conditions, the outputs of the AND circuits 251 and 253 are both at the “L” level, the PMOS transistors 256 and 258 are in the ON state, and the NMOS transistors 257 and 259 are in the OFF state. However, even in this state, even if the write circuit path is interrupted, the PMOS transistors 256 and 258 are in the ON state, so that a leak current flows.

  When RAS changes from the “H” level to the “L” level at time t47, the word line WL also has a time constant, so it cannot rapidly transition to the “L” level, and at time t49, the “L” level. become.

  When the word line WL is deactivated, BL1-1 and XBL1-1 are also set to the precharge voltage (1 / 2VDD), for example, as shown at time t49.

  The transistor size of the final stage of the write buffer circuit 250 shown in FIG. 11 uses a large transistor size in order to drive a long write bus and invert the sense amplifier. In recent years, semiconductor shrinkage has progressed, and transistor leakage current has become a problem. Since the write buffer has a large transistor size, the leakage current also increases. The number of write buffers is the same as the number of I / Os. In the embedded memory used for the system-on-chip, the number of I / Os is very large, for example, 128 bits. For this reason, the total leakage current of the write buffer becomes enormous.

In order to avoid this, FIG. 13 shows an example in which a transistor switch is inserted between the power supply line and the logic circuit. A PMOS transistor for cutting current is arranged between the power supply line at the final stage of the write buffer circuit 300 and the bus driving transistor. The standby control signal STBp is input to the gate of this transistor. When it is desired to set the DRAM in a low leak state, the leak is cut by this transistor if STBp is set to “H” level.
The configuration and operation of the write buffer circuit 300 will be described.
FIG. 13 shows a specific circuit example of the write (buffer) circuits WC1-1 to WC3-1,.
The output of the AND circuit 301 to which the write enable pulse (WEp) and data (DATA) are input is connected to the gate of the PMOS transistor 306 and to the gate of the NMOS transistor 307. The source of the PMOS transistor 306 is connected to the drain of the PMOS transistor 310, and the drain is connected to the drain of the NMOS transistor 307. The source of the PMOS transistor 310 is connected to the power supply VDD, and STBp is input to the gate. The drain of the NMOS transistor 307 is commonly connected to the drain of the PMOS transistor 306, and this common connection point is connected to a sense amplifier. The source of the NMOS transistor 307 is connected to the ground.
Further, DATA is connected to one input terminal of the AND circuit 303 via the inverter 302, and a write enable pulse (WEp) is input to the other input terminal. The output of the AND circuit 303 is connected to the gate of the PMOS transistor 308 and to the gate of the NMOS transistor 309. The source of the PMOS transistor 308 is connected to the drain of the PMOS transistor 310, the drain is connected to the drain of the NMOS transistor 309, and is connected to the output sense amplifier. The source of the NMOS transistor 309 is connected to the ground.

The basic operation is the same as in FIG. 11 described above, but the PMOS transistor 310 is connected in parallel between the power supply VDD and the sources of the PMOS transistors 306 and 308, and the STBp control signal is input to the gate of the PMOS transistor 310. As a result, the operation of the write buffer circuit is turned ON / OFF.
That is, when the STBp pulse is at “H” level, the PMOS transistor 310 is turned off, so that the write buffer circuit 300 is completely turned off, and the leakage current of the write buffer circuit 250 of FIG. 11 is cut. become.
On the other hand, when the STBp pulse becomes “L” level, the PMOS transistor 310 is turned on, so that it has the same configuration as that of the circuit of FIG.

However, even if these types of write buffer circuits are used, the write buffer circuit needs to pass a large current during writing. For this reason, if the size of the PMOS transistor used for the switch is reduced in order to increase the current reduction effect, the current driving capability is insufficient and the circuit speed is reduced. On the other hand, when the size of the switch transistor is increased, the layout size is increased and the current reduction effect is further reduced.
Japanese Patent Laid-Open No. 11-16355 JP-A-9-139084

  As described above, the conventional write buffer has the following problems. The transistor size in the final stage of the write buffer circuit uses a large transistor size to drive a long write bus and invert the sense amplifier. In recent years, semiconductor shrinkage has progressed, and transistor leakage current has become a problem. Since the write buffer circuit has a large transistor size, the leakage current also increases. The number of write buffer circuits is the same as the number of I / Os. In the embedded memory used for the system-on-chip, the number of I / Os is very large, for example, 128 bits. For this reason, the total leakage current of the write buffer circuit becomes enormous, and even if the chip is in an idle state, a very large amount of power is consumed.

Further, FIG. 13 shows an example in which a transistor switch is inserted between the power supply line and the logic circuit. However, there is a further problem even if this method is used. The write buffer circuit needs to pass a large current during writing. If the size of the PMOS transistor used for the switch is reduced in order to increase the current reduction effect, the current driving capability is insufficient and the circuit speed is reduced. On the other hand, when the size of the switch transistor is increased, the layout size is increased and the current reduction effect is further reduced.
As described above, when the conventional method is used, there is a problem that it is difficult to satisfy all the effects of size, speed, and current reduction.

  The present invention has been made in view of such circumstances, and an object thereof is to reduce a leakage current of a write buffer circuit of a memory. At the same time, an increase in the pattern layout size is suppressed, and a large leakage current is reduced without affecting the operation speed of the circuit.

  The present invention provides a first arithmetic circuit that is supplied with a first control signal and data and performs a logical operation, and a second operation that is supplied with an output signal of the first arithmetic circuit and a second control signal and performs a logical operation. A drive unit having a circuit and a plurality of transistors, wherein the output of the first arithmetic circuit and the output of the second arithmetic circuit are supplied, and simultaneously shuts off the output transistor in the final stage according to the second control signal; Have

  The present invention includes a first arithmetic circuit that is supplied with a first control signal and data and performs a logical operation, and a plurality of control signals different from the first control signal are input, and a second control signal according to the control signal A control signal generation circuit for generating a logic signal; a second operation circuit for performing a logical operation by receiving an output signal of the first operation circuit and a second control signal from the control signal generation circuit; and a plurality of transistors. In addition, the output of the first arithmetic circuit and the output of the second arithmetic circuit are supplied, and a drive unit that simultaneously shuts off the output transistor in the final stage according to the second control signal.

  The present invention provides a plurality of bit lines, a plurality of memory cells accessed through the plurality of bit lines, and signals held in the memory cells when the memory cells are accessed through the bit lines. A plurality of sense amplifiers that respectively amplify the signal of the bit line according to the write circuit, and a write circuit having a write buffer circuit that inputs a write signal to the bit line of the write target memory cell when writing to the memory cell; The write buffer circuit is supplied with a write enable signal and data and performs a logical operation, and an output signal of the first arithmetic circuit and a second control signal are supplied to perform a logical operation. A second arithmetic circuit and a plurality of transistors are provided, and an output of the first arithmetic circuit and an output of the second arithmetic circuit are supplied, and the second arithmetic circuit responds to the second control signal. And a drive unit for cutting off the output transistor of the final stage at the same time Te.

  The present invention relates to a plurality of bit lines, a plurality of memory cells accessed through the plurality of bit lines, and signals held in the memory cells when the memory cells are accessed through the bit lines. When writing to a plurality of banks each having a plurality of sense amplifiers that respectively amplify the signal of the bit line corresponding to each of the above and the memory cell of each bank, a write signal is applied to the bit line of the memory cell to be written. A write circuit having a write buffer circuit for input, wherein the write buffer circuit is supplied with a first control signal and a first arithmetic circuit for performing logical operation, and a plurality of bank switching control signals are input. A control signal generating circuit for generating a second control signal in response to the bank switching control signal; an output signal of the first arithmetic circuit; and the control signal generating circuit. A second arithmetic circuit which is supplied with a second control signal from the circuit and performs a logical operation; a plurality of transistors; and an output of the first arithmetic circuit and an output of the second arithmetic circuit are supplied; And a drive unit that simultaneously shuts off the output transistor in the final stage in response to the control signal 2.

  By using the present invention, the leakage current of the memory write buffer circuit can be reduced. In particular, when applied to a DRAM, it is possible to expect a large leakage current reduction effect while suppressing an increase in layout size and minimizing the influence on the operation speed of the circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing an outline of a configuration example of a semiconductor memory device according to an embodiment of the present invention.
The semiconductor memory device shown in FIG. 1 includes a memory cell array MA (14, 16, 18, 20, 24, 26, 28, 30) and a sense amplifier (Sense Amp) (13, 15, 17, 19, 21, 23). , 25, 27, 29, 31), write buffer circuits 12 and 22, other row decode circuits, bit line control circuits, data input / output circuits, R / W and EN (enable signals) not shown. And a control circuit for controlling each decoder circuit. The write buffer circuits 12 and 22 are supplied with two control signals WEP and STBp.

The above-described memory cell array MA (14, 16, 18, 20, 24, 26, 28, 30) includes memory cells MC11,..., MCmn arranged in a matrix of m rows and n columns.
The memory cells MCi1 to MCin in the i-th row (i represents an integer of 1 ≦ i ≦ m; the same applies hereinafter) are connected to a common word line WLi.
The memory cells MC1j to MCmj in the j-th column (j represents an integer of 1 ≦ j ≦ n; the same applies hereinafter) are connected to a common bit line pair (BLj, XBLj).
Memory cells MC11 to MCmn are an embodiment of the memory cell of the present invention.
Bit line pairs (BL1, XBL1) to (BLn, XBLn) are an embodiment of the bit lines of the present invention.

  The control circuit generates various control signals necessary for executing a read operation and a write operation on the memory cell array MA (14, 16, 18, 20, 24, 26, 28, 30), and generates a row decode circuit. , Supplied to the data input / output circuit and bit line control circuit. For example, in response to the selection signal R / W, whether to perform a read or write operation is selected, and when the enable signal EN is set to an active state, various control signals for executing the selected operation Is generated.

  The row decoding circuit decodes address data in accordance with a control signal from the control circuit when reading or writing data, and selects one of the m word lines WL1 to WLm according to the decoding result. And activate.

When reading or writing data, the data input / output circuit decodes the address data in accordance with the control signal from the control circuit 1, and n bit line pairs (BL 1, XBL 1) ˜ ( A group of bit line pairs corresponding to data of a predetermined data length (for example, 1 byte) is selected from BLn, XBLn).
When data is read, the voltage difference or current difference generated in the selected bit line pair is amplified by a built-in sense amplifier and output as read data Dout.
When data is written, the built-in write circuit drives the two bit lines of the selected bit line pair in a complementary manner based on the input write data Din. That is, one of the bit line pairs is driven to a high level and the other is driven to a low level according to the value of the write data Din.

The bit line control circuit controls the voltage and current supplied to the bit line pairs (BL1, XBL1) to (BLn, XBLn) in accordance with a control signal from the control circuit.
For example, when reading or writing data, before activating the word line WLi, the bit line pairs (BL1, XBL1) to (BLn, XBLn) are pulled up to a voltage 'VDD / 2' which is half the power supply voltage VDD. To do. Thereafter, by pulling up and activating the word line WLi, voltage differences corresponding to the stored data of the memory cells MCi1 to MCin are generated in the bit line pairs (BL1, XBL1) to (BLn, XBLn), respectively. The sense amplifier of the data input / output circuit 3 amplifies the voltage difference generated in the bit line pair.

  Next, a more detailed configuration of the main part of the memory cell array MA (14, 16, 18, 20, 24, 26, 28, 30) and the data input / output circuit, particularly the write buffer circuit, will be described with reference to FIG. .

  FIG. 2 is a diagram showing an example of the configuration of memory cell array MA and data input / output circuit in the semiconductor memory device shown in FIG. In FIG. 2, only the circuits related to the three memory cells (MC11 to MC13) are extracted and shown for easy understanding.

In the embodiment shown in FIG. 2, the memory cell MC11 has a capacitor C11 for storing information and a transistor Q11 for access. The capacitor C11 is connected to the bit line BL1 via the transistor Q11, and the gate of the transistor Q11 is connected to the word line WL1.
Similarly, the memory cell MCij has an information storage capacitor Cij and an access transistor Qij. The capacitor Cij is connected to the bit line BLj via the transistor Qij, and the gate of the transistor Qij is connected to the word line WLi.

  In the embodiment shown in FIG. 2, the data input / output circuit includes sense amplifiers SA1, SA2, SA3,..., SAn and write circuits WC1,.

When the memory cell MC1j to Mmj in the j-th column is accessed via the bit line pair (BLj, XBLj), the sense amplifier SAj has a bit line pair (BLj, XBLj corresponding to a signal held in the memory cell). ) Signal.
That is, when any of the memory cells MC1j to Mmj becomes accessible via the bit line pair (BLj, XBLj) by the activation of the word line, the power supply is received from the sense amplifier drive circuit SDj described later. The voltage difference between the bit line pair (BLj, XBLj) is amplified.

  The write circuit WCj inputs a write signal to the bit line pair (BLj, XBLj) in accordance with the control signal WAj supplied from the control circuit 1 when writing to any of the memory cells MC1j to MCmj in the j-th column.

In the example of FIG. 2, the write circuit WCj includes NMOS transistors Qn5-j and Qn6-j and a write buffer WBj.
In the write buffer WBj, write data is set by a write data setting circuit (not shown) at the time of data writing, and one of the write data line pairs (WDj, XWDj) is set to the power supply voltage VDD side and the other is grounded according to the set value. Drive to the level GND side.
The NMOS transistor Qn5-j is connected between the write data line WDj and the bit line BLj, and the control signal WAj is input to the gate.
The NMOS transistor Qn6-j is connected between the write data line XWDj and the bit line XBLj, and the control signal WAj is input to the gate.
When the control signal WAj is set to a high level by the control circuit, the NMOS transistors Qn5-j and Qn6-j are both turned on, and the bit line pair (BLj, XBLj) and the write data line pair (WDj, XWDj) are turned on. Connected.

next. FIG. 3 shows an embodiment of the write buffer circuits WB1 to WB3,... (WBj).
In the TS1 output terminal path,
The write enable pulse (WEp) and data (DATA) are input to the AND circuit 71, and the output is connected to one input terminal of the OR circuit 74. A standby (STBp) control signal is input to the other input terminal of the OR circuit 74. The output of the AND circuit 71 is further connected to the gate of the NMOS transistor 77. The output of the OR circuit 74 is connected to the gate of the PMOS transistor 76, the source of the PMOS transistor 76 is connected to the power supply VDD, the drain is connected to the drain of the NMOS transistor 77, and the drain is connected to the write data line via the output terminal TS1. (WD1, XWD1), (WD2, XWD2), (WD3, XWD3),..., (WDj, XWDj), for example, are connected to positive phase terminals (WDj), respectively. The source of the NMOS transistor 77 is connected to the ground.
In the TS2 output terminal path,
DATA is connected to one input terminal of an AND circuit 73 via an inverter 72. A write enable pulse (WEp) is input to the other input terminal of the AND circuit 73. The output of the AND circuit 73 is connected to one input terminal of the OR circuit 75, and a standby (STBp) control signal is input to the other input terminal. The output of the AND circuit 73 is further connected to the gate of the NMOS transistor 79. The output of the OR circuit 75 is connected to the gate of the PMOS transistor 78, the source of the PMOS transistor 78 is connected to the power supply VDD, the drain is connected to the drain of the NMOS transistor 79, and the drain is connected to the write data line via the output terminal TS2. (WD1, XWD1), (WD2, XWD2), (WD3, XWD3),..., (WDj, XWDj), for example, are connected to inverting terminals (XWDj), respectively. The source of the NMOS transistor 77 is connected to the ground.

Next, the operation of the write buffer circuit (WBj) 70 will be described with reference to the timing chart of FIG.
An STBp (standby) control signal (not shown) is supplied from the outside, transitions from the “H” level to the “L” level at time t0, and maintains that level until time t5. When this level is input to one input terminal of the OR circuit, the output result of the OR circuit 74 is determined by the other input level until time t5.
Further, before writing, it is necessary that the low leakage power state is released, that is, the STBp control signal is “L”. When the STBp control signal becomes “L”, a recovery period occurs until the write bus that has been in the high impedance state reaches the precharge level. Writing is performed after the write bus level returns.

After Write Bus returns and stabilizes to the “H” or “L” level state, WEp changes from the “L” level to the “H” level at time t1.
The TS1 output terminal path will be described.
The “H” level of WEp and DATA are input to the AND circuit 71. When DATA is at “H” level, the output from the AND circuit 71 is at “H” level, and the “H” level is input to the OR circuit 74. As described above, since the OR circuit 74 is determined by the state of the other input, that is, the output state of the AND circuit 71, the output of the OR circuit is at the “H” level.
As a result, the "H" level is input to the gate of the PMOS transistor 76, and the "H" level of the output of the AND circuit 71 is input to the gate of the NMOS transistor 77. The PMOS transistor 76 is OFF and the NMOS transistor 77 is ON. It becomes an operation state. Accordingly, the output terminal TS1 is at the “L” level.
When the data is at the “L” level, the output of the AND circuit 71 is at the “L” level. Since STBp is at “L” level, the output of the OR circuit 74 is at “L” level. As a result, the “L” level is input to the gate of the PMOS transistor 76, and the “L” level is input to the gate of the NMOS transistor 77. As a result, TS1 becomes “H” level.
The output terminal path of TS2 will be described.
Since DATA is at “H” level, the logic is inverted by the inverter 72, so that it becomes “L” level and the “L” level is input to the AND circuit 73. The output from the AND circuit 73 becomes “L” level, and the “L” level is input to the OR circuit 75. As described above, since the OR circuit 75 is determined by the state of the other input, that is, the output state of the AND circuit 71, the output of the OR circuit 75 is at the “L” level.
As a result, the “L” level voltage is input to the gate of the PMOS transistor 78, and the “L” level voltage of the output of the AND circuit 71 is input to the gate of the NMOS transistor 79. 77 becomes an OFF operation state.
Therefore, when DATA is at “H” level, the output of TS2 is at “H” level.
Next, when DATA is at "L" level, the data is opposite to the result at the above-described "H" level, and the output terminal TS1 is at "H" level and the TS2 terminal is at "L" level. The waveform at this time is shown at time t1 to t2 in FIG.

At time t2, WEp changes from “H” level to “L” level.
The TS1 output terminal path will be described.
Input to the AND circuit 71 is the “L” level of WEp and the “H” or “L” level of DATA. As a result, the output of the AND circuit 71 becomes “L” level. Since the STBp control signal is at the “L” level during the period from time t2 to time t3, the inputs of the OR circuit 74 are all at the “L” level, and the output is at the “L” level.
The “L” level of the OR circuit 74 is input to the gate of the PMOS transistor 76, and as a result, is turned on. On the other hand, since the output level “L” of the AND circuit 71 is input to the gate of the NMOS transistor 77, the NMOS transistor 77 is turned off. Therefore, the output terminal TS1 is at the “H” level.
Next, the output terminal path of TS2 will be described.
Input to the AND circuit 73 is data obtained by inverting the “L” level of WEp and the “H” or “L” level of DATA by the inverter 72, and as a result, the output of the AND circuit 73 becomes the “L” level. . Since the STBp control signal is at the “L” level during the period from time t2 to time t3, the inputs to the OR circuit 75 are all at the “L” level, and the output is at the “L” level.
The “L” level of the OR circuit 75 is input to the gate of the PMOS transistor 78, and as a result, the ON operation state is set. On the other hand, since the voltage of the output level “L” of the AND circuit 73 is inputted to the gate of the NMOS transistor 79, the NMOS transistor 79 is turned off. Therefore, the output terminal TS2 is set to the “H” level (time t2 to t3 in FIG. 4C).
However, since TS1 and TS2 are at "H" level and WEp is at "L" level, the PMOS transistors 76 and 78 do not operate and no write operation is performed. However, the PMOS transistors 76 and 78 in the final stage have a leakage current.
Similarly, when the WEp is at the “L” level and the output terminals TS1 and TS2 are at the “H” level, there is a possibility that the PMOS transistors 76 and 78 have a leakage current.
Times t3 to t4 perform the same operations as times t1 to t2, and times t4 to t5 perform the same operations as times t2 to t3.

At time t5, the STBp control signal changes from the “L” level to the “H” level.
Under this condition, the output levels of the OR circuits 74 and 75 are always “H” level regardless of other input conditions, so that the PMOS transistors 76 and 78 are in the OFF operation state, and no leak current as a buffer circuit flows.
The TS1 output terminal path will be described.
Since WEp is at “L” level at time t 5, the output of the AND circuit 71 becomes “L” level regardless of the DATA level, and is input to the gates of the OR circuit 74 and the NMOS transistor 77.
Since the STBp control signal is at the “H” level, the PMOS transistor 76 is in the OFF operation state as described above, and the “L” level is input to the gate of the NMOS transistor, so that it is in the OFF state.
As a result, when the STBp control signal is at the “L” level and WEp is at the “L” level, both the PMOS transistor 76 and the NMOS transistor 77 are turned off simultaneously, and the leakage current is greatly reduced.
In the conventional write buffer circuit 250 shown in FIG. 11, only one of the transistors at the final stage is in the OFF state and the leakage current cannot be sufficiently reduced. However, in the write buffer circuit 70 shown in FIG. Since the final stage transistor can be completely turned off, the leakage current can be further reduced.
Next, the output terminal path of TS2 will be described.
Since the STBp control signal is at the “H” level, the PMOS transistor 78 is turned off as described above.
Since WEp is now at the “L” level, the output of the AND circuit 73 is at the “L” level regardless of the other input state of the AND circuit 73, that is, the DATA level is at the “H” or “L” level.
Therefore, as described above, the PMOS transistor 78 is in the OFF operation state, and the “L” level is input to the gate of the NMOS transistor 79, so that the PMOS transistor 78 is in the OFF state.
As a result, when the STBp control signal is at “L” level and WEp is at “L” level, both the PMOS transistor 78 and the NMOS transistor 79 are simultaneously turned off, and the leakage current is the same as in the circuit operation of the TS1 path. Significantly reduced.

As a result, when the STBp control signal is input to the write buffer circuit 70, the final stage transistors constituting the write buffer circuit 70 are completely turned off, and the leakage current is greatly reduced.
Thus, the present invention is to provide a logic circuit in the write buffer circuit and supply a control signal thereto to turn off the transistors at the final stage of the write buffer circuit on both the high side and the low side.
As shown in FIG. 3, OR circuits 74 and 75 are inserted in front of PMOS transistors 76 and 78 which are high side transistors of the write buffer circuit. When the STBp control signal is at “L” level and a write enable (WEp) signal is input, the pair of write buffers (output terminal paths of TS1 and TS2) are written according to the logic of the data input from the outside. • Output data to the bus.
As described above, STBp is set to “H” level to bring the IC chip into a low leakage power state. In this state, if the write enable signal is “L” level, the high-side PMOS transistor is turned off by the OR circuits 74 and 75. The low-side NMOS transistor is turned off by the AND circuits 71 and 73.

If this embodiment is used, the layout size is only the amount of OR circuit insertion. Since the OR circuit is located before the final stage, the increase in layout size can be significantly suppressed. Further, since the final stage may be exactly the same as the conventional example, the speed degradation is very small as much as one stage of the OR circuit. Further, in the low leakage power state, both the high-side and low-side transistors are turned off, so that the leakage power is significantly reduced.
Since the uppermost transistor of the output circuit of the write buffer circuit connected to the non-operating bank that is not operating as a memory is completely set to the OFF state, the leakage current is greatly reduced.

  As described above, the output data from the write buffer circuit 70 in which the leakage voltage is greatly reduced is passed through the NMOS transistors Qn5-1, Qn6-1, Qn5-2, Qn6-2, Qn5-3, Qn6-3,. Are written in the memory cells MC11, MC12, MC13,.

In a state before the write operation is executed, the control circuit (not shown) performs a bit so as to precharge the bit line pairs (BL1, XBL1) to (BLn, XBLn) to a voltage “VDD / 2” which is half the power supply voltage VDD. Control the line control circuit.
The control circuit sets all the control signals WA1 to WAn to the low level, and sets the bit line pairs (BL1, XBL1) to (BLn, XBLn) and the write data line pairs (WD1, XWD1) to (WDn, XWDn), respectively. Separate.

  In this state, the control circuit controls the row decoding circuit to activate one word line corresponding to the row address data (ADD1).

When the word line WL1 is activated, the access transistor Q1j of the memory cell MC1j becomes conductive, and the voltage of the bit line BLj slightly increases or decreases from the voltage 'VDD / 2' according to the charge stored in the capacitor C1j.
In the example of FIG. 2, for example, the capacitor C12 of the memory cell MC12 has a high level voltage, and the voltage of the bit line BL2 is slightly higher than 'VDD / 2'.
At that time, the capacitors C11 and C13 of the other memory cells MC11 and MC13 have low level voltages, respectively, and the voltages of the bit lines BL1 and BL3 are slightly lower than 'VDD / 2'.

On the other hand, in parallel with the decoding of the row address data by the row decoding circuit, the control circuit causes the column decoding circuit (not shown) included in the data input / output circuit to decode the column address data. Then, data write preparation is started in the write circuit connected to the group of bit line pairs selected according to the column decoding result. That is, write data is set in the write buffer WBj of the selected column, and one of the write data line pair (WDj, XWDj) is driven to the power supply voltage VDD side and the other is driven to the ground level GND side.
For example, the second column is selected as a write target according to the decoding result of the address data, and thereafter, the write circuit WC2 starts preparation for writing data. That is, the write data line XWD2 is driven to the power supply voltage VDD side by the write buffer WB2, and the write data line WD2 is driven to the ground level GND side.

When data write preparation is started in the write circuit, the control circuit next inputs a write signal from the write circuit to the bit line pair in the write target column. At the time of writing, all bit lines are sensed, and after a predetermined time has elapsed from the write preparation time, they are activated using the control signal WA2 in the second column, and the bit line pair (BL2, XBL2) and the write data line pair ( WD2, XWD2) are connected. The write data is amplified by the sense amplifier SA2, the bit line XBL2 is driven to the power supply voltage VDD side, and the bit line BL2 is driven to the ground level GND side.
At this time, the control signals WA1 and WA3 remain inactive, and the bit line pairs (BL1, XBL1) and (BL3, XBL3) maintain a minute voltage difference as they are, and the voltage level of the bit line pair is Do not cross.

  After the bit line XBL2 is driven to the power supply voltage VDD side and the bit line BL2 is driven to the ground level GND side, the data driven to the ground level GND side of the bit line BL2 is already selected as the write transistor. It is stored in the capacitor C12 constituting the memory through the MOS transistor Q12.

Next, a write buffer circuit 90 according to another embodiment will be described with reference to FIG.
In FIG. 5, the present embodiment is characterized in that the target is a DRAM and the low-leakage power state is controlled by a row address strobe signal RASn of the DRAM.
The write buffer circuit 90 having a specific circuit configuration is the same as the circuit configuration of the write buffer circuit 70 shown in FIG. However, it differs from the STBp (standby) control signal of FIG. 3 that the signal supplied to one input terminal of the OR circuits 94 and 95 is a RASn (row address strobe) signal.
Since the circuit configuration and its operation are merely replaced by the RASp signal in the STBp control signal of the write buffer circuit 70 shown in FIG. When the RASn signal is at “H” level, the outputs of the OR circuits 94 and 95 are at “H” level regardless of the state of “H” level or “L” level of other input terminals. As a result, the PMOS transistors 96 and 98 are both turned off.

When RSAn is at “H” level and the WEp control signal is at “L” level, the outputs of the AND circuits 91 and 93 are both at “L” level, and the gates of the NMOS transistors 97 and 99 have “L” level voltage. Since these are input, both transistors are in the OFF operation state.
Therefore, when the RASn signal is at “H” level and the WEp control signal is at “L” level, the PMOS transistors 96 and 98 and the NMOS transistors 97 and 99 at the final stage of the write buffer circuit 90 are simultaneously turned off, so that leakage current is generated. It will be greatly reduced.
That is, when the write buffer circuit 90 of this embodiment is used, it is more advantageous in the following points than the write buffer circuit 70 of FIG.
When the logic of the RASn signal and the WEp control signal described above is a condition other than the above-described logic, STBp may be replaced with RASn, which is the same as described with reference to FIGS.

When the DRAM operates, a certain delay time is essential between the input of the row address strobe signal and the data write time. Therefore, the restoration of the write bus only needs to be completed between the input of the row address strobe signal and the input of the write enable signal.
Further, it is essential that the row address strobe signal has been input before writing to the DRAM. That is, if the present embodiment is applied, no special signal is required for transition to the low leakage current state and for recovery from the low leakage current state. It is also possible to conceal the revival of the light bus from the outside.

Next, another embodiment will be described with reference to FIGS.
FIG. 6 shows an example of the circuit configuration of the entire DRAM having a multi-bank configuration. In this embodiment, assuming that the DRAM operates in multiple banks, this DRAM has a four-bank configuration of bank0 to bank3 for the sake of simplicity. Here, a row address strobe signal can be input to each bank independently. Control signals RAS1 to RAS3 (RASn) are supplied to each bank, and are switched by this RASn to select a specific bank and enter an operating state. The write buffer circuits 112 and 132 are commonly used for all the banks 0 to 3 (bankn). In this case, it is necessary to return the write buffer to the normal state even when one bank is selected.

The multi-bank DRAM device shown in FIG. 6 has four banks for each of the write buffers 112 and 132. The entire DRAM circuit includes a memory cell array MA (114, 117, 120, 123, 134, 137, 143, 140) and a sense amplifier (Sense Amp) (113, 115, 116, 118, 119, 121, 122, 124). 133, 135, 136, 138, 139, 141, 142, 144), a write buffer (Write Buffer) circuit 112, 132, a row decoding circuit, a bit line control circuit, a data input / output circuit, R / W, not shown. And ENp (enable signal) are supplied to control the decoder circuit. In addition, each bank 0 to 3 has a sense amp (113, 115, 116, 118, 119, 121, 122, 124) on each side (as a pair) of the memory cell arrays MA114, 117, 120, 123, 134, 137, 140, 143. 133, 135, 136, 138, 139, 141, 142, 144).
The memory cell array MA, the bit line pair, and the like are the same as the circuit configuration shown in FIG.

The memory cell array MA (114, 117, 120, 123, 134, 137, 140, 143) described above includes memory cells MC11,..., MCmn arranged in a matrix of m rows and n columns.
The memory cells MCi1 to MCin in the i-th row (i represents an integer of 1 ≦ i ≦ m; the same applies hereinafter) are connected to a common word line WLi.
The memory cells MC1j to MCmj in the j-th column (j represents an integer of 1 ≦ j ≦ n; the same applies hereinafter) are connected to a common bit line pair (BLj, XBLj).

  The control circuit generates various control signals necessary for executing a read operation and a write operation on the memory cell array MA (114, 117, 120, 123, 134, 137, 140, 143), and generates a row decode circuit. , Supplied to the data input / output circuit and bit line control circuit. For example, in response to the selection signal R / W, whether to perform a read or write operation is selected, and when the enable signal EN is set to an active state, various control signals for executing the selected operation Is generated.

  The row decoding circuit decodes address data in accordance with a control signal from the control circuit when reading or writing data, and selects one of the m word lines WL1 to WLm according to the decoding result. And activate.

When reading or writing data, the data input / output circuit decodes address data in accordance with a control signal from the control circuit, and n bit line pairs (BL1, XBL1) to (BLn) according to the decoding result. , XBLn), a group of bit line pairs corresponding to data of a predetermined data length (for example, 1 byte) is selected.
When data is read, the voltage difference or current difference generated in the selected bit line pair is amplified by a built-in sense amplifier and output as read data Dout.
When data is written, the built-in write circuit drives the two bit lines of the selected bit line pair in a complementary manner based on the input write data Din. That is, one of the bit line pairs is driven to a high level and the other is driven to a low level according to the value of the write data Din.

The bit line control circuit controls the voltage and current supplied to the bit line pairs (BL1, XBL1) to (BLn, XBLn) in accordance with a control signal from the control circuit.
For example, when reading or writing data, before activating the word line WLi, the bit line pairs (BL1, XBL1) to (BLn, XBLn) are pulled up to a voltage 'VDD / 2' which is half the power supply voltage VDD. To do. Thereafter, by pulling up and activating the word line WLi, voltage differences corresponding to the stored data of the memory cells MCi1 to MCin are generated in the bit line pairs (BL1, XBL1) to (BLn, XBLn), respectively. The sense amplifier of the data input / output circuit amplifies the voltage difference generated in the bit line pair.

The write circuit WC1 inputs a write signal to the bit line pair (BL1, XBL1) in accordance with the control signal WA1 at the time of write access. That is, one of the write data line pairs (WD1-1, XWD1-1) is driven to the power supply voltage VDD and the other to the ground level GND by the write buffer, and this is driven to the bit line pair (BL1, XBL1) according to the control signal WA1-1. Connect to.
As in FIG. 1, the write circuit having the write buffer circuits 112 and 132 inputs a write signal to the bit line pair in accordance with the control signal. The write circuit inputs a write signal to the bit line pair according to the control signal.

A specific circuit example of the write buffer circuit 170 constituting the write circuits 112 and 132 is shown in FIG. An AND circuit that performs an AND operation on the row address strobe signals RASn of all the bank signals is provided in the preceding stage of the OR circuit of the write buffer circuit 90 shown in FIG. 5, and one of the banks is selected to be in an operating state. If this is the case, the low leakage current state is canceled.
About TS11 output terminal path
The output of the AND circuit 171 to which the write enable pulse (WEp) and data (DATA) are input is connected to one input terminal of the OR circuit 174 and also connected to the gate of the NMOS transistor 177. The RASn signals of the respective banks 0 to n are input to the AND circuit 181 and the logical operation result is supplied to the other input terminal of the OR circuit 174. The output of the OR circuit 174 is connected to the gate of the PMOS transistor 176, the source of the PMOS transistor 176 is connected to the power supply VDD, the drain is connected to the drain of the NMOS transistor 177, and the drain is connected to the write data line via the output terminal TS11. For example, to the positive phase terminal (WDj). The source of the NMOS transistor 177 is connected to the ground.
About TS21 output terminal path
DATA is connected to one input terminal of an AND circuit 173 via an inverter 172, and a write enable pulse (WEp) control signal is input to the other input terminal. The output of the AND circuit 173 is connected to one input terminal of the OR circuit 175 and to the gate of the NMOS transistor 179. The RASn (bank 0 to n) signal is input to the AND circuit 182 and an AND logic operation is performed. The output of the AND circuit 182 is connected to the other input of the OR circuit 175.
The output of the OR circuit 175 is connected to the gate of the PMOS transistor 178, the source of the PMOS transistor 178 is connected to the power supply VDD, the drain is connected to the drain of the NMOS transistor 179, and the drain is connected to the write data line via the output terminal TS21. For example, it is connected to the inverting terminal (XWDj). The source of the NMOS transistor 179 is connected to the ground.

Next, the operation of the write buffer circuit (WBj) 170 will be described with reference to the timing chart of FIG.
From time t10 to t13, RASn (bank0) is at “L” level, and RASn (bank3) is at “H” level from time t10 to t14.
From time t10 to t11, WEp is at the “L” level.
The output path of TS11 will be described.
Since RASn bank0 is at "H" level and RASn bank3 is at "L" level, the output of AND circuit 181 is at "L" level, and since WEp is at "L" level, the output of AND circuit 171 is also at "L" level. "Become level. As a result, the output of the OR circuit 174 is at the “L” level. Since the output of the OR circuit 174 is at the “L” level, the “L” level is input to the gate of the PMOS transistor 176, and the ON operation state is entered. On the other hand, since the “L” level of the output of the AND circuit 171 is input to the gate of the NMOS transistor 177, the NMOS transistor 177 is turned off. Therefore, the output terminal TS11 becomes “H” level.
When WEp is at “L” level, writing is not possible, so the DATA level does not matter in terms of circuit operation.
The output path of TS21 will be described.
Since RASn bank0 is "H" level and RASn bank3 is "L", the output of the AND circuit 182 is "L" level, and since WEp is "L" level, the output of the AND circuit 173 is also "L". Become a level. As a result, the output of the OR circuit 175 is at the “L” level. Since the output of the OR circuit 175 is at the “L” level, the “L” level is input to the gate of the PMOS transistor 178 and the ON operation state is entered. On the other hand, since the “L” level of the output of the AND circuit 173 is input to the gate of the NMOS transistor 179, the NMOS transistor 179 is turned off. Therefore, the output terminal TS21 is at the “H” level.
When WEp is at “L” level, writing is not possible, so the DATA level does not matter in terms of circuit operation.

After Write Bus returns and stabilizes to the “H” or “L” level state, WEp transitions from the “L” level to the “H” level at time t11.
The output path of TS11 will be described.
At time t11, the “H” level of WEp is input to AND circuits 171 and 173, and DATA is inverted by AND circuit 171 and DATA by inverter 172 and input to AND circuit 173, respectively. When DATA is at “H” level, a voltage at “H” level is input to the AND circuit 171.
When DATA is at “H” level, the output from the AND circuit 171 becomes “H” level, and the “H” level is input to the OR circuit 174. Along with this, the output of the OR circuit 174 becomes “H” level.
The “H” level is input to the gate of the PMOS transistor 176, and the “H” level voltage output from the AND circuit 171 is input to the gate of the NMOS transistor 177. The PMOS transistor 176 is OFF and the NMOS transistor 177 is ON. It becomes a state. Accordingly, the output terminal TS11 is at the “L” level.
When DATA is at the “L” level, the output of the AND circuit 171 is at the “L” level, and the input to the OR circuit 174 is at the “L” level. When bank 3 of RASn is “L” level, “L” level is output from the output of AND circuit 181. As a result, the output of the OR circuit 174 becomes “L” level.
Therefore, since the “L” level is input to the gate of the PMOS transistor 176, the PMOS transistor 176 is turned on.
On the other hand, since the “L” level voltage of the AND circuit 171 is input to the gate of the NMOS transistor 177, the NMOS transistor 177 is turned off.
Next, the output terminal path of TS21 will be described.
When DATA is at “H” level, the logic is inverted by the inverter 172, so that it becomes “L” level and the “L” level is input to the AND circuit 173. The output from the AND circuit 173 becomes “L” level, and the “L” level is input to the OR circuit 175. Further, since the RASn bank3 is “L” level and the “L” level is output from the AND circuit 182, the OR circuit 175 is determined by the output state of the AND circuit 173, and the output of the OR circuit 175 becomes “L” level. .
As a result, the “L” level is input to the gate of the PMOS transistor 178, and the “L” level of the output of the AND circuit 173 is input to the gate of the NMOS transistor 179. The PMOS transistor 178 is ON and the NMOS transistor 179 is OFF. It becomes an operation state. At this time, the output terminal of TS21 is at "H" level.
On the other hand, when DATA is at “L” level, the output of INV circuit 172 is at “H” level and WEp is also at “H” level, so that the output of AND circuit 173 is at “H” level.
The output of the AND circuit 182 is at the “L” level, but since the output of the AND circuit 173 is at the “H” level, the output of the OR circuit 175 is at the “H” level. As a result, the “H” level is input to the gate of the PMOS transistor 178 and is turned OFF, while the “H” level is input to the gate of the NMOS transistor 179 and is turned ON. At this time, the output terminal becomes “L” level.
Write BUS changes to the “H” or “L” level in accordance with the “H” or “L” level of DATA during the period from time t11 to t12 (FIG. 8D).

At time t12, bank 0 of RASn remains “H” and bank 3 remains at “L” level, but WEp transitions from “H” level to “L” level.
The TS11 output path will be described.
The AND circuit 171 receives the “L” level of WEp and the “H” or “L” level of DATA. As a result, the output of the AND circuit 171 becomes “L” level. Since the output of the AND circuit 181 is at the “L” level during the period from time t12 to time t13, the inputs to the OR circuit 174 are all at the “L” level, and the output is at the “L” level.
The “L” level of the OR circuit 174 is input to the gate of the PMOS transistor 176 and, as a result, is turned on. On the other hand, since the output level “L” of the AND circuit 171 is input to the gate of the NMOS transistor 177, the NMOS transistor 177 enters the OFF operation state. Therefore, the output terminal TS11 becomes “H” level.
The output terminal path of TS21 will be described.
Data obtained by inverting the “L” level of WEp and the “H” or “L” level of DATA by the inverter 172 is input to the AND circuit 173. As a result, the output of the AND circuit 173 becomes “L” level. During the period from time t12 to t13, bank0 of RASn is at “H” level and bank3 of RASn is at “L” level, so that the output signal of AND circuit 182 is at “L” level, and the input to OR circuit 175 is Is also at the “L” level, and its output is at the “L” level.
The “L” level of the OR circuit 175 is input to the gate of the PMOS transistor 178 and, as a result, is turned on. On the other hand, since the output level “L” of the AND circuit 173 is input to the gate of the NMOS transistor 179, the NMOS transistor 179 is turned off. Therefore, the output terminal TS21 is at the “H” level (FIG. 8D).
During this period, the output terminals TS11 and TS21 are at the “H” level, but the write operation is not performed because WEp is at the “L” level. Further, although the PMOS transistors 176 and 178 do not actually operate, there is a possibility that a leak current flows.

At time t13, bank 0 of RASn transits from “H” level to “L” level, but bank 3 of RASn remains at “L” level.
The TS11 output path will be described.
The AND circuit 171 receives the WEp “L” level and the DATA “H” or “L” level. As a result, the output of the AND circuit 171 becomes “L” level. During the period from time t13 to t14, bank0 and bank3 of RASn are both at "L" level, so the output of AND circuit 181 is at "L" level. As a result, the inputs of the OR circuit 174 are all at the “L” level, and the outputs thereof are at the “L” level.
The “L” level of the OR circuit 174 is input to the gate of the PMOS transistor 176 and, as a result, is turned on. On the other hand, since the “L” level of the output of the AND circuit 171 is input to the gate of the NMOS transistor 177, the NMOS transistor 177 is turned off. Therefore, the output terminal TS11 becomes “H” level.
The output terminal path of TS21 will be described.
Data obtained by inverting the “L” level of WEp and the “H” or “L” level of DATA by the inverter 172 is input to the AND circuit 173. As a result, the output of the AND circuit 173 becomes “L” level. During the period from time t13 to t14, bank0 of RASn is at "L" level and bank3 of RASn is at "L" level, so that the output signal of AND circuit 182 is at "L" level, and the input to OR circuit 175 is Is also at the “L” level, and its output is at the “L” level.
The “L” level of the OR circuit 175 is input to the gate of the PMOS transistor 178 and, as a result, is turned on. On the other hand, since the output level “L” of the AND circuit 173 is input to the gate of the NMOS transistor 179, the NMOS transistor 179 is turned off. Therefore, the output terminal TS21 is at the “H” level (FIG. 8D).
During this period, the output terminals TS11 and TS21 are at the “H” level, but the write operation is not performed because WEp is at the “L” level. Further, although the PMOS transistors 176 and 178 do not actually operate, there is a possibility that a leak current flows.

At time t14, bank 3 of RASn changes from “L” level to “H” level, but bank 0 of RASn remains at “L” level. The operation during this period is the same as the operation at time t13.
The TS11 output path will be described.
The AND circuit 171 receives the WEp “L” level and the DATA “H” or “L” level. As a result, the output of the AND circuit 171 becomes “L” level. At time t14, bank 0 of RASn is at “L” level and bank 3 of RASn is at “H” level, so that the output of AND circuit 181 is at “L” level. As a result, the inputs of the OR circuit 174 are all at the “L” level, and the outputs thereof are at the “L” level.
The “L” level of the OR circuit 174 is input to the gate of the PMOS transistor 176 and, as a result, is turned on. On the other hand, since the output level “L” of the AND circuit 171 is input to the gate of the NMOS transistor 177, the NMOS transistor 177 enters the OFF operation state. Therefore, the output terminal TS11 becomes “H” level.
The output terminal path of TS21 will be described.
Data obtained by inverting the “L” level of WEp and the “H” or “L” level of DATA by the inverter 172 is input to the AND circuit 173. As a result, the output of the AND circuit 173 becomes “L” level. At time t14, bank 0 of RASn is at “L” level and bank 3 of RASn is at “H” level. Therefore, the output signal of AND circuit 182 is at “L” level, and the inputs of OR circuit 175 are both “L”. The output is “L” level.
The “L” level of the OR circuit 175 is input to the gate of the PMOS transistor 178 and, as a result, is turned on. On the other hand, since the output level “L” of the AND circuit 173 is input to the gate of the NMOS transistor 179, the NMOS transistor 179 is turned off. Therefore, the output terminal TS21 is at the “H” level (FIG. 8D).
During this period, the output terminals TS11 and TS21 are at the “H” level, but the write operation is not performed because WEp is at the “L” level. Further, although the PMOS transistors 176 and 178 do not actually operate, there is a possibility that a leak current flows.

At time t16, bank 0 of RASn remains at “L” level and bank 3 remains at “H” level, but WEp transitions from “L” level to “H” level. During the period from time t16 to t17, the same operation as that from time t11 to t12 is performed.
The output path of TS11 will be described.
At time t16, the “H” level of WEp is input to AND circuits 171 and 173, and DATA is inverted by AND circuit 171 and DATA by inverter 172 and input to AND circuit 173, respectively.
When DATA is at “H” level, the output from the AND circuit 171 becomes “H” level, and the “H” level is input to the OR circuit 174. As a result, the output of the OR circuit 174 becomes “H” level.
The “H” level is input to the gate of the PMOS transistor 176, and the “H” level of the output of the AND circuit 171 is input to the gate of the NMOS transistor 177. The PMOS transistor 176 is OFF and the NMOS transistor 177 is ON. Become. Accordingly, the output terminal TS11 is at the “L” level.
When DATA is at the “L” level, the output of the AND circuit 171 is at the “L” level, and the input of the OR circuit 174 is at the “L” level. Since the “L” level from the output of the AND circuit 181 is input to the OR circuit 174, the output of the OR circuit 174 becomes the “L” level.
Therefore, since the “L” level is input to the gate of the PMOS transistor 176, the PMOS transistor 176 is turned on.
On the other hand, since the “L” level of the AND circuit 171 is input to the gate of the NMOS transistor 177, the NMOS transistor 177 is turned off. At this time, the output terminal TS11 becomes "H" level.
Next, the output terminal path of TS21 will be described.
When DATA is at “H” level, the logic is inverted by the inverter 172, so that it becomes “L” level and the “L” level is input to the AND circuit 173. The output from the AND circuit 173 becomes “L” level, and the “L” level is input to the OR circuit 175. The AND circuit 182 outputs the “L” level when the bank 0 of the RASn is “L” level. The OR circuit 175 is determined by the output state of the AND circuit 173 and becomes “L” level.
As a result, the “L” level is input to the gate of the PMOS transistor 178 to be in the ON operation state, and the “L” level of the output of the AND circuit 173 is input to the gate of the NMOS transistor 179 to be in the OFF state. At this time, the output terminal of TS21 is at "H" level.
On the other hand, when DATA is at “L” level, the output of INV circuit 172 is at “H” level and WEp is also at “H” level, so that the output of AND circuit 173 is at “H” level.
The output of the AND circuit 182 is at the “L” level, but since the output of the AND circuit 173 is at the “H” level, the output of the OR circuit 175 is at the “H” level. As a result, the “H” level is input to the gate of the PMOS transistor 178 and is turned OFF, while the “H” level is input to the gate of the NMOS transistor 179 and is turned ON. At this time, the output terminal becomes the “L” level (FIG. 8D).

At time t17, WEp changes from “H” level to “L” level. However, the logic levels of bank0 and bank3 in the period RASn from time t17 to t18 do not change.
The operation is the same as that during the period from time t14 to t15.
The TS11 output path will be described.
The AND circuit 171 receives the WEp “L” level and the DATA “H” or “L” level. As a result, the output of the AND circuit 171 becomes “L” level. At time t17, RASn bank0 is at "L" level and bank3 is at "H" level, so the output of the AND circuit 181 is at "L" level. As a result, the inputs of the OR circuit 174 are all at the “L” level, and the outputs thereof are at the “L” level.
The “L” level of the OR circuit 174 is input to the gate of the PMOS transistor 176 and, as a result, is turned on. On the other hand, since the output level “L” of the AND circuit 171 is input to the gate of the NMOS transistor 177, the NMOS transistor 177 enters the OFF operation state. Therefore, the output terminal TS11 becomes “H” level.
The output terminal path of TS21 will be described.
Input to the AND circuit 173 is data obtained by inverting the “L” level of WEp and the “H” or “L” level of DATA by the inverter 172. As a result, the output of the AND circuit 173 becomes “L” level. At time t17, bank 0 of RASn is at “L” level and bank 3 of RASn is at “H” level, so that the output signal of AND circuit 182 is at “L” level, and the inputs of OR circuit 175 are both “L”. The output is “L” level.
The “L” level of the OR circuit 175 is input to the gate of the PMOS transistor 178 and, as a result, is turned on. On the other hand, since the output “L” level of the AND circuit 173 is input to the gate of the NMOS transistor 179, the NMOS transistor 179 is turned off. Therefore, the output terminal TS21 is at the “H” level (FIG. 8D).
During this period, the output terminals TS11 and TS21 are at the “H” level, but the write operation is not performed because WEp is at the “L” level. Further, although the PMOS transistors 176 and 178 do not actually operate, there is a possibility that a leak current flows.

At time t18, RASn bank0 to bank3 are both at the “H” level. This state corresponds to, for example, that the memory region driven by Write Buffer-B1 in FIG. 1 is deactivated and Write Buffer-B2 is activated.
The output path of TS11 will be described.
Since bank 0 to bank 3 are at “H” level, the output of the AND circuit 181 becomes “H” level, and the output of the OR circuit 174 also becomes “H” level regardless of the result of the AND circuit 171. Since the WEp control signal is at “L” level, the output of the AND circuit 171 becomes “L” level. As a result, the PMOS transistor 176 is turned off, the NMOS transistor 177 is turned off, and the output terminal TS11 maintains a high impedance state. Further, since all the output transistors are in the OFF state during this period, no leak current flows.
The TS21 output path will be described.
Since all the inputs of the AND circuit 182 are at the “H” level, the output is at the “H” level. Since the WEp control signal is at “L” level, the output of the AND circuit 173 is at “L” level. As a result, the “H” level is input to the gate of the PMOS transistor 178 to enter the OFF operation state, and the “L” level is input to the gate of the NMOS transistor 179 to enter the OFF operation state. Therefore, the output terminal TS21 is in a high impedance state. Further, since all the output transistors are in the OFF state during this period, no leak current flows.
That is, after this time t18, all the transistors in the final stage are turned off, and unlike the case where only one of the transistors in the final stage is turned off, the leakage current is greatly reduced.

  In the circuit described above, an OR circuit and an AND circuit are added to significantly reduce the leakage current. The layout size of this write buffer circuit is only for the OR circuit and AND circuit insertion. Since the OR circuit and the AND circuit are before the final stage, the increase in the layout size can be remarkably suppressed. Further, since the final stage may be exactly the same as that of the conventional example, the speed deterioration is very small as much as one stage of the OR circuit and the AND circuit. Further, in the low leakage power state, both the high-side and low-side transistors are turned off, so that the leakage power is significantly reduced.

  Therefore, the write buffer circuit described above can reduce the leakage current of the memory write buffer. In particular, when applied to a DRAM, it is possible to expect a large leakage current reduction effect while suppressing an increase in layout size and minimizing the influence on the operation speed of the circuit.

It is a figure which shows an example of a structure of the semiconductor memory device which concerns on embodiment of this invention. FIG. 2 is a diagram showing an example of a configuration of a memory cell array and a data input / output circuit in the semiconductor memory device shown in FIG. 1. FIG. 2 is a diagram illustrating an example of a configuration of a write buffer circuit illustrated in FIG. 1. FIG. 4 is a diagram showing an example of a timing signal of each part for explaining the write buffer circuit shown in FIG. 3. It is a figure which shows an example of a structure of the write buffer circuit of other embodiment. It is a figure which shows an example of a structure of the semiconductor memory device which concerns on the example of another embodiment. FIG. 7 is a diagram illustrating an example of a configuration of a write buffer circuit illustrated in FIG. 6. FIG. 8 is a diagram illustrating an example of a timing signal of each unit for describing the write buffer circuit illustrated in FIG. 7. It is a figure which shows an example of a structure of the semiconductor memory device of a prior art example. FIG. 11 is a diagram showing an example of a configuration of a memory cell array and a data input / output circuit in the semiconductor memory device shown in FIG. 10. It is a figure which shows the write buffer circuit of the prior art example shown in FIG. FIG. 11 is a diagram illustrating an example of timing signals of respective units for explaining the conventional write buffer circuit shown in FIG. 10. It is a figure which shows an example of a structure of the write buffer circuit of another prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,100,200 ... Semiconductor memory device 13,15,17,19,21 ... Sense amplifier (Sense Amp) 14,16,18,20 ... Memory cell array (MA) 12,22,70,90,170 , 250, 300 ... write buffer circuit, 72, 172, 252, 302 ... inverter circuit, 74, 75, 94, 95, 174, 175 ... OR circuit, 71, 73, 91, 93, 171, 173 , 181, 182, 151, 253, 301, 303 ... AND circuit, 76, 78, 96, 98, 176, 178, 256, 258, 306, 308, 310 ... PMOS transistors, 77, 79, 97, 99, 177 , 179, 257, 259, 307, 309, Qn5-1 to Qn5-n, Qn6-1 to Qn6-n,. NMOS transistors, MC11 to MCmn ... memory cells, SA1 to SAn ... sense amplifiers, WC1 to WCn ... write circuits, WB1 to WBn ... write buffers, WL1 to WLm ... word lines, BL1 to BLn, XBL1 to XBLn ... bit lines, WD1 to WDn, XWD1 to XWDn: write data lines

Claims (15)

A first arithmetic circuit which is supplied with a first control signal and data and performs a logical operation;
A second arithmetic circuit which is supplied with an output signal of the first arithmetic circuit and a second control signal and performs a logical operation;
A buffer that includes a plurality of transistors, and that is supplied with the output of the first arithmetic circuit and the output of the second arithmetic circuit, and simultaneously shuts off the output transistor in the final stage according to the second control signal. circuit. The buffer circuit according to claim 1, wherein the drive unit includes a complementary transistor. The buffer circuit according to claim 1, wherein the first arithmetic circuit includes an AND circuit, and the second arithmetic circuit includes an OR circuit. The first control signal and the data are logically operated when the second control signal is in a first state to operate the drive unit, and when the second control signal is in a second state, the drive unit is shut off. Buffer circuit. A first arithmetic circuit which is supplied with a first control signal and data and performs a logical operation;
A control signal generating circuit that receives a plurality of control signals different from the first control signal and generates a second control signal in response to the control signal;
A second arithmetic circuit which is supplied with an output signal of the first arithmetic circuit and a second control signal from the control signal generation circuit and performs a logical operation;
A buffer that includes a plurality of transistors, and that is supplied with the output of the first arithmetic circuit and the output of the second arithmetic circuit, and simultaneously shuts off the output transistor in the final stage according to the second control signal. circuit. The buffer circuit according to claim 5, wherein the drive unit includes a complementary transistor. The buffer circuit according to claim 5, wherein the first arithmetic circuit and the control signal generation circuit have an AND circuit, and the second arithmetic circuit has an OR circuit. 6. The second control signal operates the drive unit by performing a logical operation on the first control signal and the data when in the first state, and shuts off the drive unit when in the second state. Buffer circuit. Multiple bit lines,
A plurality of memory cells accessed via the plurality of bit lines;
A plurality of sense amplifiers that respectively amplify the signals of the bit lines according to signals held in the memory cells when the memory cells are accessed via the bit lines;
A write circuit having a write buffer circuit for inputting a write signal to the bit line of the memory cell to be written when writing to the memory cell;
The write buffer circuit includes:
A first arithmetic circuit that is supplied with a write enable signal and data and performs a logical operation;
A second arithmetic circuit which is supplied with an output signal of the first arithmetic circuit and a second control signal and performs a logical operation;
A drive unit that has a plurality of transistors, is supplied with the output of the first arithmetic circuit and the output of the second arithmetic circuit, and simultaneously shuts off the output transistor in the final stage according to the second control signal. Storage device. The semiconductor memory device according to claim 9, wherein the drive unit includes a complementary transistor. The semiconductor memory device according to claim 9, wherein the first arithmetic circuit includes an AND circuit, and the second arithmetic circuit includes an OR circuit. The second control signal is a standby signal or a row address strobe signal. In the first state, the write enable signal and the data are logically operated to operate the drive unit, and in the second state, the drive The semiconductor memory device according to claim 9, wherein the part is cut off. Multiple bit lines,
A plurality of memory cells accessed via the plurality of bit lines;
A plurality of banks each having a plurality of sense amplifiers for amplifying signals of the bit lines according to signals held in the memory cells when the memory cells are accessed via the bit lines;
A write circuit including a write buffer circuit for inputting a write signal to a bit line of a memory cell to be written when writing to the memory cell of each bank;
The write buffer circuit is
A first arithmetic circuit which is supplied with a first control signal and data and performs a logical operation;
A control signal generating circuit that receives a plurality of bank switching control signals and generates a second control signal in response to the bank switching control signals;
A second arithmetic circuit which is supplied with an output signal of the first arithmetic circuit and a second control signal from the control signal generation circuit and performs a logical operation;
A drive unit that has a plurality of transistors, is supplied with the output of the first arithmetic circuit and the output of the second arithmetic circuit, and simultaneously shuts off the output transistor in the final stage according to the second control signal. Storage device. The semiconductor memory device according to claim 13, wherein the drive unit includes a complementary transistor. The semiconductor memory device according to claim 13, wherein the first arithmetic circuit includes an AND circuit, and the second arithmetic circuit includes an OR circuit.

Images