JP2001160297A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which switching between high speed access operation and low power consumption operation can be performed. SOLUTION: A word line control circuit 12 is provided so that the word line is started with two different timing in accordance with a state of an external control signal, as a word line is started performing pre-charge at the time of high speed operation, sense operation is started directly after finish of pre- charge, and high speed access can be performed. At the low power consumption, as the word line is started after finish of pre-charge, power consumption can be suppressed. Thus, high speed and low power consumption can be performed by only switching external control signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a read circuit technology of a nonvolatile memory core such as a PROM.

[0002]

2. Description of the Related Art As one method of reading a semiconductor product, especially a nonvolatile memory device, memory cells arranged in a matrix in a matrix are selected from a word line and a bit line, and a sense amplifier is selected from the cell current of the selected memory cell. Generally, a method of amplifying stored information is used. In order to perform reading at a higher speed, the selected bit line is precharged in advance, and the current of the memory cell is detected by the sense amplifier after the precharge is completed.

FIG. 7 shows a conventional read circuit. 1 is 1
N-channel type memory cell for recording bit information, 2
Is a word line (WL0 to WLm) connected to the gate of the N-channel type memory cell 1, 3 is a bit line (BL0 to BLn) connected to the drain of the N-channel type memory cell 1, and 4 is an N-channel type memory cell 1 in a matrix. Are arranged in m rows and n columns.

5 is a word line 2 according to a row address Ay.
, And a row decoder 8 for arbitrarily selecting the bit line 3 according to the column address Ax, and a row decoder 8 for arbitrarily selecting the bit line 3 by the column address Ax. This is a sense amplifier that amplifies information stored in the channel type memory cell 1.

The column decoder 8 is composed of N-type transistors Qn0 to Qnn. Further, in the sense amplifier 10, the gate of the P-channel transistor Qp0 is connected to the precharge signal CLK, the source is connected to VDD, and the drain is connected to the sense node N00. N00 and sense amplifier output
INV0 is interposed between SOUT. FIG. 8 shows a timing chart of the above read circuit.

Here, the bit line BL1 and the word line WL0
Will be described when the memory cell Qm10 at which the data intersects is selected in the cycle (T1). When the address changes during the period in which CLK is at "L", one selected column decode signal CLM1 changes from "L" to "H", and precharging of the bit line BL1 is started via the column decoder Qn1. CLK is "H"
Then, one word line WL0 selected by the row address Ay is selected ("L" → "H"), and reading of the memory cell Qm10 is started. If current does not flow through the memory cell ("0" program), bit line BL1 maintains the precharge level, and if current flows through the memory cell ("1" program), bit line BL1 is discharged via memory cell Qm10. Is done.

The sense node N00 is maintained at Vcc during a precharge period. When the precharge is completed and the sensing operation is started, at the time of programming "0", N00 maintains Vcc, and "L" is output from SOUT by INV0. Also"
At the time of 1 "programming, when the precharge is completed and the sense operation is started, the sense node N00 is discharged to VSS via the column decoder Qn1 like the bit line, and INV0
"H" data is output from the sense amplifier when the switching level is exceeded.

[0008]

However, in such a conventional read circuit, since a word line is selected after precharge is completed, it takes time for the rise of the word line, and it is difficult to perform high-speed access. is there. On the other hand, required specifications such as high-speed access and low power consumption are different depending on the use of the microcontroller or the system LSI to be used. In addition, the same type uses different frequencies, and low power consumption is required at low speeds.

An object of the present invention is to provide a semiconductor memory device capable of switching between a high-speed access operation and a low power consumption operation.

[0010]

According to a semiconductor memory device of the present invention, a word line is selected simultaneously with precharge in a high speed mode in accordance with a high speed / low power consumption mode signal input from the outside, and immediately after precharge. The sense operation is started, and in the low power consumption mode, the word line is selected after the end of the precharge, so that one memory core can satisfy the two specifications of high speed and low power consumption.

A semiconductor memory device according to the present invention includes a memory cell array composed of memory cells arranged in a matrix, a word line for selecting a row of the memory cell array, and a bit line for selecting a column of the memory cell array. A sense amplifier for amplifying information read from the memory cell via the bit line, and control means for controlling the selection timing of the word line in response to an operation mode switching signal. .

Further, the semiconductor memory device of the present invention further comprises bit line precharge means for precharging the bit line, wherein the control means is configured to operate the bit line precharge operation by the bit line precharge operation. The present invention is characterized in that a first timing for starting a word line selection and a second timing for starting a word line selection after a bit line precharge is completed can be selected.

Further, the semiconductor memory device of the present invention further comprises a row decoder for selecting a word line according to a row address, wherein the control means controls the row decoder in response to the operation mode switching signal, The word line selection is started at the first timing in the high-speed mode, and the word line selection is started at the second timing in the low-power consumption mode.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. (Embodiment 1) FIGS. 1 and 2 show (Embodiment 1). The read circuit of FIG. 1 differs from the conventional example shown in FIG. 7 in that a word line control circuit 12 is provided in a stage preceding the row decoder 5.

1 is an N-channel type memory cell for recording 1-bit information, 2 is a word line (WL0 to WLm) connected to the gate of the N-channel type memory cell 1, and 3 is connected to a drain of the N-channel type memory cell 1. Bit line (BL0
To BLn), 4 is a memory cell array of m rows and n columns in which N-channel type memory cells 1 are arranged in a matrix.

The word line control circuit 12 includes a high speed / low power consumption switching terminal (HS) which is an external input signal and an address.
Ay is input and the row decoder 5 is controlled according to the HS terminal. The row decoder 5 arbitrarily selects the word line 2 and activates the selected word line 2. Reference numeral 8 denotes a column decoder for arbitrarily selecting the bit line 3 by the address Ax, and reference numeral 10 denotes a sense amplifier for amplifying information stored in the N-channel type memory cell 1 arbitrarily selected by the row decoder 5 and the column decoder 8.

The column decoder 8 comprises N-type transistors Qn0 to Qnn. Further, in the sense amplifier 10, the gate of the P-channel transistor Qp0 is connected to the precharge signal CLK, the source is connected to VDD, and the drain is connected to the sense node N00. The column decoders (Qn0 to Qnn) are connected to N000. INV0 is interposed between N00 and the sense amplifier output SOUT.

FIG. 2 shows a timing chart of the read circuit having such a configuration in the high-speed mode (HS = H). The memory cell Qm10 where the bit line BL1 and the word line WL0 cross is selected in the cycle (T1). The operation at the time will be described. When the address changes during the period in which CLK is at "L", one selected column decode signal CLM1 changes from "L" to "H", and precharging of the bit line BL1 is started via the column decoder Qn1. At the same time, when the address changes, the word line WL
1 is also selected.

Thereafter, when CLK becomes "H", the precharge is completed, and reading of the memory cell Qm10 is started. That is, if no current flows through the memory cell ("0" program), the bit line BL1 maintains the precharge level, and if a current flows through the memory cell ("1" program), the bit line BL1 passes through the memory cell Qm10. Discharged. The sense node NS0 is maintained at the precharge period Vcc. When the precharge is completed and the sensing operation is started, when "0" is programmed, N00 maintains Vcc, and "L" is output from SOUT by INV0. In addition, at the time of programming "1", when the precharge is completed and the sensing operation is started, the sense node N00 is discharged to VSS via the column decoder Qn1 similarly to the bit line, and becomes "H" when the switching level exceeds the switching level of INV0. Output data.

As described above, by selecting a word line while performing precharge, a sense operation can be started immediately after precharge is completed, so that data can be read at high speed. Also, when the selected memory cell is "1" program, a current flows through the memory cell when precharging is performed, so that the precharge level of the bit line is lower than when the word line is not activated, and the precharge is completed and the discharge is performed. Takes less time.

By setting the high-speed / low-power-consumption mode signal to "H", the word line can be selected at the same time as the precharge, and high-speed access can be performed. On the other hand, in the low power consumption mode (HS = “L”), the power consumption can be suppressed because the word line is activated after the end of the precharge as in the conventional example. As described above,
By controlling the timing of selecting a word line in accordance with the low power consumption mode signal, it is possible to satisfy two specifications, that is, high speed / low power consumption.

(Embodiment 2) FIGS. 3 and 4 show (Embodiment 2). The read circuit in FIG. 3 represents a block of a nonvolatile memory for outputting 1-bit data. Reference numeral 1 denotes an N-channel type memory cell for recording 1-bit information, 2 denotes a word line (WL0 to WLm) connected to the gate of the N-channel type memory cell 1, and 3 denotes a bit line connected to the drain of the N-channel type memory cell 1 ( BL0
To BLn), 4 is a memory cell array of m rows and n columns in which N-channel type memory cells 1 are arranged in a matrix.

Reference numeral 8 denotes a coder constituted by a single-stage column of N-channel transistors, 11 denotes a sense amplifier,
The sense amplifier and the bit line are connected via a column decoder. The gate of the precharge transistor Qp10 of the sense amplifier is connected to the output of a NAND circuit that receives the precharge signal CLK and the sense amplifier activation signals (SA0 to SA3), and the discharge transistor Qn100
Source is VSS and drain is bit line (BL0-BLn)
The gate is connected to the output of the inverter INV11 that receives the sense amplifier activation signal SA.

In order to perform high-speed reading, a column decoder is provided in one stage, and a sense amplifier selecting circuit 22 for decoding outputs of a plurality of sense amplifiers and outputting 1-bit data is provided. Further, eight column transistors (Qn0 to Qn7) are connected to one sense amplifier, and four sense amplifiers are arranged with eight columns as a basic unit, and are respectively connected to the power supplies of VDS0 to VDS3.
Further, the sense amplifier power supplies VDS0 to VDS3 are supplied with an externally input high-speed / low-consumption switching signal HS and an address (Ax).
, And is controlled by the sense amplifier power supply control circuit 21. Outputs of the sense amplifier power control circuit 21 (IN0 to I
N3) is connected to the gate of the sense amplifier power supply circuit 20 composed of high VT transistors, and its output is connected to the sense amplifier power supplies VDS0 to VDS3.

FIG. 4 is a timing chart of the low-consumption mode of the read circuit having such a configuration.
Cell transistor Qm01 crossing the word line WL0
The operation when is selected will be described. When the address changes during the CLK “L” period, IN0 changes from H to L and VDS0
DD is supplied. IN0 is controlled by a high-speed / low-consumption switching signal HS. At high speed (HS = H), since IN0 to IN3 are VSS, the power of the sense amplifier is always supplied. On the other hand, during low power consumption (HS = “L”), only the power of the selected sense amplifier is supplied, and the power of the non-selected sense amplifier is VSS. That is, IN1 to IN3 become "H", the high VT transistor Qn20 of the sense amplifier power supply circuit 20 conducts, and VDS1 to VDS
3 is grounded.

On the other hand, when the sense amplifier activation signal SA0 and the column decoder Qn1 are selected in response to the address change,
Precharge of the selected bit line BL1 is started. CLK is L
→ When the precharge is completed by changing to H, the word line WL0 is selected, and data is output from SAOUT0 according to the information programmed in the memory cell. At the same time, the sense amplifiers that are not selected have the sense amplifier selection signals SA1 to
Therefore, the output of INV11 becomes “H” and the sense node N100 becomes “L” by the Nch transistor Qn100.

Therefore, "H" is output from SAOUT1 to SAOUT3. Further, the sense amplifier outputs SAOUT0 to SAOUT3 are decoded into 1-bit data by the sense amplifier output decode circuit 21 and output. As design rules become finer, off-state leakage current during operation and standby increases, making it difficult to reduce power consumption. In this way, by reducing the number of column decoders connected to the sense amplifiers and decoding the outputs of the plurality of sense amplifiers, not only can high-speed access be made, but also the power supply of a plurality of unselected sense amplifiers is turned off in the low power consumption mode. Thus, off-leakage due to the memory cells can be reduced and power consumption can be reduced.

On the other hand, in the high-speed mode, the power supply of the sense amplifier is maintained at VDD, so that high-speed reading can be performed. (Embodiment 3) FIGS. 5 and 6 show (Embodiment 3). The read circuit in FIG. 5 illustrates a block of a nonvolatile memory for outputting 1-bit data.

1 is an N-channel type memory cell for recording 1-bit information, 2 is a word line (WL0-WLm) connected to the gate of the N-channel type memory cell 1, and 3 is connected to a drain of the N-channel type memory cell 1. Bit line (BL0
To BLn), 4 is a memory cell array of m rows and n columns in which N-channel type memory cells 1 are arranged in a matrix. Reference numeral 8 denotes a column formed of N-channel transistors in one stage, and a coder. Reference numeral 11 denotes a sense amplifier. The sense amplifier and the bit lines are connected via a column decoder. Also, the precharge transistor Qp10 of the sense amplifier
Is connected to the output of a NAND circuit that receives a precharge signal CLK and a sense amplifier activation signal (SA0 to SA3), the source of the discharge transistor Qn100 is VSS, and the drain is a bit line (BL0 to BLn). The gate is connected to the output of the inverter that receives the sense amplifier activation signal SA. In order to perform high-speed reading, a column decoder is provided in one stage, and a sense amplifier selecting circuit 22 for decoding outputs of a plurality of sense amplifiers and outputting 1-bit data is provided.

Eight column transistors (Qn0 to Qn7) are connected to one sense amplifier, and four sense amplifiers are arranged with eight columns as a basic unit and VDS0 to VDS
It is connected to the power supply of S3. Also, the precharge signal CLK
Is delayed by the delay circuit 23, so that the delay signal DLY
Are generated, and the sense amplifier power supply circuits VDS0 to VDS3 are controlled by the sense amplifier power supply control circuit 21 in accordance with a high-speed / low-consumption switching signal HS, an address (Ax) and a delay signal DLY input from outside. Outputs (IN0 to IN3) of the sense amplifier power supply control circuit 21 are connected to the gate of a sense amplifier power supply circuit 20 composed of high VT transistors, and the outputs thereof are sense amplifier power supplies VDS0 to VDS3.
It is connected to the.

FIG. 6 is a timing chart of the low consumption mode of the read circuit having such a configuration, and the operation when the memory cell transistor Qm01 where the bit line BL1 and the word line WL0 intersect is selected will be described. When the address changes during the CLK “L” period, IN0 changes from H to L and VDD is applied to VDS0.
Is supplied. IN0 is controlled by a high-speed / low-consumption switching signal HS. At high speed (HS = H), since IN0 to IN3 are VSS, the power of the sense amplifier is always supplied. on the other hand,
During low power consumption (HS = “L”), only the power of the selected sense amplifier is supplied, and the power of the non-selected sense amplifier is VSS. That is, IN1 to IN3 become "H", the high VT transistor Qn20 of the sense amplifier power supply circuit 20 conducts, and VDS1 to VDS3
Is grounded.

The delay signal DLY is "L" during the "L" period of CLK, and when CLK changes from L to H, DLY changes from L to H after being delayed according to the number of delay stages set by the delay circuit 23. .
At this time, the delay circuit 23 is set to a delay time sufficient to read one bit. On the other hand, when the sense amplifier activation signal SA0 and the column decoder Qn1 are selected in response to the address change, the precharge of the selected bit line BL1 is started. When CLK changes from L to H and precharge is completed, word line WL0 is selected, and data is output from SAOUT0 according to the information programmed in the memory cell. At the same time, since the sense amplifier selection signals SA1 to SA3 become “L” in the non-selected sense amplifier, the output of INV11 becomes “H”.
And the sense node N100 by the Nch transistor Qn100.
Becomes “L”. Therefore, "H" is output from SAOUT1 to SAOUT3. Further, the sense amplifier outputs SAOUT0 to SAOUT3 are decoded into 1-bit data by the sense amplifier output decode circuit 21, and the data is output from the output circuit 30. At this time, the data is latched in the output circuit 30 by the delay signal DLY. When DLY changes from L to H, the sense amplifier power supply control circuit 21 changes the input IN0 of the sense amplifier power supply circuit 20 from L to H, and the selected sense amplifier power supply VD
S0 changes from H to L.

As the cycle time for reading becomes longer, power consumption due to the off current of the memory cell increases. Therefore, during low-speed access, setting to the low power consumption mode not only turns off the power supply of the unselected bit sense amplifiers, but also turns off the power supply of the selected sense amplifiers after latching the output data. The off-state current of the cell can be cut, and low power consumption can be realized.

[0034]

As described above, the semiconductor memory device of the present invention controls high-speed access and low power consumption by controlling the rising timing of the word line in accordance with the high-speed / low power consumption switching signal input from the outside. An excellent effect that the operation can be switched can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a read circuit according to Embodiment 1 of the present invention;

FIG. 2 is a read timing chart of the embodiment.

FIG. 3 is a configuration diagram of a read circuit according to (Embodiment 2) of the present invention;

FIG. 4 is a read timing chart of the embodiment.

FIG. 5 is a configuration diagram of a read circuit according to (Embodiment 3) of the present invention;

FIG. 6 is a read timing chart of the embodiment.

FIG. 7 is a configuration diagram of a conventional readout circuit.

FIG. 8 is a conventional read timing chart.

[Explanation of symbols]

Reference Signs List 1 nonvolatile memory cell 2 word line for selecting a row of nonvolatile memory cell 3 bit line for selecting a column of nonvolatile memory cell 4 m rows and n columns composed of nonvolatile memory cells 5 A row decoder for selecting a word line 8 A column decoder for selecting a bit line 10 Sense amplifier 11 Sense amplifier 12 Word line control circuit 20 Inverter composed of high VT transistors 21 Sense amplifier power control circuit 22 Sense amplifier selection circuit 23 Delay circuit 30 Output circuit

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shuji Nakaya 1006 Kazuma Kadoma, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. 5B025 AD02 AD03 AD05 AD06 AD11 AE05 AE06

Claims (5)

[Claims] A memory cell array comprising memory cells arranged in a matrix; a word line for selecting a row of the memory cell array; a bit line for selecting a column of the memory cell array; A semiconductor memory device comprising: a sense amplifier for amplifying information read via a line; and control means for controlling a timing of selecting the word line in response to an operation mode switching signal. 2. The semiconductor device according to claim 1, further comprising a bit line precharge unit for precharging the bit line, wherein the control unit starts selecting a word line during a bit line precharge operation period by the bit line precharge unit. 2. The semiconductor memory device according to claim 1, wherein the first timing and the second timing for starting the selection of the word line after the end of the bit line precharge are selectable. A row decoder for selecting a word line in accordance with a row address; wherein said control means controls said row decoder in response to said operation mode switching signal, and said first timing in a high speed mode. 3. The semiconductor memory device according to claim 2, wherein the selection of a word line is started at a second timing in the low power consumption mode. 4. A memory cell array in which nonvolatile memory cells are arranged in a matrix by a desired storage capacity, a word line connected to a gate of the memory cell array to select a row, and to select the word line. A row decoder, a bit line connected to the drain of the memory cell, a column decoder for selecting the bit line, a plurality of sense amplifiers for amplifying information programmed in the memory cell, and an address. A sense amplifier selection circuit for selecting and outputting a specific bit from the outputs of the plurality of sense amplifiers in accordance with an input signal, wherein the control signal is supplied from a control signal input means and the control signal input means. When the signal is in one state, power is supplied to all of the plurality of sense amplifiers, and when the signal is in the other state, the address input is performed. The semiconductor memory device having a sense amplifier power supply control circuit for supplying power only specific sense amplifier in accordance with the Patent. 5. A memory cell array in which nonvolatile memory cells are arranged in a matrix of a desired storage capacity, a word line connected to a gate of the memory cell array, and a row decoder for selecting the word line. A bit line connected to the drain of the memory cell; a column decoder for selecting the bit line; a plurality of sense amplifiers for amplifying information programmed in the memory cell; and an address input signal. , A sense amplifier selection circuit for selecting and outputting a specific bit from the outputs of the plurality of sense amplifiers, first control signal input means, and having a certain delay value from the first control signal input means. Delay means for generating a data latch signal; and latching an output of the sense amplifier selection circuit by the data latch signal. A second control signal input means; and a control signal supplied from the second control signal input means, the control signal being supplied from the second control signal input means being in one state. A semiconductor amplifier comprising: a sense amplifier power supply control circuit for supplying power to all of the sense amplifiers and supplying power only to a specific sense amplifier in accordance with the address input signal during a delay period set by the delay means in the other state. Storage device.