JP4998495B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a high-speed nonvolatile memory using a memory cell that stores information using phase change resistance.

  Aiming at high-speed and highly integrated non-volatile memory, phase change memory is being developed, and is described in Non-Patent Document 1. In the phase change memory, information is stored by utilizing the fact that a phase change material called a chalcogenide material has different resistance depending on the state. The rewriting of the phase change resistor is performed by changing the state by causing a current to flow to generate heat. Low resistance, also called set operation, is performed by maintaining a relatively low temperature for a sufficient period, and high resistance, called reset operation, is performed by setting the phase change resistance to a relatively high temperature. The phase change material reading operation is performed by passing a current within a range in which the state of the phase change resistance is not changed.

  Non-Patent Document 2 describes the characteristics of phase change resistance. Further, Non-Patent Document 3 describes a memory cell composed of a phase change resistor and an NMOS transistor.

  These documents describe the possibility of non-volatile RAM (Random Access Memory) as well as high-speed ROM (Read-Only Memory), and mention the realization of an integrated memory that combines the functions of ROM and RAM. Has been. FeRAM (Ferroelectric RAM) and MRAM (Magnetic RAM) have also been developed as similar high-speed nonvolatile memories. In FeRAM, it is difficult to reduce the area of the ferroelectric capacitor, and it is difficult to reduce the cell area. Also, since the MRAM has a small magnetoresistance change rate, the read signal amount is small and high-speed read operation is difficult. On the other hand, the phase change memory has a smaller electrode area of the phase change resistance, and the phase change resistance can be changed with a small amount of power, so that scaling is easy. Further, since the phase change resistance changes greatly compared to the magnetic resistance of the MRAM, a high-speed read operation can be realized. For these reasons, realization of a high-speed nonvolatile memory using a phase change memory is expected.

IEE, International Solid-State Circuits Conference, Digest of Technical Papers, pages 202-203 (2002) (2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 202-203.) IEE, International Electron Devices Meeting, Technical Digest, pages 923 to 926 (2002) (2002 IEEE International Electron Devices Meeting, Technical Digest, pp. 923-926) Non-Volatile Semiconductor Memory Workshop, Digest of Technical Papers, Pages 91-92 (2003) (2003 Non-Volatile Semiconductor Memory Workshop, Digest of Technical Papers, pp. 91-92. )

  In order to use the phase change memory as a RAM, the writing time becomes a problem. In reducing the resistance, it is necessary to continue to pass a current through the phase change resistor for a sufficient time, for example, about 20 ns. In addition, after the resistance is increased, an interval must be provided for a sufficient time, for example, about 20 ns, so that the state of the phase change resistance is stabilized before the read operation to the memory cell is performed.

  When phase change memory is introduced as non-volatile RAM, it is desirable to match the specifications of low power RAM so that system changes can be minimized. Currently, low power SRAM (Static RAM) is widely used as the low power RAM. In contrast to the general specifications, simply replacing the SRAM memory array with the phase change memory memory array cannot satisfy the above-described operational problems of the phase change memory. That is, a sufficient time is required for writing to access the same memory cell immediately after the write operation for reducing the resistance, and when reading from the same memory cell immediately after the write operation for increasing the resistance is performed. Since sufficient time for stabilizing the state of the phase change resistance is required, it is difficult to realize high-speed access similar to that of the low-power SRAM.

  SUMMARY OF THE INVENTION An object of the present invention is to realize a highly integrated high-speed nonvolatile memory that enables stable operation of a phase change memory in a short operation cycle time.

  Representative means of the present invention for achieving the above object are arranged at intersections of a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, and a plurality of word lines and the plurality of bit lines. A nonvolatile memory cell array including a plurality of nonvolatile memory cells, a write buffer that supplies a write signal corresponding to the write data to the nonvolatile memory cell array, an input buffer that supplies write data to the write buffer, and an input buffer A write data register connected to hold the write data, and having a dummy write cycle for writing data held in the write data register before power-off.

  A semiconductor device capable of high-speed operation can be realized.

The block diagram which shows the structural example of an asynchronous phase change memory. The figure which shows the structural example of a memory array. The circuit diagram which shows the structural example of a column selector. FIG. 6 is a diagram illustrating a configuration example of a writing circuit. The circuit diagram which shows the structural example of a flag control circuit. The circuit diagram which shows another structural example of a flag control circuit. The figure which shows the example of write-in operation | movement of asynchronous type phase change memory. The figure which shows the example of read-out operation | movement of asynchronous phase change memory. The block diagram which shows the structural example of a synchronous type phase change memory. The figure which shows the example of the write-in operation | movement of synchronous type phase change memory. The figure which shows the example of read-out operation | movement of a synchronous type phase change memory. The block diagram which shows the structural example which provided the register | resistor 2 steps | paragraphs. The block diagram which shows the structural example which performs late write operation. The figure which shows the example of write-in operation | movement of a late write. 1 is a block diagram of a system LSI using a phase change memory. The block diagram of the memory card using a phase change memory.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each functional block in the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). In the drawing, the PMOS transistor is distinguished from the NMOS transistor by attaching an arrow symbol to the body. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally. Unless otherwise noted, the signal low level is set to “0” and the high level is set to “1”.

(First embodiment)
FIG. 1 is a block diagram of a main part of a configuration example of an asynchronous phase change memory according to the present invention. Although not particularly limited, the asynchronous phase change memory operates in accordance with the state of the control signal and also by detecting address transition. Here, the asynchronous phase change memory according to the present invention is characterized in that a write data register DIR, an output data selector DOS, a write address register AR, an address comparator ACP, and a flag register FR are provided. Has command buffer CB, control signal generation circuit CPG, address buffer AB, address transition detection circuit ATD, row predecoder RPD, column predecoder CPD, input buffer DIB, output buffer DOB, sense amplifier block SA, write buffer block WB Further, a row decoder RDEC, a word driver WD, a column decoder CDEC, and a column selector CSEL are provided corresponding to the memory cell array MCA. Although only one memory cell array MCA is shown here, a plurality of memory cell arrays MCA may be provided according to the memory cell capacity. In this figure, a defect relief circuit and the like are omitted for simplicity.

  FIG. 2 shows a configuration example of the memory cell array MCA. Memory cells MC are provided at the intersections of the word lines WL0, WL1, WL2, WL3,... Connected to the word driver WD and the bit lines BL0, BL1, BL2, BL3,. Further, source lines SL01, SL23,... Are provided and connected to the ground voltage VSS. Each memory cell MC includes a phase change resistor PCR and a memory cell transistor MT. One end of the phase change resistor PCR is connected to the bit line, and the other end is connected to one of the source and drain of the memory cell transistor MT. The phase change resistance is made of a chalcogenide material containing germanium, antimony, tellurium, or the like, for example. The other of the source and drain of the memory cell transistor is connected to the source line, and the gate is connected to the word line. Although not shown here for simplicity, a dummy cell for generating a reference signal for reading is also provided if necessary. Further, although an NMOS transistor is shown here as a memory cell transistor, a PMOS transistor or a bipolar transistor can also be used. However, a MOS transistor is desirable from the viewpoint of high integration, and an NMOS transistor having a smaller channel resistance in the on state than the PMOS transistor is preferable. Hereinafter, the operation and the like will be described in terms of voltage when an NMOS transistor is used as the memory cell transistor. The bit line is also called a data line.

  Each circuit block plays the following role. The control signal generation circuit CPG includes a write data register DIR, an output data selector DOS, a write address register AR, an address comparator ACP, a flag register FR, an input buffer DIB, according to an external control signal CMD captured by the command buffer CB. A control signal CTL for controlling the output buffer DOB, the sense amplifier block SA, the write buffer block WB, and the like is generated. The address buffer AB takes in the address ADR from the outside and sends the internal address AI to the write address register AR, the address comparator ACP, the address transition detection circuit ATD, the row predecoder RPD, and the column predecoder CPD. The address transition detection circuit ATD detects a transition of the internal address AI and outputs an address transition signal AT to the control signal generation circuit CPG. Specifically, the logic for detecting the change is taken for each bit of the address, and the logical sum of these is taken as the address transition signal AT. The write address register AR holds an address for performing the write operation until the next write operation, and outputs the held write address AS to the address comparator ACP. The flag register FR outputs a flag FLG indicating whether the retained write address AS retained in the write address register AR is valid. When the flag FLG is “1”, the address comparator ACP compares the internal address AI with the retained write address AS, and outputs an address match signal AH to the sense amplifier block SA and the output data selector DOS. Specifically, for each bit of the address, an exclusive NOR (negative OR is negated) is taken between the internal address AI and the retained write address AS, and the logical product of these is taken as an address match signal ACP. When the flag FLG is “0”, the address match signal AH is set to “0” as a mismatch.

  The row address predecoder XPD predecodes the row address and outputs the row predecode address RPA to the row decoder RDEC. Row decoder RDEC further decodes row predecode address RPA, and word driver WD selectively drives a word line in memory cell array MCA accordingly. The column address predecoder YPD predecodes the column address and outputs the column predecode address CPA to the column decoder CDEC. The column decoder CDEC further decodes the column predecode address CPA, and the column selector CSEL accordingly selectively connects the bit line in the memory cell array MCA to the input / output line IO.

  The input buffer DIB takes in the input / output data DQ with the outside at a desired timing, and sends the input data DI to the write data register DIR and the write buffer block WB. The write data register DIR holds the write data until the next write operation, and outputs the held write data DR to the output data selector DOS. The write buffer block WB drives the input / output line IO according to the input data DI for the write operation. The sense amplifier block SA includes a number of sense amplifiers corresponding to the number of bits operating simultaneously, and for the read operation, amplifies and discriminates the signal of the input / output line IO and outputs read data DO. The output data selector DOS selects either the read data DO or the retained write data DR according to the address match signal AH and outputs it as output data DS. The output buffer DOB outputs the output data DS to the input / output data DQ at a desired timing.

  With the configuration described above, it can be used in the same control as a conventional asynchronous SRAM. Here, the write data is written into the memory cell, stored in the write data register, and held until the next write cycle. If there is a read to the address until the next write cycle, the read access to the memory array is stopped and the data is read from the write data register. Thereby, the period from the writing operation to the reading operation to the same memory cell can be extended without extending the cycle time. Since reading is not performed to the memory cell in an unstable state immediately after writing, stable operation is possible. In other words, the period from increasing the resistance to reading in the same memory cell does not limit the cycle time, and the cycle time can be shortened.

  Hereinafter, characteristic features of the circuit blocks shown in FIG. 1 will be described. FIG. 3 shows a configuration example of the column selector CSEL in FIG. This is an example in which a memory cell is selected from the memory cell array by 2 bits and operated. Even if the number of memory cells to be selected at the same time is different, the same configuration is possible. A column switch CSL2 is provided for every two bit lines, and is controlled by a column selection signal output from the column decoder CDEC to connect two bit lines to the input / output lines IO0 and IO1. The column selection signal is a signal complementary to CO1b and C01t, C23b and C23t,. The column switch CSL2 includes four NMOS transistors MNP0, MNP1, MNS0, and MNS1 and two PMOS transistors MPS0 and MPS1. The NMOS transistors MNP0 and MNP1 hold the unselected bit lines at the ground voltage VSS. The NMOS transistors MMNS0 and MNS1 and the PMOS transistors MPS0 and MPS1 constitute two CMOS pass gates and connect the selected bit line to the input / output lines IO0 and IO1. Thus, by using the CMOS pass gate, the bit line and the input / output line can be connected with a low resistance in a wide voltage range. As a result, the range of the applied voltage of the bit line is widened, and a margin can be ensured when the resistance reduction and the resistance increase in the read operation and the write operation are divided by the value of the current flowing through the phase change resistor.

  FIG. 4 shows a configuration example of the write buffer block WB in FIG. It consists of a write pulse generation circuit WPG and two write buffers WB1. This is also an example in the case where data is simultaneously written in two memory cells in the memory cell array. If the write buffer WB1 is provided according to the number of memory cells to be written at the same time, the number of other memory cells can be accommodated. The write pulse generation circuit WPG generates pulses for lowering resistance and increasing resistance, and outputs the pulses to the write pulse lines WP0 and WP1, respectively. The write buffer WB1 includes two inverters, two two-input NAND gates, two CMOS pass gates including two NMOS transistors MNC1 and MNC0 and two PMOS transistors. It is activated by the write control signal WRIT, and the input / output lines IO0 and IO1 are connected to the write pulse lines WP0 and WP1 according to the write data DI0 and DI1. Here, by using the CMOS pass gate, it is possible to drive to the ground voltage at the fall of the input / output lines IO0 and IO1 by the write pulse generation circuit WPG. This prevents the charge charged in the parasitic capacitance of the input / output lines from being discharged through the bit lines and memory cells, making the pulse waveform of the bit line current fall sharply and realizing a stable write operation. it can.

  FIG. 5 shows a configuration example of the flag register FR in FIG. It consists of a set / reset type latch SRL with two 2-input NOR gates and an inverter. When the power is turned on, the latch SRL is reset by the power-on reset signal POR, and the flag FLG becomes “0”. Thereafter, in the first write operation, the latch SRL is set by the write control signal WRIT, and the flag FLG becomes “1”. This power-on reset signal POR is generated by detecting the rise of the power supply by a known power-on reset circuit.

  In the non-volatile RAM, there may be a case where data written immediately after power-on and before power-off is read. When the power is turned off, the retained write address AS held in the write address register AR and the retained write data DR held in the write data register DIR are reset. For this reason, it is necessary to prevent the retained write data DR from being output data when reading the reset retained address AS. By using the flag register as shown in FIG. 5, the write operation is performed after the power is turned on, and the flag FLG becomes “0” until the hold write address AS and the hold write data DR become valid, and the read operation from the memory cell array is always performed. Can be done.

  If the transistor dimensions of the two NOR gates of the latch SRL are appropriately adjusted, a similar function can be realized even if the ground voltage VSS is input to the latch SRL instead of the power-on reset signal POR. In that case, wiring of the power-on reset signal POR is facilitated. In some cases, a power-on reset circuit is not required.

  FIG. 6 shows another configuration example of the flag register FR. It comprises a set / reset type latch SRL, an inverter, a delay circuit DLS, a shot pulse generation circuit SPG comprising two inverters and a two-input NAND gate, and a delay circuit DLY. The latch SRL is set by the write control signal WRIT, and the flag FLG becomes “1”. Thereafter, the latch SRL is reset by the feedback signal WFB which is the output of the delay circuit DLY, and the flag FLG becomes “0”. The delay circuit DLY has a delay time corresponding to the time until the read operation can be stably performed after applying the high-resistance pulse to the phase change resistor of the memory cell. The delay circuit DLS has a delay time such that the feedback signal WFB has a shorter pulse width than the write control signal WRIT. As a result, it is possible to avoid the possibility of malfunction when the write control signal WRIT and the feedback signal WFB become “1” at the same time.

  The power-on-reset signal used in the flag register shown in Fig. 5 does not change to '1' depending on how the power supply voltage is raised when the power is turned on. There is a risk of sneaking. In the flag register of FIG. 6, since the flag FLG is reset at the time after writing, the flag FLG is surely set to “0” when a certain time elapses after the power is turned on. For this reason, the time until the read operation becomes possible after the power is turned on becomes longer, but there is no risk of malfunction.

  The operation of the asynchronous phase change memory described above will be described below. FIG. 7 shows an example of the timing of the write operation. In response to the transition of the external address ADR, the address transition detection circuit ATD generates a pulse in the address transition signal AT, and the word lines WL (WL0, WL1, WL2, WL3,... In FIG. 2) are switched. When the chip select bar signal CSb and the write enable bar signal WEb, which are part of the control signal CMD, become low level, the write control signal WRIT becomes “1”, and the write operation is performed. As a result, the flag FLG becomes “1”. The selected bit line BL (BL0, BL1, BL2, BL3,... In FIG. 2) is driven in accordance with the input Din to the input / output data DQ. Here, if the input Din is “0”, the bit line BL is driven to the set voltage VSET, but if it is “1”, the bit line BL is kept at the ground voltage VSS. When either the chip select bar signal CSb or the write enable bar signal WEb goes high and the write operation period ends, the write address register AR and write data register DIR store the internal address AI and input data. Capture DI. If the input Din is “1”, the bit line BL is driven to the reset voltage VRST. The write control signal WRIT becomes “0” so that the high resistance pulse has a desired pulse width, the bit line BL is returned to the ground voltage VSS, and the write operation is completed. Although Din is described as being 1 bit here, in the case of a plurality of bits, an operation corresponding to data is performed for each bit. In the following, other operation timings will be similarly simplified and described.

  In general asynchronous SRAM specifications, it is determined that the input Din is valid when the write operation period ends. In the operation of FIG. 7, if the input Din is “0”, the bit line is driven as it is to ensure a low resistance period. On the other hand, if the input Din is '1', the bit line is driven after it is determined that it is valid, the pulse width for driving the bit line is shortened, and the area around the phase change resistance of the selected memory cell is required This prevents the temperature from rising and the cooling time from extending. As a result, a stable write operation can be realized for both “0” and “1”. In addition, by limiting the pulse width for increasing the resistance as described above, an unnecessary write current is not flowed, so that a low-power write operation can be realized.

  FIG. 8 shows an example of the timing of the read operation. Similar to the write operation shown in FIG. 7, the word line WL is switched according to the transition of the external address ADR. When the flag FLG is “1”, the address comparator ACP is activated by the pulse of the address transition signal AT, compares the internal address AI with the held write address AS, and outputs the address match signal AH. When the address match signal AH is '0', the sense amplifier supplies the read voltage VRED to the selected bit line BL through the input / output line IO and the column selector CSEL for a desired period, and the data from the magnitude of the flowing current. Determine. The data selector DOS outputs read data DO, which is the output of the sense amplifier block, as output data DS. When the address match signal AH is “1”, the sense amplifier is kept in a standby state, and the bit line BL is kept at the ground voltage VSS. The data selector DOS outputs the retained write data DR as output data DS. When the chip select bar signal CSb and the output enable bar signal WEb, which are part of the control signal CMD, become low level, the output buffer is activated and the input / output data DQ is output Dout corresponding to the output data DS. To drive. When either the chip select bar signal CSb or the write enable bar signal WEb becomes high level and the read operation period ends, the output buffer DOB enters a high impedance state.

  By controlling the voltage supply to the bit line with the address match signal AH in this way, it is possible to prevent the state from becoming unstable due to the voltage being applied to the phase change resistor immediately after the increase in resistance. Even in the specification of the asynchronous SRAM, the address comparison for each address transition can be controlled by using the address transition detection circuit.

(Second embodiment)
FIG. 9 is a principal block diagram of a configuration example of a synchronous phase change memory according to the present invention. Although not particularly limited, in the synchronous phase change memory, a command or address is fetched based on an external clock signal. In the synchronous phase change memory in the present application, the write data register DIR, the output data selector DOS, the write address register AR, the address comparator ACP, and the flag register FR are provided as in the configuration example of the asynchronous phase change memory shown in FIG. Provided. Has a clock buffer CKB, has a command buffer CB, command decoder CD, address buffer AB, row predecoder RPD, column predecoder CPD, input buffer DIB, output buffer DOB, sense amplifier block SA, write buffer block WB, Further, a row decoder RDEC, a word driver WD, a column decoder CDEC, and a column selector CSEL are provided corresponding to the memory cell array MCA. The memory cell array MCA is configured as shown in FIG. 2, and only one memory cell array MCA is shown in FIG.

  Each circuit block plays the following role. The clock buffer CKB receives the external clock CLK and outputs the internal clock CLKI. Controlled by the internal clock CLKI, the command decoder CD generates a control signal CTL for controlling the operation of each circuit block in accordance with an external control signal CMD taken in by the command buffer CB. The address buffer AB takes in an external address ADR according to the internal clock CLKI and outputs an internal address AI. Similar to the example of the asynchronous phase change memory shown in FIG. 1, the write address register AR holds an address for performing the write operation until the next write operation, and outputs the held write address AS to the address comparator ACP. The flag register FR outputs a flag FLG indicating whether the retained write address AS retained in the write address register AR is valid. When the flag FLG is “1”, the address comparator ACP compares the internal address AI with the retained write address AS, and outputs an address match signal AH to the sense amplifier block SA and the output data selector DOS.

  The row address predecoder XPD outputs the row predecode address RPA to the row decoder RDEC, the row decoder RDEC further decodes the row predecode address RPA, and the word driver WD responds accordingly to the word line in the memory cell array MCA. Is selectively driven. Further, the column address predecoder YPD outputs the column predecode address CPA to the column decoder CDEC, the column decoder CDEC further decodes the column predecode address CPA, and the column selector CSEL correspondingly in the memory cell array MCA The bit line is selectively connected to the input / output line IO.

  The input buffer DIB takes in the data of external input / output data DQ at a timing according to the internal clock CLKI, and sends the input data DI to the write data register DIR and the write buffer block WB. The write data register DIR holds the write data until the next write operation, and outputs the held write data DR to the output data selector DOS. The write buffer block WB drives the input / output line IO according to the input data DI in the write operation. The sense amplifier block SA amplifies and discriminates the signal of the input / output line IO in the read operation, and outputs the read data DO. The output data selector DOS selects either the read data DO or the retained write data DR according to the address match signal AH and outputs it as output data DS. The output buffer DOB outputs the output data DS to the input / output data DQ according to the internal clock CLKI.

  FIG. 10 shows an example of the timing of the write operation. Each time the external clock CLK rises, the command decoder CD determines the control signal CMD. When the write command W is given, the address ADR is taken into the address buffer AB, and the word line WL is selected. The write control signal WRIT becomes “1”, and the flag FLG becomes “1”. The input Din to the input / output data DQ is also taken into the input buffer DIB and drives the selected bit line BL. Here, if the input Din is “0”, the bit line BL is driven to the set voltage VSET, and if it is “1”, the bit line BL is driven to the reset voltage VRST. After driving the bit line for a desired time according to the input Din, the bit line BL is returned to the ground voltage VSS, the word line WL is also returned to the ground voltage VSS, and the write operation is completed.

  Unlike the example of the asynchronous operation shown in FIG. 7, a valid input Din is captured simultaneously with the write command W. Therefore, when the input Din is “0”, the time during which the bit line BL is driven to the set voltage VSET can be lengthened to sufficiently reduce the phase change resistance. Further, when the input Din is “1”, the bit line BL is immediately driven to the reset voltage VRST, so that the high resistance of the phase change resistor can be completed quickly. As a result, the interval between read operations of the cell can be further increased from the increase in resistance.

  FIG. 11 shows an example of the timing of the read operation. Here, a case where the latency is 2 is shown. When the read command R is given, the address ADR is taken into the address buffer AB and the word line WL is selected as in the write operation. Further, the address comparator ACP compares the internal address AI with the retained write address AS and outputs an address match signal AH. Similarly to the operation shown in FIG. 8, when the address match signal AH is “0”, the sense amplifier supplies the read voltage VRED to the selected bit line BL and determines the data from the magnitude of the flowing current. The data selector DOS outputs the read data DO as output data DS. When the address match signal AH is “1”, the sense amplifier is kept in the standby state, the bit line BL is kept at the ground voltage VSS, and the data selector DOS outputs the retained write data DR as the output data DS. In response to the next rising edge of the external clock CLK, the output buffer is activated, and the input / output data DQ is driven to the output Dout corresponding to the output data DS. Further, in response to the next rise, the output buffer DOB enters a high impedance state.

  In this way, timing control such as address comparison is facilitated by controlling the internal circuit at the timing according to the external clock CLK.

  In addition, by using a synchronous memory, it is possible to operate at a high frequency by using a synchronous memory that takes in commands and addresses and inputs / outputs data in synchronization with the external clock CLK. Can be realized. As the phase change memory according to the present invention, various high-speed memory systems developed for SRAM and DRAM can be applied. For example, a burst operation for controlling a continuous operation of a plurality of cycles with a single command can be easily realized.

(Third embodiment)
FIG. 12 is a principal block diagram of another configuration example of the asynchronous phase change memory according to the present invention. The write data register has two stages, the first write data register DIR1 and the second write data register DIR2, and the write address register has two stages, the first write address register AR1 and the second write address register AR2. It is. The address comparator AC2 compares the internal address AI with the first held write address AS1 and the second held write address AS2, and outputs an address match signal AH2 indicating whether they match with each other. The output data selector DS3 is controlled by the address match signal AH2, and selects the read data DO, the first held write data DR1, and the second held write data DR2, and outputs the output data DS. When the internal address AI and the first held write address AS1 match, the first held write data DR1 is selected. If the internal address AI and the first held write address AS1 do not match and the internal address AI and the second held write address AS2 match, the second held write data DR1 is selected. If the internal address AI does not match either the first held write address AS1 or the second held write address AS2, the read data DO is selected. If the write operation is continuously performed on the same address, the first held write address AS1 and the second held write address AS2 are the same, and both the internal address AI may match. In this case, the data is input later. The first retained write data DR1 is selected.

  Similar to the configuration example shown in FIG. 1, flag register FR, command buffer CB, control signal generation circuit CPG2, address buffer AB, address transition detection circuit ATD, row predecoder RPD, column predecoder CPD, input buffer DIB, output A buffer DOB, a sense amplifier block SA, and a write buffer block WB are provided, and a row decoder RDEC, a word driver WD, a column decoder CDEC, and a column selector CSEL are also provided corresponding to the memory cell array MCA. These operate as described for FIG. The write operation and the read operation are performed as shown in FIGS. 7 and 8, similarly to the configuration example shown in FIG.

  In this configuration example, the write data is written into the memory cell, stored in the write data register, and held until the next next write cycle. If there is a read to that address until the next next write cycle, the read access to the memory array is stopped and the data is read from the register. As a result, at least one write cycle is inserted during the period from the write operation to the read operation to the same memory cell. For this reason, the period from the write operation to the read operation to the same memory cell can be made longer than in the configuration example shown in FIG. 1, and a more stable operation is possible.

  Here, the configuration example of the asynchronous phase change memory is shown, but the write data register and the write address register can be formed in two stages even in the synchronous phase change memory as shown in FIG. Even in this case, an effect of further extending the period from the write operation to the read operation to the same memory cell can be obtained.

(Fourth embodiment)
FIG. 13 is a principal block diagram of still another configuration example of the asynchronous phase change memory according to the present invention. Its feature is to perform a write operation called late write. Similar to the configuration example shown in FIG. 12, the write data register is composed of two stages of the first write data register DRL and the second write data register DRD, and the write address register is composed of the first write address register ARL and the second write data. The address register ARD has two stages. However, unlike the configuration example shown in FIG. 12, the first write data register DRL and the first write address register ARL are for the late write operation. An address selector ASL is provided, which outputs the internal address AI in the read operation and the first held write address AL in the write operation to the row predecoder RPD and the column predecoder CPD as the selection address AO. Also, the first held write data DL is sent to the write buffer block WB. Similar to the embodiment shown in FIG. 12, the address comparator AC2 compares the internal address AI with the first holding write address AL and the second holding write address AD, and indicates whether they match each other. The coincidence signal AH2 is output. The output data selector DS3 is controlled by the address match signal AH2, and selects the read data DO, the first held write data DL, and the second held write data DD, and outputs the output data DS. Also, flag register FR, command buffer CB, control signal generation circuit CPGL, address buffer AB, address transition detection circuit ATD, row predecoder RPD, column predecoder CPD, input buffer DIB, output buffer DOB, sense amplifier block SA, write A buffer block WB is provided, and a row decoder RDEC, a word driver WD, a column decoder CDEC, and a column selector CSEL are also provided corresponding to the memory cell array MCA. These operate as described for FIG.

  FIG. 14 shows an example of the timing of the write operation. In response to the transition of the external address ADR, a pulse is generated in the address transition signal AT, the internal address AI and the selection address AO are switched, and the word line WL is switched. Here, when the chip select bar signal CSb and the write enable bar signal WEb, which are part of the control signal CMD, become low level, the write control signal WRIT becomes “1”, and the write operation is performed. As a result, the address selector ASL outputs the first held write address AL as the selected address AO, and the word line WL is switched again. Further, the flag FLG is “1”. The write buffer block WB drives the selected bit line BL according to the first held write data DL. If the retained write data DL is “0”, the bit line BL is driven to the set voltage VSET, and if it is “1”, the bit line BL is driven to the reset voltage VRST for a desired time. When either the chip select bar signal CSb or the write enable bar signal WEb goes high and the write operation period ends, the first write address register ARL and the first write data register DRL The internal address AI and the input data DI are captured, and the second write address register ARD and the second write data register DRD capture the first retained write address AL and the first retained write data DL. The bit line BL is returned to the ground voltage VSS, and the write operation is completed.

  Even when it is determined that the input Din is valid when the period of the write operation ends, it is possible to write the determined data by performing such a late write operation. Therefore, the writing time to the memory cell can be lengthened and the period of low resistance can be lengthened. In addition, the phase change resistance can be increased quickly, and the interval between read operations of the cell can be increased due to the increased resistance. As a result, a stable write operation can be realized for both “0” and “1”.

  The read operation is performed at the timing as shown in FIG. 8, similarly to the configuration example shown in FIG. Even if the late write operation is introduced, the speed penalty for the read operation is small.

  In the configuration for performing such a late write operation, the register information is lost by the power shutdown, so that the write data of the write cycle before the power shutdown is not stored as it is. Therefore, it is desirable to determine that the dummy write cycle is inserted before the power is shut down as a specification.

  When the time from the increase in resistance to the reading can be short, it is possible to perform only the late write operation without holding the data after writing to the memory cell. In that case, the second write data register DRD and the second write address register ARD are deleted. Further, the address comparator AC2 compares the internal address AI with the first held write address AL, the output data selector DS3 is selected from the read data DO and the first held write data DL, and the output data Change to output DS. With such a configuration, compared to the configuration shown in FIG. 13, the control is simpler, and the current consumed by the register or the like can be reduced to reduce the power consumption.

(Fifth embodiment)
Examples of application of the phase change memory according to the present invention will be described below. FIG. 15 shows a configuration example of a flash memory card. The flash memory card FMC includes a plurality of large-capacity flash memories LMF, a memory controller MCT, and a phase change memory PMC. The memory controller MCT uses the phase change memory PMC as a buffer to exchange signals with the outside to control the large-capacity flash memory LMF.

  By using a high-speed nonvolatile memory such as a phase change memory as a buffer, data can be retained even if the power is turned off before the writing to the large-capacity flash memory is completed. As a result, it becomes possible to remove the flash memory card FMC from the device immediately after data transfer during writing, improving usability.

  The phase change memory according to the present invention may have various other applications. For example, it is possible to replace a NOR flash memory and a low power SRAM used in a mobile phone with a single chip. In this case, the cost can be reduced and the mounting volume can be reduced.

(Sixth embodiment)
The phase change memory according to the present invention can also be applied as a mixed memory. FIG. 16 shows a configuration example of the system LSI. The system LSI chip SOC includes a processor module CPU, a cache memory module CM, a peripheral module PRC, and a power supply control module PMU.

  As shown in FIG. 2, in the phase change memory, a memory cell can be configured with one phase change resistor and one transistor, so that the cell area can be reduced and a large-capacity on-chip memory can be realized. Moreover, since it is non-volatile, the power supply can be shut down by the power supply control module PMU while retaining data during standby. At this time, since it is not necessary to save data to an external memory, there is no power overhead associated with data transfer, and fine power control that cuts off the power supply in a short time is possible. Such a low power system LSI is suitable for mobile devices such as mobile phones.

  Among the inventions of the present application, a typical effect is that in a phase change memory in which data is written to a memory cell by passing a current through the phase change resistor, the memory cell can reduce the phase change resistance without increasing the cycle time. And the period from the write operation to increase the phase change resistance to the read operation to the memory cell can be extended. As a result, a stable write operation becomes possible. In other words, the cycle time for realizing a stable write operation can be shortened. Therefore, a semiconductor device having a high-speed nonvolatile memory can be realized.

  AB ... Address buffer, AC2, ACP ... Address comparator, ADD ... Address signal from outside, AH, AH2 ... Address match signal, AI ... Internal address, AO ... Selected address, AR, AR1, AR2, ARL, ARD ... Write Address register, AS, AS1, AS2, AL, AD ... holding write address, ASL ... address selector, AT ... address transition signal, ATD ... address transition detection circuit, BL, BL0-BL3 ... bit line, CB ... command buffer, CD ... Command decoder, CDEC ... Column decoder, CLK ... External clock, CKB ... Clock buffer, CLKI ... Internal clock, CM ... Cache memory module, CMD ... External control signal, CPA ... Column predecode address, CPG, CPG2, CPGL …control Signal generation circuit, CPD ... column predecoder, CPU ... processor module, CSEL ... column selector, CSL2 ... column switch, CTL ... control signal, DI ... input data, DIB ... input buffer, DIR, DIR1, DIR2, DRL, DRD ... Write data register, DLS, DLY ... delay circuit, DO ... read data, DOB ... output buffer, DOD ... data control circuit, DOS, DS3 ... output data selector, DQ ... external input / output data, DR, DR1, DR2, DL, DD ... retained write data, DS ... output data, FLG ... flag, FMC ... flash memory card, FR ... flag register, IO, IO0, IO1 ... I / O line, LMF ... large capacity flash memory, MC ... memory cell, MCA ... Memory cell array, MCT ... Memory co Controller, PCM ... Phase change memory module, PCR ... Phase change resistance, PMC ... Phase change memory, PMU ... Power supply control module, PRC ... Peripheral module, RDEC ... Row decoder, RPA ... Row predecode address, RPD ... Row predecoder, SL01, SL23 ... Source line, SA ... Sense amplifier block, SOC ... System LSI chip, SPG ... Shot pulse generation circuit, SRL ... Set / reset type latch, VSS ... Ground voltage, WB ... Write buffer block, WB1 ... Write buffer, WD: Word driver, WL, WL0 to WL3: Word line, WPG: Write pulse generation circuit, WRIT: Write control signal.

Claims (4)

A plurality of nonvolatile memories disposed at intersections of a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, and the plurality of word lines and the plurality of bit lines, each having a phase change resistance A non-volatile memory cell array including cells, and a write data register for holding write data for writing to the non-volatile memory cells,
And the write data register for holding data input from the outside,
Connected to said nonvolatile memory cell array, the data held in the write data register includes a write buffer to be supplied to said nonvolatile memory cell array,
In the first write cycle, the write data register holds data input from the outside,
In a second write cycle following the first write cycle, the write data register, the data held is output to the write buffer, the write buffer, prior Symbol nonvolatile data output from said write data register Supply to the memory cell array,
In order to write the data held in the write data register to the nonvolatile memory cell before the power supply to the write data register is stopped, the write data register It outputs the write buffer, the write buffer to a semiconductor device and executes a dummy write cycle for supplying data output from the write data register to the nonvolatile memory cell array. In claim 1,
An address register for holding an access address corresponding to the data held in the write data register;
A comparator for comparing the access address held in the address register with the access address input from the outside of the semiconductor device;
In a read cycle, the access address held in the address register is compared with the access address input from the outside of the semiconductor device, and if they match, the semiconductor device outputs the data held in the write data register A semiconductor device comprising: In claim 1 or 2,
A semiconductor device further comprising a flag register indicating whether or not the data held in the write data register is valid. In any one of Claims 1 thru | or 3,
A processor module;
A power control module for controlling power supply to the nonvolatile memory cell array, the write data register, the write buffer, and the processor module;
The non-volatile memory cell array, the write data register, the write buffer, and the processor module are formed in one semiconductor chip.

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